From 653b2f88089407e4a714783985a9bc1c54490c64 Mon Sep 17 00:00:00 2001 From: milesdig Date: Mon, 22 May 2017 04:03:42 +0100 Subject: [PATCH] Got branch working --- Project/Project/ControlFSM.vhd | 18 +++++-- Project/Project/ControlUnit.vhd | 10 ++-- Project/Project/Decoder.vhd | 57 +++++++++------------- Project/Project/DualPortMemory.vhd | 91 +++++++++++++++++++----------------- Project/Project/ProcessorColors.wcfg | 26 +++++------ Project/Project/Project.xise | 66 +++++++++++++------------- Project/Project/Sequencer.vhd | 50 ++++++++++++++------ Project/simpleprogram.txt | 3 ++ 8 files changed, 171 insertions(+), 150 deletions(-) create mode 100644 Project/simpleprogram.txt diff --git a/Project/Project/ControlFSM.vhd b/Project/Project/ControlFSM.vhd index 78f5844..3d3db85 100644 --- a/Project/Project/ControlFSM.vhd +++ b/Project/Project/ControlFSM.vhd @@ -14,7 +14,7 @@ entity ControlFSM is rst : in STD_LOGIC; opcode : in STD_LOGIC_Vector(5 downto 0); S : out STD_LOGIC_VECTOR (4 downto 1); - FETCH : out STD_LOGIC + STAGE : out STD_LOGIC_VECTOR(8 downto 0) ); end ControlFSM; @@ -81,11 +81,20 @@ begin end case; end process; - FETCH <= '1' when curr_state = S0 else '0'; + STAGE(0) <= '1' when curr_state = S0 else '0'; + STAGE(1) <= '1' when curr_state = S1 else '0'; + STAGE(2) <= '1' when curr_state = S2 else '0'; + STAGE(3) <= '1' when curr_state = S3 else '0'; + STAGE(4) <= '1' when curr_state = S4 else '0'; + STAGE(5) <= '1' when curr_state = S5 else '0'; + STAGE(6) <= '1' when curr_state = S6 else '0'; + STAGE(7) <= '1' when curr_state = S7 else '0'; + STAGE(8) <= '1' when curr_state = S8 else '0'; S(1) <= '-' when curr_state = S0 else - '-' when curr_state = S1 else + '-' when curr_state = S1 and optype /= "11" else + '1' when curr_state = S1 and optype = "11" else '0' when curr_state = S2 else '-' when curr_state = S3 else '1' when curr_state = S4 else @@ -97,7 +106,8 @@ begin S(2) <= '1' when curr_state = S0 else - '-' when curr_state = S1 else + '-' when curr_state = S1 and optype /= "11" else + '1' when curr_state = S1 and optype = "11" else '0' when curr_state = S2 else '-' when curr_state = S3 else '0' when curr_state = S4 else diff --git a/Project/Project/ControlUnit.vhd b/Project/Project/ControlUnit.vhd index c2031f5..21a57b6 100644 --- a/Project/Project/ControlUnit.vhd +++ b/Project/Project/ControlUnit.vhd @@ -44,23 +44,24 @@ end ControlUnit; architecture Behavioral of ControlUnit is signal OPCODE : STD_LOGIC_VECTOR (5 downto 0); - signal FETCH : STD_LOGIC; - + + signal STAGE : STD_LOGIC_VECTOR (8 downto 0); begin + Inst_ControlFSM: entity work.ControlFSM PORT MAP( clk => clk , rst => rst, opcode => OPCODE , S => S, - FETCH => FETCH + STAGE => STAGE ); Inst_Sequencer: entity work.Sequencer PORT MAP( clk => clk , rst => rst, en => en, - FETCH => FETCH, + STAGE => STAGE, instr => instr , PC_plus => PC_Plus, flags => Flags, @@ -70,6 +71,7 @@ begin Inst_Decoder_Block: entity work.Decoder_Block PORT MAP( instr => instr, + STAGE => STAGE, OPCODE => OPCODE, RA => RA, RB => RB, diff --git a/Project/Project/Decoder.vhd b/Project/Project/Decoder.vhd index 4b772d0..55a5d29 100644 --- a/Project/Project/Decoder.vhd +++ b/Project/Project/Decoder.vhd @@ -1,42 +1,26 @@ ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 21:58:01 05/18/2017 --- Design Name: --- Module Name: Decoder_Block - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- library IEEE; +USE ieee.numeric_std.ALL; use IEEE.STD_LOGIC_1164.ALL; entity Decoder_Block is - Port ( instr : in STD_LOGIC_VECTOR (31 downto 0); - - OPCODE : out STD_LOGIC_VECTOR(5 downto 0); + Port ( + instr : in STD_LOGIC_VECTOR (31 downto 0); + + STAGE : in STD_LOGIC_VECTOR(8 downto 0); + OPCODE : out STD_LOGIC_VECTOR(5 downto 0); + + RA : out STD_LOGIC_VECTOR (4 downto 0); + RB : out STD_LOGIC_VECTOR (4 downto 0); + WA : out STD_LOGIC_VECTOR (4 downto 0); + + MA : out STD_LOGIC_VECTOR (15 downto 0); + IMM : out STD_LOGIC_VECTOR (15 downto 0); + + AL : out STD_LOGIC_VECTOR (3 downto 0); + SH : out STD_LOGIC_VECTOR (3 downto 0); - RA : out STD_LOGIC_VECTOR (4 downto 0); - RB : out STD_LOGIC_VECTOR (4 downto 0); - WA : out STD_LOGIC_VECTOR (4 downto 0); - - MA : out STD_LOGIC_VECTOR (15 downto 0); - IMM : out STD_LOGIC_VECTOR (15 downto 0); - - AL : out STD_LOGIC_VECTOR (3 downto 0); - SH : out STD_LOGIC_VECTOR (3 downto 0); - - WEN : out STD_LOGIC; - OEN : out STD_LOGIC + WEN : out STD_LOGIC; + OEN : out STD_LOGIC ); end Decoder_Block; @@ -59,8 +43,8 @@ begin instr(20 downto 16) when OPCODE_int(5 downto 4) = "00" else instr(4 downto 0); - InstrInternal1(9 downto 0) <= instr(19 downto 10); - InstrInternal2(8 downto 0) <= instr(24 downto 16); + InstrInternal1 <= std_logic_vector(resize(signed(instr(19 downto 10)), 16)); + InstrInternal2 <= std_logic_vector(resize(signed(instr(24 downto 16)), 16)); IMM_internal <= InstrInternal1 when OPCODE_int(5 downto 4) = "10" and OPCODE_int(1 downto 0) = "11" else @@ -71,6 +55,7 @@ begin MA <= IMM_internal; AL <= + "1010" when STAGE(1) = '1' else -- calc branch "0100" when OPCODE_int(5 downto 3) = "010" and OPCODE_int(1 downto 0) = "01" else -- A & B "0101" when OPCODE_int(5 downto 3) = "010" and OPCODE_int(1 downto 0) = "10" else -- A || B "0110" when OPCODE_int(5 downto 3) = "010" and OPCODE_int(1 downto 0) = "11" else -- A xor B diff --git a/Project/Project/DualPortMemory.vhd b/Project/Project/DualPortMemory.vhd index 750fd10..4ce2afa 100644 --- a/Project/Project/DualPortMemory.vhd +++ b/Project/Project/DualPortMemory.vhd @@ -20,49 +20,54 @@ architecture Behavioral of DualPortMemory is type ram_type is array (0 to (2**7)-1) of std_logic_vector(31 downto 0); signal ram : ram_type := ( 0 => X"00000000", - 1 => X"8407C00F", - 2 => X"C1FF800F", - 3 => X"18AD9C1F", - 4 => X"00000001", - 5 => X"20000021", - 6 => X"CC02801F", - 7 => X"980003E1", - 8 => X"20000021", - 9 => X"240003FF", - 10 => X"DDFE0000", - 11 => X"84019002", - 12 => X"5400101E", - 13 => X"880003C3", - 14 => X"8C000FC4", - 15 => X"5BFFFC1D", - 16 => X"80000007", - 17 => X"500043A5", - 18 => X"50000486", - 19 => X"C0010006", - 20 => X"00038067", - 21 => X"64010084", - 22 => X"60010063", - 23 => X"240000A5", - 24 => X"C5FD0005", - 25 => X"94000007", - 26 => X"680900E7", - 27 => X"6C0300E7", - 28 => X"400000E8", - 29 => X"4C0403A8", - 30 => X"14038109", - 31 => X"1C00052A", - 32 => X"D004800A", - 33 => X"C004000A", - 34 => X"1800294B", - 35 => X"C003000B", - 36 => X"480580EC", - 37 => X"9C00040C", - 38 => X"4405818C", - 39 => X"C800800C", - 40 => X"DC000000", - 41 => X"DC000000", - 42 => X"940FFC07", - 43 => X"DC000000", + 1 => X"00000000", + 2 => X"CDFF8000", + 3 => X"00000000", + 4 => X"C1FF8000", +-- 0 => X"00000000", +-- 1 => X"8407C00F", +-- 2 => X"C1FF800F", +-- 3 => X"18AD9C1F", +-- 4 => X"00000001", +-- 5 => X"20000021", +-- 6 => X"CC02801F", +-- 7 => X"980003E1", +-- 8 => X"20000021", +-- 9 => X"240003FF", +-- 10 => X"DDFE0000", +-- 11 => X"84019002", +-- 12 => X"5400101E", +-- 13 => X"880003C3", +-- 14 => X"8C000FC4", +-- 15 => X"5BFFFC1D", +-- 16 => X"80000007", +-- 17 => X"500043A5", +-- 18 => X"50000486", +-- 19 => X"C0010006", +-- 20 => X"00038067", +-- 21 => X"64010084", +-- 22 => X"60010063", +-- 23 => X"240000A5", +-- 24 => X"C5FD0005", +-- 25 => X"94000007", +-- 26 => X"680900E7", +-- 27 => X"6C0300E7", +-- 28 => X"400000E8", +-- 29 => X"4C0403A8", +-- 30 => X"14038109", +-- 31 => X"1C00052A", +-- 32 => X"D004800A", +-- 33 => X"C004000A", +-- 34 => X"1800294B", +-- 35 => X"C003000B", +-- 36 => X"480580EC", +-- 37 => X"9C00040C", +-- 38 => X"4405818C", +-- 39 => X"C800800C", +-- 40 => X"DC000000", +-- 41 => X"DC000000", +-- 42 => X"940FFC07", +-- 43 => X"DC000000", others => X"00000000" ); begin diff --git a/Project/Project/ProcessorColors.wcfg b/Project/Project/ProcessorColors.wcfg index 200fadb..e98de32 100644 --- a/Project/Project/ProcessorColors.wcfg +++ b/Project/Project/ProcessorColors.wcfg @@ -359,7 +359,7 @@ imm[15:0] imm[15:0] - HEXRADIX + SIGNEDDECRADIX m_a[15:0] @@ -567,10 +567,6 @@ Sequencer label - - clk - clk - rst rst @@ -580,11 +576,6 @@ instr[31:0] HEXRADIX - - pc_plus[7:0] - pc_plus[7:0] - HEXRADIX - flags[7:0] flags[7:0] @@ -605,6 +596,11 @@ pc_internal[7:0] HEXRADIX + + pc_plus[7:0] + pc_plus[7:0] + HEXRADIX + pc_next[7:0] pc_next[7:0] @@ -614,6 +610,10 @@ cond_met cond_met + + clk + clk + opcode[5:0] opcode[5:0] @@ -622,7 +622,7 @@ cond[2:0] cond[2:0] - HEXRADIX + BINARYRADIX ClockDivider @@ -648,10 +648,6 @@ s[4:1] s[4:1] - - fetch - fetch - curr_state curr_state diff --git a/Project/Project/Project.xise b/Project/Project/Project.xise index 26fd5a4..b1b5726 100644 --- a/Project/Project/Project.xise +++ b/Project/Project/Project.xise @@ -16,28 +16,28 @@ - - + + - - + + - - + + - + - - + + - - + + @@ -46,22 +46,22 @@ - - + + - - + + - + - - + + @@ -70,8 +70,8 @@ - - + + @@ -80,8 +80,8 @@ - - + + @@ -90,8 +90,8 @@ - - + + @@ -100,8 +100,8 @@ - - + + @@ -110,11 +110,11 @@ - - + + - + @@ -374,8 +374,8 @@ - - + + @@ -393,7 +393,7 @@ - + @@ -443,7 +443,7 @@ - + diff --git a/Project/Project/Sequencer.vhd b/Project/Project/Sequencer.vhd index 5706aad..2ac7e1b 100644 --- a/Project/Project/Sequencer.vhd +++ b/Project/Project/Sequencer.vhd @@ -9,7 +9,7 @@ entity Sequencer is clk : in STD_LOGIC; rst : in STD_LOGIC; en : in STD_LOGIC; - FETCH : in STD_LOGIC; + STAGE : in STD_LOGIC_VECTOR(8 downto 0); instr : in STD_LOGIC_VECTOR (31 downto 0); -- instruction PC_plus : in STD_LOGIC_VECTOR (7 downto 0); -- PC + offset flags : in STD_LOGIC_VECTOR (7 downto 0); -- flags @@ -22,47 +22,67 @@ architecture Behavioral of Sequencer is signal PC_internal : STD_LOGIC_VECTOR (7 downto 0) := (others => '0'); -- current internal PC state signal PC_next : STD_LOGIC_VECTOR (7 downto 0); -- the next PC state - signal cond_met : STD_LOGIC; -- weather the branching condition has been met + signal cond_met : STD_LOGIC; -- whether the branching condition has been met signal opcode : STD_LOGIC_VECTOR(5 downto 0); -- the opcode part of the instruction signal cond : STD_LOGIC_VECTOR(2 downto 0); -- the condition part of the opcode + signal cond_met_i : STD_LOGIC; begin opcode <= instr(31 downto 26); cond <= opcode(2 downto 0); cond_met <= - '1' when cond = "000" and flags(0) = '1' else -- ra = 0 - '1' when cond = "001" and flags(1) = '1' else -- ra != 0 - '1' when cond = "010" and flags(2) = '1' else -- ra = 1 - '1' when cond = "011" and flags(4) = '1' else -- ra < 0 - '1' when cond = "100" and flags(3) = '1' else -- ra > 0 - '1' when cond = "101" and flags(6) = '1' else -- ra <= 0 - '1' when cond = "110" and flags(5) = '1' else -- ra >= 0 + '1' when cond = "000" and flags(0) = '1' and STAGE(8) = '1' else -- ra = 0 + '1' when cond = "001" and flags(1) = '1' and STAGE(8) = '1' else -- ra != 0 + '1' when cond = "010" and flags(2) = '1' and STAGE(8) = '1' else -- ra = 1 + '1' when cond = "011" and flags(4) = '1' and STAGE(8) = '1' else -- ra < 0 + '1' when cond = "100" and flags(3) = '1' and STAGE(8) = '1' else -- ra > 0 + '1' when cond = "101" and flags(6) = '1' and STAGE(8) = '1' else -- ra <= 0 + '1' when cond = "110" and flags(5) = '1' and STAGE(8) = '1' else -- ra >= 0 '1' when cond = "111" else -- jump '0'; PC <= PC_internal; MIA <= PC_internal; - PC_next <= + --PC_next <= -- if its a branch instruction and the condition is met then do PC_plus - PC_plus when opcode(5 downto 4) = "11" and cond_met = '1' else + --PC_plus when opcode(5 downto 4) = "11" and cond_met = '1' else -- else incriment the value - std_logic_vector(unsigned(PC_internal) + 1); + --std_logic_vector(unsigned(PC_internal) + 1); -- The Instruction register update process - register_proc : process(clk, rst, en, FETCH) is + register_proc : process(clk, rst, en, STAGE, cond_met, opcode) is begin if rising_edge(clk) then if rst = '1' then PC_internal <= (others => '0'); - elsif en = '1' and FETCH = '1' then - PC_internal <= PC_next; + elsif en = '1' and STAGE(0) = '1' then + --PC_internal <= PC_next; + if opcode(5 downto 4) = "11" and cond_met_i = '1' then + PC_internal <= PC_next; + else + PC_internal <= std_logic_vector(unsigned(PC_internal) + 1); + end if; end if; end if; end process; + + stick_proc : process(clk, PC_plus, STAGE) is + begin + if rising_edge(clk) and STAGE(8) = '1' then + PC_next <= PC_plus; + end if; + end process; + met_proc : process(clk, cond_met, STAGE) is + begin + if rising_edge(clk) and STAGE(8) = '1' then + cond_met_i <= cond_met; + end if; + end process; + end Behavioral; diff --git a/Project/simpleprogram.txt b/Project/simpleprogram.txt new file mode 100644 index 0000000..6f6ba93 --- /dev/null +++ b/Project/simpleprogram.txt @@ -0,0 +1,3 @@ +nop +nop +jmp -1 \ No newline at end of file -- 2.11.4.GIT