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Added report 1 to repo
2017-04-26 milesdigAdded report 1 to repo
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2017-04-26 milesdigLast few changes before subbmission and screen shots
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2017-04-26 milesdigCleaned up ALU code and added failing test
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2017-04-26 milesdigfinished up Regs lab ready for submistion
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2017-02-24 milesdigLast few changes before subbmission and screen shots
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2017-02-24 milesdigCleaned up ALU code and added failing test
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2017-02-24 milesdigLab One all working
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2017-02-23 milesdig Committer: Zak West <zraw500@its.york.ac.uk>
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2017-02-22 milesdigAdded 'xor' , 'not' and 'sl' tests. Fixed issue with...
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2017-02-22 milesdigBetter error reporting and tests for 'and' and 'or'
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2017-02-19 milesdigMerge pull request #5 from zwrawr/zwrawr-lab1-add-testbench
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2017-02-18 milesdigFixed overflow flag and started test bench
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2017-02-18 milesdigAdded some commenting
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2017-02-17 milesdigMerge pull request #4 from zwrawr/zwrawr-update-lab-one
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2017-02-17 milesdigDid some more work on lab one
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2017-02-17 milesdigMerge pull request #3 from zwrawr/zwrawr-start-lab-one
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2017-02-16 milesdig\# Added lab one folder and Xilinx ise project
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2017-02-15 milesdigMerge pull request #2 from zwrawr/zwrawr-restructure
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2017-02-15 milesdigRestructures folders
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2017-02-15 milesdigMerge pull request #1 from zwrawr/zwrawr-add-instruction-set
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2017-02-15 milesdigStared on the instruction set
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2017-02-15 milesdigInitial commit
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Computer Architectures project to design a 16/32 bit microprocessor in VHDL