?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Cygwin: fhandler_virtual: move fileid to path_conv member
[newlib-cygwin.git] / libgloss / bfin / include / defBF537.h
blob29fa7e9348f2dfd2b4973c9c2fe63019b8f2a85c
1 /*
2 * The authors hereby grant permission to use, copy, modify, distribute,
3 * and license this software and its documentation for any purpose, provided
4 * that existing copyright notices are retained in all copies and that this
5 * notice is included verbatim in any distributions. No written agreement,
6 * license, or royalty fee is required for any of the authorized uses.
7 * Modifications to this software may be copyrighted by their authors
8 * and need not follow the licensing terms described here, provided that
9 * the new terms are clearly indicated on the first page of each file where
10 * they apply.
11 */
12
13 /*
14 ** Copyright (C) 2004-2008 Analog Devices Inc., All Rights Reserved.
15 **
16 ************************************************************************************
17 **
18 ** This include file contains a list of macro "defines" to enable the programmer
19 ** to use symbolic names for register-access and bit-manipulation.
20 **
21 **/
22 #ifndef _DEF_BF537_H
23 #define _DEF_BF537_H
24
25 /* Include all Core registers and bit definitions */
26 #include <def_LPBlackfin.h>
27
28 /* Include all MMR and bit defines common to BF534 */
29 #include <defBF534.h>
30
31 #ifdef _MISRA_RULES
32 #pragma diag(push)
33 #pragma diag(suppress:misra_rule_19_4)
34 #pragma diag(suppress:misra_rule_19_7)
35 #pragma diag(suppress:misra_rule_19_11)
36 #endif /* _MISRA_RULES */
37
38
39 /************************************************************************************
40 ** Define EMAC Section Unique to BF536/BF537
41 *************************************************************************************/
42
43 /* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */
44 #define EMAC_OPMODE 0xFFC03000 /* Operating Mode Register */
45 #define EMAC_ADDRLO 0xFFC03004 /* Address Low (32 LSBs) Register */
46 #define EMAC_ADDRHI 0xFFC03008 /* Address High (16 MSBs) Register */
47 #define EMAC_HASHLO 0xFFC0300C /* Multicast Hash Table Low (Bins 31-0) Register */
48 #define EMAC_HASHHI 0xFFC03010 /* Multicast Hash Table High (Bins 63-32) Register */
49 #define EMAC_STAADD 0xFFC03014 /* Station Management Address Register */
50 #define EMAC_STADAT 0xFFC03018 /* Station Management Data Register */
51 #define EMAC_FLC 0xFFC0301C /* Flow Control Register */
52 #define EMAC_VLAN1 0xFFC03020 /* VLAN1 Tag Register */
53 #define EMAC_VLAN2 0xFFC03024 /* VLAN2 Tag Register */
54 #define EMAC_WKUP_CTL 0xFFC0302C /* Wake-Up Control/Status Register */
55 #define EMAC_WKUP_FFMSK0 0xFFC03030 /* Wake-Up Frame Filter 0 Byte Mask Register */
56 #define EMAC_WKUP_FFMSK1 0xFFC03034 /* Wake-Up Frame Filter 1 Byte Mask Register */
57 #define EMAC_WKUP_FFMSK2 0xFFC03038 /* Wake-Up Frame Filter 2 Byte Mask Register */
58 #define EMAC_WKUP_FFMSK3 0xFFC0303C /* Wake-Up Frame Filter 3 Byte Mask Register */
59 #define EMAC_WKUP_FFCMD 0xFFC03040 /* Wake-Up Frame Filter Commands Register */
60 #define EMAC_WKUP_FFOFF 0xFFC03044 /* Wake-Up Frame Filter Offsets Register */
61 #define EMAC_WKUP_FFCRC0 0xFFC03048 /* Wake-Up Frame Filter 0,1 CRC-16 Register */
62 #define EMAC_WKUP_FFCRC1 0xFFC0304C /* Wake-Up Frame Filter 2,3 CRC-16 Register */
63
64 #define EMAC_SYSCTL 0xFFC03060 /* EMAC System Control Register */
65 #define EMAC_SYSTAT 0xFFC03064 /* EMAC System Status Register */
66 #define EMAC_RX_STAT 0xFFC03068 /* RX Current Frame Status Register */
67 #define EMAC_RX_STKY 0xFFC0306C /* RX Sticky Frame Status Register */
68 #define EMAC_RX_IRQE 0xFFC03070 /* RX Frame Status Interrupt Enables Register */
69 #define EMAC_TX_STAT 0xFFC03074 /* TX Current Frame Status Register */
70 #define EMAC_TX_STKY 0xFFC03078 /* TX Sticky Frame Status Register */
71 #define EMAC_TX_IRQE 0xFFC0307C /* TX Frame Status Interrupt Enables Register */
72
73 #define EMAC_MMC_CTL 0xFFC03080 /* MMC Counter Control Register */
74 #define EMAC_MMC_RIRQS 0xFFC03084 /* MMC RX Interrupt Status Register */
75 #define EMAC_MMC_RIRQE 0xFFC03088 /* MMC RX Interrupt Enables Register */
76 #define EMAC_MMC_TIRQS 0xFFC0308C /* MMC TX Interrupt Status Register */
77 #define EMAC_MMC_TIRQE 0xFFC03090 /* MMC TX Interrupt Enables Register */
78
79 #define EMAC_RXC_OK 0xFFC03100 /* RX Frame Successful Count */
80 #define EMAC_RXC_FCS 0xFFC03104 /* RX Frame FCS Failure Count */
81 #define EMAC_RXC_ALIGN 0xFFC03108 /* RX Alignment Error Count */
82 #define EMAC_RXC_OCTET 0xFFC0310C /* RX Octets Successfully Received Count */
83 #define EMAC_RXC_DMAOVF 0xFFC03110 /* Internal MAC Sublayer Error RX Frame Count */
84 #define EMAC_RXC_UNICST 0xFFC03114 /* Unicast RX Frame Count */
85 #define EMAC_RXC_MULTI 0xFFC03118 /* Multicast RX Frame Count */
86 #define EMAC_RXC_BROAD 0xFFC0311C /* Broadcast RX Frame Count */
87 #define EMAC_RXC_LNERRI 0xFFC03120 /* RX Frame In Range Error Count */
88 #define EMAC_RXC_LNERRO 0xFFC03124 /* RX Frame Out Of Range Error Count */
89 #define EMAC_RXC_LONG 0xFFC03128 /* RX Frame Too Long Count */
90 #define EMAC_RXC_MACCTL 0xFFC0312C /* MAC Control RX Frame Count */
91 #define EMAC_RXC_OPCODE 0xFFC03130 /* Unsupported Op-Code RX Frame Count */
92 #define EMAC_RXC_PAUSE 0xFFC03134 /* MAC Control Pause RX Frame Count */
93 #define EMAC_RXC_ALLFRM 0xFFC03138 /* Overall RX Frame Count */
94 #define EMAC_RXC_ALLOCT 0xFFC0313C /* Overall RX Octet Count */
95 #define EMAC_RXC_TYPED 0xFFC03140 /* Type/Length Consistent RX Frame Count */
96 #define EMAC_RXC_SHORT 0xFFC03144 /* RX Frame Fragment Count - Byte Count x < 64 */
97 #define EMAC_RXC_EQ64 0xFFC03148 /* Good RX Frame Count - Byte Count x = 64 */
98 #define EMAC_RXC_LT128 0xFFC0314C /* Good RX Frame Count - Byte Count 64 < x < 128 */
99 #define EMAC_RXC_LT256 0xFFC03150 /* Good RX Frame Count - Byte Count 128 <= x < 256 */
100 #define EMAC_RXC_LT512 0xFFC03154 /* Good RX Frame Count - Byte Count 256 <= x < 512 */
101 #define EMAC_RXC_LT1024 0xFFC03158 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
102 #define EMAC_RXC_GE1024 0xFFC0315C /* Good RX Frame Count - Byte Count x >= 1024 */
103
104 #define EMAC_TXC_OK 0xFFC03180 /* TX Frame Successful Count */
105 #define EMAC_TXC_1COL 0xFFC03184 /* TX Frames Successful After Single Collision Count */
106 #define EMAC_TXC_GT1COL 0xFFC03188 /* TX Frames Successful After Multiple Collisions Count */
107 #define EMAC_TXC_OCTET 0xFFC0318C /* TX Octets Successfully Received Count */
108 #define EMAC_TXC_DEFER 0xFFC03190 /* TX Frame Delayed Due To Busy Count */
109 #define EMAC_TXC_LATECL 0xFFC03194 /* Late TX Collisions Count */
110 #define EMAC_TXC_XS_COL 0xFFC03198 /* TX Frame Failed Due To Excessive Collisions Count */
111 #define EMAC_TXC_DMAUND 0xFFC0319C /* Internal MAC Sublayer Error TX Frame Count */
112 #define EMAC_TXC_CRSERR 0xFFC031A0 /* Carrier Sense Deasserted During TX Frame Count */
113 #define EMAC_TXC_UNICST 0xFFC031A4 /* Unicast TX Frame Count */
114 #define EMAC_TXC_MULTI 0xFFC031A8 /* Multicast TX Frame Count */
115 #define EMAC_TXC_BROAD 0xFFC031AC /* Broadcast TX Frame Count */
116 #define EMAC_TXC_XS_DFR 0xFFC031B0 /* TX Frames With Excessive Deferral Count */
117 #define EMAC_TXC_MACCTL 0xFFC031B4 /* MAC Control TX Frame Count */
118 #define EMAC_TXC_ALLFRM 0xFFC031B8 /* Overall TX Frame Count */
119 #define EMAC_TXC_ALLOCT 0xFFC031BC /* Overall TX Octet Count */
120 #define EMAC_TXC_EQ64 0xFFC031C0 /* Good TX Frame Count - Byte Count x = 64 */
121 #define EMAC_TXC_LT128 0xFFC031C4 /* Good TX Frame Count - Byte Count 64 < x < 128 */
122 #define EMAC_TXC_LT256 0xFFC031C8 /* Good TX Frame Count - Byte Count 128 <= x < 256 */
123 #define EMAC_TXC_LT512 0xFFC031CC /* Good TX Frame Count - Byte Count 256 <= x < 512 */
124 #define EMAC_TXC_LT1024 0xFFC031D0 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
125 #define EMAC_TXC_GE1024 0xFFC031D4 /* Good TX Frame Count - Byte Count x >= 1024 */
126 #define EMAC_TXC_ABORT 0xFFC031D8 /* Total TX Frames Aborted Count */
127
128 /* Listing for IEEE-Supported Count Registers */
129 #define FramesReceivedOK EMAC_RXC_OK /* RX Frame Successful Count */
130 #define FrameCheckSequenceErrors EMAC_RXC_FCS /* RX Frame FCS Failure Count */
131 #define AlignmentErrors EMAC_RXC_ALIGN /* RX Alignment Error Count */
132 #define OctetsReceivedOK EMAC_RXC_OCTET /* RX Octets Successfully Received Count */
133 #define FramesLostDueToIntMACRcvError EMAC_RXC_DMAOVF /* Internal MAC Sublayer Error RX Frame Count */
134 #define UnicastFramesReceivedOK EMAC_RXC_UNICST /* Unicast RX Frame Count */
135 #define MulticastFramesReceivedOK EMAC_RXC_MULTI /* Multicast RX Frame Count */
136 #define BroadcastFramesReceivedOK EMAC_RXC_BROAD /* Broadcast RX Frame Count */
137 #define InRangeLengthErrors EMAC_RXC_LNERRI /* RX Frame In Range Error Count */
138 #define OutOfRangeLengthField EMAC_RXC_LNERRO /* RX Frame Out Of Range Error Count */
139 #define FrameTooLongErrors EMAC_RXC_LONG /* RX Frame Too Long Count */
140 #define MACControlFramesReceived EMAC_RXC_MACCTL /* MAC Control RX Frame Count */
141 #define UnsupportedOpcodesReceived EMAC_RXC_OPCODE /* Unsupported Op-Code RX Frame Count */
142 #define PAUSEMACCtrlFramesReceived EMAC_RXC_PAUSE /* MAC Control Pause RX Frame Count */
143 #define FramesReceivedAll EMAC_RXC_ALLFRM /* Overall RX Frame Count */
144 #define OctetsReceivedAll EMAC_RXC_ALLOCT /* Overall RX Octet Count */
145 #define TypedFramesReceived EMAC_RXC_TYPED /* Type/Length Consistent RX Frame Count */
146 #define FramesLenLt64Received EMAC_RXC_SHORT /* RX Frame Fragment Count - Byte Count x < 64 */
147 #define FramesLenEq64Received EMAC_RXC_EQ64 /* Good RX Frame Count - Byte Count x = 64 */
148 #define FramesLen65_127Received EMAC_RXC_LT128 /* Good RX Frame Count - Byte Count 64 < x < 128 */
149 #define FramesLen128_255Received EMAC_RXC_LT256 /* Good RX Frame Count - Byte Count 128 <= x < 256 */
150 #define FramesLen256_511Received EMAC_RXC_LT512 /* Good RX Frame Count - Byte Count 256 <= x < 512 */
151 #define FramesLen512_1023Received EMAC_RXC_LT1024 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
152 #define FramesLen1024_MaxReceived EMAC_RXC_GE1024 /* Good RX Frame Count - Byte Count x >= 1024 */
153
154 #define FramesTransmittedOK EMAC_TXC_OK /* TX Frame Successful Count */
155 #define SingleCollisionFrames EMAC_TXC_1COL /* TX Frames Successful After Single Collision Count */
156 #define MultipleCollisionFrames EMAC_TXC_GT1COL /* TX Frames Successful After Multiple Collisions Count */
157 #define OctetsTransmittedOK EMAC_TXC_OCTET /* TX Octets Successfully Received Count */
158 #define FramesWithDeferredXmissions EMAC_TXC_DEFER /* TX Frame Delayed Due To Busy Count */
159 #define LateCollisions EMAC_TXC_LATECL /* Late TX Collisions Count */
160 #define FramesAbortedDueToXSColls EMAC_TXC_XS_COL /* TX Frame Failed Due To Excessive Collisions Count */
161 #define FramesLostDueToIntMacXmitError EMAC_TXC_DMAUND /* Internal MAC Sublayer Error TX Frame Count */
162 #define CarrierSenseErrors EMAC_TXC_CRSERR /* Carrier Sense Deasserted During TX Frame Count */
163 #define UnicastFramesXmittedOK EMAC_TXC_UNICST /* Unicast TX Frame Count */
164 #define MulticastFramesXmittedOK EMAC_TXC_MULTI /* Multicast TX Frame Count */
165 #define BroadcastFramesXmittedOK EMAC_TXC_BROAD /* Broadcast TX Frame Count */
166 #define FramesWithExcessiveDeferral EMAC_TXC_XS_DFR /* TX Frames With Excessive Deferral Count */
167 #define MACControlFramesTransmitted EMAC_TXC_MACCTL /* MAC Control TX Frame Count */
168 #define FramesTransmittedAll EMAC_TXC_ALLFRM /* Overall TX Frame Count */
169 #define OctetsTransmittedAll EMAC_TXC_ALLOCT /* Overall TX Octet Count */
170 #define FramesLenEq64Transmitted EMAC_TXC_EQ64 /* Good TX Frame Count - Byte Count x = 64 */
171 #define FramesLen65_127Transmitted EMAC_TXC_LT128 /* Good TX Frame Count - Byte Count 64 < x < 128 */
172 #define FramesLen128_255Transmitted EMAC_TXC_LT256 /* Good TX Frame Count - Byte Count 128 <= x < 256 */
173 #define FramesLen256_511Transmitted EMAC_TXC_LT512 /* Good TX Frame Count - Byte Count 256 <= x < 512 */
174 #define FramesLen512_1023Transmitted EMAC_TXC_LT1024 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
175 #define FramesLen1024_MaxTransmitted EMAC_TXC_GE1024 /* Good TX Frame Count - Byte Count x >= 1024 */
176 #define TxAbortedFrames EMAC_TXC_ABORT /* Total TX Frames Aborted Count */
177
178
179 /***********************************************************************************
180 ** System MMR Register Bits And Macros
181 **
182 ** Disclaimer: All macros are intended to make C and Assembly code more readable.
183 ** Use these macros carefully, as any that do left shifts for field
184 ** depositing will result in the lower order bits being destroyed. Any
185 ** macro that shifts left to properly position the bit-field should be
186 ** used as part of an OR to initialize a register and NOT as a dynamic
187 ** modifier UNLESS the lower order bits are saved and ORed back in when
188 ** the macro is used.
189 *************************************************************************************/
190 /************************ ETHERNET 10/100 CONTROLLER MASKS ************************/
191 /* EMAC_OPMODE Masks */
192 #define RE 0x00000001 /* Receiver Enable */
193 #define ASTP 0x00000002 /* Enable Automatic Pad Stripping On RX Frames */
194 #define HU 0x00000010 /* Hash Filter Unicast Address */
195 #define HM 0x00000020 /* Hash Filter Multicast Address */
196 #define PAM 0x00000040 /* Pass-All-Multicast Mode Enable */
197 #define PR 0x00000080 /* Promiscuous Mode Enable */
198 #define IFE 0x00000100 /* Inverse Filtering Enable */
199 #define DBF 0x00000200 /* Disable Broadcast Frame Reception */
200 #define PBF 0x00000400 /* Pass Bad Frames Enable */
201 #define PSF 0x00000800 /* Pass Short Frames Enable */
202 #define RAF 0x00001000 /* Receive-All Mode */
203 #define TE 0x00010000 /* Transmitter Enable */
204 #define DTXPAD 0x00020000 /* Disable Automatic TX Padding */
205 #define DTXCRC 0x00040000 /* Disable Automatic TX CRC Generation */
206 #define DC 0x00080000 /* Deferral Check */
207 #define BOLMT 0x00300000 /* Back-Off Limit */
208 #define BOLMT_10 0x00000000 /* 10-bit range */
209 #define BOLMT_8 0x00100000 /* 8-bit range */
210 #define BOLMT_4 0x00200000 /* 4-bit range */
211 #define BOLMT_1 0x00300000 /* 1-bit range */
212 #define DRTY 0x00400000 /* Disable TX Retry On Collision */
213 #define LCTRE 0x00800000 /* Enable TX Retry On Late Collision */
214 #define RMII 0x01000000 /* RMII/MII* Mode */
215 #define RMII_10 0x02000000 /* Speed Select for RMII Port (10MBit/100MBit*) */
216 #define FDMODE 0x04000000 /* Duplex Mode Enable (Full/Half*) */
217 #define LB 0x08000000 /* Internal Loopback Enable */
218 #define DRO 0x10000000 /* Disable Receive Own Frames (Half-Duplex Mode) */
219
220 /* EMAC_STAADD Masks */
221 #define STABUSY 0x00000001 /* Initiate Station Mgt Reg Access / STA Busy Stat */
222 #define STAOP 0x00000002 /* Station Management Operation Code (Write/Read*) */
223 #define STADISPRE 0x00000004 /* Disable Preamble Generation */
224 #define STAIE 0x00000008 /* Station Mgt. Transfer Done Interrupt Enable */
225 #define REGAD 0x000007C0 /* STA Register Address */
226 #define PHYAD 0x0000F800 /* PHY Device Address */
227
228 #ifdef _MISRA_RULES
229 #define SET_REGAD(x) (((x)&0x1Fu)<< 6 ) /* Set STA Register Address */
230 #define SET_PHYAD(x) (((x)&0x1Fu)<< 11 ) /* Set PHY Device Address */
231 #else
232 #define SET_REGAD(x) (((x)&0x1F)<< 6 ) /* Set STA Register Address */
233 #define SET_PHYAD(x) (((x)&0x1F)<< 11 ) /* Set PHY Device Address */
234 #endif /* _MISRA_RULES */
235
236 /* EMAC_STADAT Mask */
237 #define STADATA 0x0000FFFF /* Station Management Data */
238
239 /* EMAC_FLC Masks */
240 #define FLCBUSY 0x00000001 /* Send Flow Ctrl Frame / Flow Ctrl Busy Status */
241 #define FLCE 0x00000002 /* Flow Control Enable */
242 #define PCF 0x00000004 /* Pass Control Frames */
243 #define BKPRSEN 0x00000008 /* Enable Backpressure */
244 #define FLCPAUSE 0xFFFF0000 /* Pause Time */
245
246 #ifdef _MISRA_RULES
247 #define SET_FLCPAUSE(x) (((x)&0xFFFFu)<< 16) /* Set Pause Time */
248 #else
249 #define SET_FLCPAUSE(x) (((x)&0xFFFF)<< 16) /* Set Pause Time */
250 #endif /* _MISRA_RULES */
251
252 /* EMAC_WKUP_CTL Masks */
253 #define CAPWKFRM 0x00000001 /* Capture Wake-Up Frames */
254 #define MPKE 0x00000002 /* Magic Packet Enable */
255 #define RWKE 0x00000004 /* Remote Wake-Up Frame Enable */
256 #define GUWKE 0x00000008 /* Global Unicast Wake Enable */
257 #define MPKS 0x00000020 /* Magic Packet Received Status */
258 #define RWKS 0x00000F00 /* Wake-Up Frame Received Status, Filters 3:0 */
259
260 /* EMAC_WKUP_FFCMD Masks */
261 #define WF0_E 0x00000001 /* Enable Wake-Up Filter 0 */
262 #define WF0_T 0x00000008 /* Wake-Up Filter 0 Addr Type (Multicast/Unicast*) */
263 #define WF1_E 0x00000100 /* Enable Wake-Up Filter 1 */
264 #define WF1_T 0x00000800 /* Wake-Up Filter 1 Addr Type (Multicast/Unicast*) */
265 #define WF2_E 0x00010000 /* Enable Wake-Up Filter 2 */
266 #define WF2_T 0x00080000 /* Wake-Up Filter 2 Addr Type (Multicast/Unicast*) */
267 #define WF3_E 0x01000000 /* Enable Wake-Up Filter 3 */
268 #define WF3_T 0x08000000 /* Wake-Up Filter 3 Addr Type (Multicast/Unicast*) */
269
270 /* EMAC_WKUP_FFOFF Masks */
271 #define WF0_OFF 0x000000FF /* Wake-Up Filter 0 Pattern Offset */
272 #define WF1_OFF 0x0000FF00 /* Wake-Up Filter 1 Pattern Offset */
273 #define WF2_OFF 0x00FF0000 /* Wake-Up Filter 2 Pattern Offset */
274 #define WF3_OFF 0xFF000000 /* Wake-Up Filter 3 Pattern Offset */
275
276 #ifdef _MISRA_RULES
277 #define SET_WF0_OFF(x) (((x)&0xFFu)<< 0 ) /* Set Wake-Up Filter 0 Byte Offset */
278 #define SET_WF1_OFF(x) (((x)&0xFFu)<< 8 ) /* Set Wake-Up Filter 1 Byte Offset */
279 #define SET_WF2_OFF(x) (((x)&0xFFu)<< 16 ) /* Set Wake-Up Filter 2 Byte Offset */
280 #define SET_WF3_OFF(x) (((x)&0xFFu)<< 24 ) /* Set Wake-Up Filter 3 Byte Offset */
281 #else
282 #define SET_WF0_OFF(x) (((x)&0xFF)<< 0 ) /* Set Wake-Up Filter 0 Byte Offset */
283 #define SET_WF1_OFF(x) (((x)&0xFF)<< 8 ) /* Set Wake-Up Filter 1 Byte Offset */
284 #define SET_WF2_OFF(x) (((x)&0xFF)<< 16 ) /* Set Wake-Up Filter 2 Byte Offset */
285 #define SET_WF3_OFF(x) (((x)&0xFF)<< 24 ) /* Set Wake-Up Filter 3 Byte Offset */
286 #endif /* _MISRA_RULES */
287
288 /* Set ALL Offsets */
289 #define SET_WF_OFFS(x0,x1,x2,x3) (SET_WF0_OFF((x0))|SET_WF1_OFF((x1))|SET_WF2_OFF((x2))|SET_WF3_OFF((x3)))
290
291 /* EMAC_WKUP_FFCRC0 Masks */
292 #define WF0_CRC 0x0000FFFF /* Wake-Up Filter 0 Pattern CRC */
293 #define WF1_CRC 0xFFFF0000 /* Wake-Up Filter 1 Pattern CRC */
294
295 #ifdef _MISRA_RULES
296 #define SET_WF0_CRC(x) (((x)&0xFFFFu)<< 0 ) /* Set Wake-Up Filter 0 Target CRC */
297 #define SET_WF1_CRC(x) (((x)&0xFFFFu)<< 16 ) /* Set Wake-Up Filter 1 Target CRC */
298 #else
299 #define SET_WF0_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 0 Target CRC */
300 #define SET_WF1_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 1 Target CRC */
301 #endif /* _MISRA_RULES */
302
303 /* EMAC_WKUP_FFCRC1 Masks */
304 #define WF2_CRC 0x0000FFFF /* Wake-Up Filter 2 Pattern CRC */
305 #define WF3_CRC 0xFFFF0000 /* Wake-Up Filter 3 Pattern CRC */
306
307 #ifdef _MISRA_RULES
308 #define SET_WF2_CRC(x) (((x)&0xFFFFu)<< 0 ) /* Set Wake-Up Filter 2 Target CRC */
309 #define SET_WF3_CRC(x) (((x)&0xFFFFu)<< 16 ) /* Set Wake-Up Filter 3 Target CRC */
310 #else
311 #define SET_WF2_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 2 Target CRC */
312 #define SET_WF3_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 3 Target CRC */
313 #endif /* _MISRA_RULES */
314
315 /* EMAC_SYSCTL Masks */
316 #define PHYIE 0x00000001 /* PHY_INT Interrupt Enable */
317 #define RXDWA 0x00000002 /* Receive Frame DMA Word Alignment (Odd/Even*) */
318 #define RXCKS 0x00000004 /* Enable RX Frame TCP/UDP Checksum Computation */
319 #define MDCDIV 0x00003F00 /* SCLK:MDC Clock Divisor [MDC=SCLK/(2*(N+1))] */
320 #if !defined(__SILICON_REVISION__) || (__SILICON_REVISION__>0x2)
321 /* In BF536/7 revs. 0.0, 0.1 and 0.2, this bit was reserved */
322 #define TXDWA 0x00000010 /* Transmit Frame DMA Word Alignment(Even/Odd*) */
323 #endif
324 #ifdef _MISRA_RULES
325 #define SET_MDCDIV(x) (((x)&0x3Fu)<< 8) /* Set MDC Clock Divisor */
326 #else
327 #define SET_MDCDIV(x) (((x)&0x3F)<< 8) /* Set MDC Clock Divisor */
328 #endif /* _MISRA_RULES */
329
330 /* EMAC_SYSTAT Masks */
331 #define PHYINT 0x00000001 /* PHY_INT Interrupt Status */
332 #define MMCINT 0x00000002 /* MMC Counter Interrupt Status */
333 #define RXFSINT 0x00000004 /* RX Frame-Status Interrupt Status */
334 #define TXFSINT 0x00000008 /* TX Frame-Status Interrupt Status */
335 #define WAKEDET 0x00000010 /* Wake-Up Detected Status */
336 #define RXDMAERR 0x00000020 /* RX DMA Direction Error Status */
337 #define TXDMAERR 0x00000040 /* TX DMA Direction Error Status */
338 #define STMDONE 0x00000080 /* Station Mgt. Transfer Done Interrupt Status */
339
340 /* EMAC_RX_STAT, EMAC_RX_STKY, and EMAC_RX_IRQE Masks */
341 #define RX_FRLEN 0x000007FF /* Frame Length In Bytes */
342 #define RX_COMP 0x00001000 /* RX Frame Complete */
343 #define RX_OK 0x00002000 /* RX Frame Received With No Errors */
344 #define RX_LONG 0x00004000 /* RX Frame Too Long Error */
345 #define RX_ALIGN 0x00008000 /* RX Frame Alignment Error */
346 #define RX_CRC 0x00010000 /* RX Frame CRC Error */
347 #define RX_LEN 0x00020000 /* RX Frame Length Error */
348 #define RX_FRAG 0x00040000 /* RX Frame Fragment Error */
349 #define RX_ADDR 0x00080000 /* RX Frame Address Filter Failed Error */
350 #define RX_DMAO 0x00100000 /* RX Frame DMA Overrun Error */
351 #define RX_PHY 0x00200000 /* RX Frame PHY Error */
352 #define RX_LATE 0x00400000 /* RX Frame Late Collision Error */
353 #define RX_RANGE 0x00800000 /* RX Frame Length Field Out of Range Error */
354 #define RX_MULTI 0x01000000 /* RX Multicast Frame Indicator */
355 #define RX_BROAD 0x02000000 /* RX Broadcast Frame Indicator */
356 #define RX_CTL 0x04000000 /* RX Control Frame Indicator */
357 #define RX_UCTL 0x08000000 /* Unsupported RX Control Frame Indicator */
358 #define RX_TYPE 0x10000000 /* RX Typed Frame Indicator */
359 #define RX_VLAN1 0x20000000 /* RX VLAN1 Frame Indicator */
360 #define RX_VLAN2 0x40000000 /* RX VLAN2 Frame Indicator */
361 #define RX_ACCEPT 0x80000000 /* RX Frame Accepted Indicator */
362
363 /* EMAC_TX_STAT, EMAC_TX_STKY, and EMAC_TX_IRQE Masks */
364 #define TX_COMP 0x00000001 /* TX Frame Complete */
365 #define TX_OK 0x00000002 /* TX Frame Sent With No Errors */
366 #define TX_ECOLL 0x00000004 /* TX Frame Excessive Collision Error */
367 #define TX_LATE 0x00000008 /* TX Frame Late Collision Error */
368 #define TX_DMAU 0x00000010 /* TX Frame DMA Underrun Error (STAT) */
369 #define TX_MACE 0x00000010 /* Internal MAC Error Detected (STKY and IRQE) */
370 #define TX_EDEFER 0x00000020 /* TX Frame Excessive Deferral Error */
371 #define TX_BROAD 0x00000040 /* TX Broadcast Frame Indicator */
372 #define TX_MULTI 0x00000080 /* TX Multicast Frame Indicator */
373 #define TX_CCNT 0x00000F00 /* TX Frame Collision Count */
374 #define TX_DEFER 0x00001000 /* TX Frame Deferred Indicator */
375 #define TX_CRS 0x00002000 /* TX Frame Carrier Sense Not Asserted Error */
376 #define TX_LOSS 0x00004000 /* TX Frame Carrier Lost During TX Error */
377 #define TX_RETRY 0x00008000 /* TX Frame Successful After Retry */
378 #define TX_FRLEN 0x07FF0000 /* TX Frame Length (Bytes) */
379
380 /* EMAC_MMC_CTL Masks */
381 #define RSTC 0x00000001 /* Reset All Counters */
382 #define CROLL 0x00000002 /* Counter Roll-Over Enable */
383 #define CCOR 0x00000004 /* Counter Clear-On-Read Mode Enable */
384 #define MMCE 0x00000008 /* Enable MMC Counter Operation */
385
386 /* EMAC_MMC_RIRQS and EMAC_MMC_RIRQE Masks */
387 #define RX_OK_CNT 0x00000001 /* RX Frames Received With No Errors */
388 #define RX_FCS_CNT 0x00000002 /* RX Frames W/Frame Check Sequence Errors */
389 #define RX_ALIGN_CNT 0x00000004 /* RX Frames With Alignment Errors */
390 #define RX_OCTET_CNT 0x00000008 /* RX Octets Received OK */
391 #define RX_LOST_CNT 0x00000010 /* RX Frames Lost Due To Internal MAC RX Error */
392 #define RX_UNI_CNT 0x00000020 /* Unicast RX Frames Received OK */
393 #define RX_MULTI_CNT 0x00000040 /* Multicast RX Frames Received OK */
394 #define RX_BROAD_CNT 0x00000080 /* Broadcast RX Frames Received OK */
395 #define RX_IRL_CNT 0x00000100 /* RX Frames With In-Range Length Errors */
396 #define RX_ORL_CNT 0x00000200 /* RX Frames With Out-Of-Range Length Errors */
397 #define RX_LONG_CNT 0x00000400 /* RX Frames With Frame Too Long Errors */
398 #define RX_MACCTL_CNT 0x00000800 /* MAC Control RX Frames Received */
399 #define RX_OPCODE_CTL 0x00001000 /* Unsupported Op-Code RX Frames Received */
400 #define RX_PAUSE_CNT 0x00002000 /* PAUSEMAC Control RX Frames Received */
401 #define RX_ALLF_CNT 0x00004000 /* All RX Frames Received */
402 #define RX_ALLO_CNT 0x00008000 /* All RX Octets Received */
403 #define RX_TYPED_CNT 0x00010000 /* Typed RX Frames Received */
404 #define RX_SHORT_CNT 0x00020000 /* RX Frame Fragments (< 64 Bytes) Received */
405 #define RX_EQ64_CNT 0x00040000 /* 64-Byte RX Frames Received */
406 #define RX_LT128_CNT 0x00080000 /* 65-127-Byte RX Frames Received */
407 #define RX_LT256_CNT 0x00100000 /* 128-255-Byte RX Frames Received */
408 #define RX_LT512_CNT 0x00200000 /* 256-511-Byte RX Frames Received */
409 #define RX_LT1024_CNT 0x00400000 /* 512-1023-Byte RX Frames Received */
410 #define RX_GE1024_CNT 0x00800000 /* 1024-Max-Byte RX Frames Received */
411
412 /* EMAC_MMC_TIRQS and EMAC_MMC_TIRQE Masks */
413 #define TX_OK_CNT 0x00000001 /* TX Frames Sent OK */
414 #define TX_SCOLL_CNT 0x00000002 /* TX Frames With Single Collisions */
415 #define TX_MCOLL_CNT 0x00000004 /* TX Frames With Multiple Collisions */
416 #define TX_OCTET_CNT 0x00000008 /* TX Octets Sent OK */
417 #define TX_DEFER_CNT 0x00000010 /* TX Frames With Deferred Transmission */
418 #define TX_LATE_CNT 0x00000020 /* TX Frames With Late Collisions */
419 #define TX_ABORTC_CNT 0x00000040 /* TX Frames Aborted Due To Excess Collisions */
420 #define TX_LOST_CNT 0x00000080 /* TX Frames Lost Due To Internal MAC TX Error */
421 #define TX_CRS_CNT 0x00000100 /* TX Frames With Carrier Sense Errors */
422 #define TX_UNI_CNT 0x00000200 /* Unicast TX Frames Sent */
423 #define TX_MULTI_CNT 0x00000400 /* Multicast TX Frames Sent */
424 #define TX_BROAD_CNT 0x00000800 /* Broadcast TX Frames Sent */
425 #define TX_EXDEF_CTL 0x00001000 /* TX Frames With Excessive Deferral */
426 #define TX_MACCTL_CNT 0x00002000 /* MAC Control TX Frames Sent */
427 #define TX_ALLF_CNT 0x00004000 /* All TX Frames Sent */
428 #define TX_ALLO_CNT 0x00008000 /* All TX Octets Sent */
429 #define TX_EQ64_CNT 0x00010000 /* 64-Byte TX Frames Sent */
430 #define TX_LT128_CNT 0x00020000 /* 65-127-Byte TX Frames Sent */
431 #define TX_LT256_CNT 0x00040000 /* 128-255-Byte TX Frames Sent */
432 #define TX_LT512_CNT 0x00080000 /* 256-511-Byte TX Frames Sent */
433 #define TX_LT1024_CNT 0x00100000 /* 512-1023-Byte TX Frames Sent */
434 #define TX_GE1024_CNT 0x00200000 /* 1024-Max-Byte TX Frames Sent */
435 #define TX_ABORT_CNT 0x00400000 /* TX Frames Aborted */
436 #ifdef _MISRA_RULES
437 #pragma diag(pop)
438 #endif /* _MISRA_RULES */
439
440 #endif /* _DEF_BF537_H */
441