eth_ocm/HAL/inc/ins_eth_ocm.h

   1 #ifndef __INS_ETH_OCM_H__
   2 #define __INS_ETH_OCM_H__
   3 //Altera includes
   4 #include <io.h>             //Altera IOWR, IORD macros
   5 #include <errno.h>          //Error return codes
   6 #include "alt_types.h"      //Altera variable types
   7 #include <sys/alt_cache.h>  //For cache bypassing
   8 #include <sys/alt_irq.h>    //for ISR registering
   9
  10 //Interniche includes
  11 #include "alt_iniche_dev.h" //For alt_iniche_dev struct
  12 #include "ether.h"          //For ethhdr struct
  13
  14 //UCOSII includes
  15 #ifdef UCOS_II
  16 #include <ucos_ii.h>
  17 #include <os_cpu.h>
  18 #endif
  19
  20 //Opencores MAC includes
  21 #include "eth_ocm.h"
  22 #include "eth_ocm_regs.h"
  23 #include "eth_ocm_desc.h"
  24
  25 #include "system.h"         //Macro defs for your system
  26
  27 //****************************************************************************
  28 //************************** Compilation options *****************************
  29
  30 // Set debug print statement level.
  31 // Level 0 - No debugging)
  32 // Level 1 - Harmless debugging (initialization) will not harm performance.
  33 // Level 2 - Runtime debugging Transmit errors. High level of
  34 //           errors may impact performance due to excessive printing.
  35 // Level 3 - Runtimine debugging transmit and receive errors. High level of TX
  36 //           or RX errors may impact performance due to excessive printing.
  37 // Level 4 - Low level debugging. Will impact performance.
  38 #ifndef ETH_OCM_DBG_LVL
  39     #define ETH_OCM_DBG_LVL 0
  40 #endif
  41
  42 // Define ETH_OCM_SYNC_TX to enable synchronous transmit operations
  43 // Whether or not this makes sense depends on your system. With syncronous
  44 // transmits, all transmits block until the frame as been transmitted. This
  45 // obviously implies a performance hit as nothing else can be done until the
  46 // frame has been tranferred.
  47 //      On the other hand, asynchronous transfers incurr a performance hit
  48 //  due to increased interrupt activity. Try both to see which gives you higher
  49 //  performance.
  50 // #define ETH_OCM_SYNC_TX
  51
  52 // Total number of available descriptors
  53 #define ETH_OCM_TOTAL_DESC_COUNT    128
  54
  55 // Define the number of descriptors used for Transmit
  56 #ifndef ETH_OCM_TX_DESC_COUNT
  57     #define ETH_OCM_TX_DESC_COUNT       1
  58 #endif //ifndef ETH_OCM_TX_DESC_COUNT
  59
  60 // Validate Transmit descriptor count
  61 #if (ETH_OCM_TX_DESC_COUNT >= ETH_OCM_TOTAL_DESC_COUNT)
  62     #error [ins_eth_ocm.h] Defined TX descriptor count not supported
  63 #endif
  64
  65 // Define the number of descriptors used for Receive
  66 #ifndef ETH_OCM_RX_DESC_COUNT
  67     #define ETH_OCM_RX_DESC_COUNT       1   //Requires sufficient Iniche Buffers
  68 #endif //ifndef ETH_OCM_TX_DESC_COUNT
  69
  70 // Validate Receive descriptor count
  71 #if (ETH_OCM_RX_DESC_COUNT > (128 - ETH_OCM_TX_DESC_COUNT))
  72     #error  [ins_eth_ocm.h] Defined RX descriptor count not supported
  73 #endif
  74
  75 //************************ End Compilation options ***************************
  76 //****************************************************************************
  77 // Define the size of Buffers the driver will request for RX.
  78 #define ETH_OCM_BUF_ALLOC_SIZE      1536
  79
  80 // Define the flags that will trigger an interrupt.
  81 #ifdef ETH_OCM_TX_SYNC
  82 #define ETH_OCM_DEFAULT_INTERRUPT_MASK  \
  83     (ETH_OCM_INT_MASK_BUSY_MSK  |       \
  84      ETH_OCM_INT_MASK_RXE_MSK   |       \
  85      ETH_OCM_INT_MASK_RXB_MSK )
  86
  87 #else
  88
  89 #define ETH_OCM_DEFAULT_INTERRUPT_MASK  \
  90     (ETH_OCM_INT_MASK_BUSY_MSK  |       \
  91      ETH_OCM_INT_MASK_TXE_MSK   |       \
  92      ETH_OCM_INT_MASK_TXB_MSK   |       \
  93      ETH_OCM_INT_MASK_RXE_MSK   |       \
  94      ETH_OCM_INT_MASK_RXB_MSK )
  95
  96 #endif // !defined ETH_OCM_TX_SYNC
  97
  98
  99 // Define the number of times to poll the Transmit descriptor to determine if
 100 // a synchronous transmit has finished (Not used in regular asynchronous mode)
 101 #define ETH_OCM_TRANSMIT_TIMEOUT    1000000
 102
 103 /**
 104  * eth_ocm_regs struct is used to enumerate the registers within
 105  * the Opencores MAC. It is custom tuned for the number of TX and RX
 106  * Descriptors
 107  */
 108 typedef struct{
 109     alt_u32         moder;
 110     alt_u32         int_source;
 111     alt_u32         int_mask;
 112     alt_u32         ipgt;
 113     alt_u32         ipgr1;
 114     alt_u32         ipgr2;
 115     alt_u32         packetlen;
 116     alt_u32         collconf;
 117     alt_u32         tx_bd_num;
 118     alt_u32         ctrlmoder;
 119     alt_u32         miimoder;
 120     alt_u32         miicommand;
 121     alt_u32         miiaddress;
 122     alt_u32         miitx_data;
 123     alt_u32         miirx_data;
 124     alt_u32         miistatus;
 125     alt_u32         mac_addr0;
 126     alt_u32         mac_addr1;
 127     alt_u32         eth_hash0;
 128     alt_u32         eth_hash1;
 129     alt_u32         eth_ctrl;
 130     alt_u32         reserved[235];
 131     eth_ocm_desc    txdescs[ETH_OCM_TX_DESC_COUNT];
 132     eth_ocm_desc    rxdescs[ETH_OCM_RX_DESC_COUNT];
 133 } volatile eth_ocm_regs;
 134
 135 /**
 136  * eth_ocm_info contains information needed for runtime operation of the MAC in
 137  * conjunction with the InterNiche Stack. It is created and initialized if and
 138  * when the InterNiche Stack calls the MAC driver's "prep" function.
 139  */
 140 typedef struct{
 141     unsigned char   mac_addr[6];    //MAC address
 142     NET             netp;           //Pointer to associated interface
 143     alt_u8          sem;            //semaphore
 144     alt_u8          cur_tx_desc;    //Current TX descriptor (currently transferring)
 145     alt_u8          cur_rx_desc;    //Current RX descriptor
 146     PACKET          *rx_pkts;       //To be alloced and used as array
 147 #ifndef ETH_OCM_SYNC_TX
 148     queue           tosend;         //Packets to be sent queue
 149     queue           sending;        //Packets being sent queue
 150     alt_u8          next_tx_desc;   //Next TX descriptor (to schedule a transfer)
 151     alt_u8          next_tx_desc_rdy; //Next TX descriptor can be used
 152 #endif
 153 } eth_ocm_info;
 154
 155 /**
 156  * eth_ocm_dev contains information aquired at initialization time that is
 157  * required for further access to the device. This struct is initialized
 158  * by the alt_sys_init routine for each instance of the OpenCores MAC in the
 159  * system.
 160  */
 161 typedef struct{
 162     alt_iniche_dev  ins_dev;
 163     alt_u32         base;
 164     eth_ocm_regs    *regs;
 165     alt_u8          irq;
 166     char            name[20];
 167     eth_ocm_info    *info;
 168 } eth_ocm_dev;
 169
 170
 171 #ifdef __cplusplus
 172 extern "C"
 173 {
 174 #endif // __cplusplus
 175
 176 error_t eth_ocm_prep(alt_iniche_dev *ins_dev);
 177 int     eth_ocm_init(int iface);
 178 int     eth_ocm_close(int iface);
 179 void    eth_ocm_stats(void *pio, int iface);
 180
 181 #ifdef  __cplusplus
 182 }
 183 #endif  // __cplusplus
 184
 185 //Information that can't be obtained later
 186 #define ETH_OCM_INSTANCE(name, dev)     \
 187 eth_ocm_dev dev =                       \
 188 {                                       \
 189     {                                   \
 190         ALT_LLIST_ENTRY,                \
 191         name##_NAME,                    \
 192         eth_ocm_prep                    \
 193     },                                  \
 194     name##_BASE,                        \
 195     (eth_ocm_regs*)(name##_BASE | 0x80000000), \
 196     name##_IRQ,                         \
 197     name##_NAME,                        \
 198     NULL                                \
 199 }
 200
 201 //Opencores ethernet mac init function
 202 #define ETH_OCM_INIT(name, dev_inst)    \
 203     alt_iniche_dev_reg(&(dev_inst.ins_dev))
 204
 205 #endif  //__INS_ETH_OCM_H__