eth_ocm/eth_ocm_hw.tcl

   1 # TCL File Generated by Component Editor 8.0sp1
   2 # Wed Oct 08 08:58:57 MDT 2008
   3 # DO NOT MODIFY
   4
   5
   6 # +-----------------------------------
   7 # |
   8 # | eth_ocm "OpenCores 10/100 Ethernet MAC Avalon" v8.0.2
   9 # | Jakob Jones 2008.10.08.08:58:57
  10 # |
  11 # |
  12 # | C:/altera/80/ip/sopc_builder_ip/eth_ocm/eth_ocm.v
  13 # |
  14 # |    ./eth_ocm.v syn, sim
  15 # |
  16 # +-----------------------------------
  17
  18
  19 # +-----------------------------------
  20 # | module eth_ocm
  21 # |
  22 set_module_property DESCRIPTION ""
  23 set_module_property NAME eth_ocm
  24 set_module_property VERSION 8.0.2
  25 set_module_property GROUP "Interface Protocols/Ethernet"
  26 set_module_property AUTHOR "Jakob Jones"
  27 set_module_property DISPLAY_NAME "OpenCores 10/100 Ethernet MAC Avalon"
  28 set_module_property TOP_LEVEL_HDL_FILE eth_ocm.v
  29 set_module_property TOP_LEVEL_HDL_MODULE eth_ocm
  30 set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
  31 set_module_property EDITABLE false
  32 set_module_property SIMULATION_MODEL_IN_VERILOG false
  33 set_module_property SIMULATION_MODEL_IN_VHDL false
  34 set_module_property SIMULATION_MODEL_HAS_TULIPS false
  35 set_module_property SIMULATION_MODEL_IS_OBFUSCATED false
  36 # |
  37 # +-----------------------------------
  38
  39 # +-----------------------------------
  40 # | files
  41 # |
  42 add_file eth_ocm.v {SYNTHESIS SIMULATION}
  43 # |
  44 # +-----------------------------------
  45
  46 # +-----------------------------------
  47 # | parameters
  48 # |
  49 add_parameter TOTAL_DESCRIPTORS int 128 "Total number of DMA descriptors"
  50 set_parameter_property TOTAL_DESCRIPTORS DISPLAY_NAME TOTAL_DESCRIPTORS
  51 set_parameter_property TOTAL_DESCRIPTORS UNITS None
  52 set_parameter_property TOTAL_DESCRIPTORS AFFECTS_PORT_WIDTHS true
  53 add_parameter TX_FIFO_SIZE_IN_BYTES int 128 "Transmit FIFO size in bytes"
  54 set_parameter_property TX_FIFO_SIZE_IN_BYTES DISPLAY_NAME TX_FIFO_SIZE_IN_BYTES
  55 set_parameter_property TX_FIFO_SIZE_IN_BYTES UNITS None
  56 set_parameter_property TX_FIFO_SIZE_IN_BYTES AFFECTS_PORT_WIDTHS true
  57 add_parameter RX_FIFO_SIZE_IN_BYTES int 4096 "Receive FIFO size in bytes"
  58 set_parameter_property RX_FIFO_SIZE_IN_BYTES DISPLAY_NAME RX_FIFO_SIZE_IN_BYTES
  59 set_parameter_property RX_FIFO_SIZE_IN_BYTES UNITS None
  60 set_parameter_property RX_FIFO_SIZE_IN_BYTES AFFECTS_PORT_WIDTHS true
  61 # |
  62 # +-----------------------------------
  63
  64 # +-----------------------------------
  65 # | connection point control_port
  66 # |
  67 add_interface control_port avalon end
  68 set_interface_property control_port holdTime 0
  69 set_interface_property control_port linewrapBursts false
  70 set_interface_property control_port minimumUninterruptedRunLength 1
  71 set_interface_property control_port bridgesToMaster ""
  72 set_interface_property control_port isMemoryDevice false
  73 set_interface_property control_port burstOnBurstBoundariesOnly false
  74 set_interface_property control_port addressSpan 4096
  75 set_interface_property control_port timingUnits Cycles
  76 set_interface_property control_port setupTime 0
  77 set_interface_property control_port writeWaitTime 0
  78 set_interface_property control_port isNonVolatileStorage false
  79 set_interface_property control_port addressAlignment DYNAMIC
  80 set_interface_property control_port maximumPendingReadTransactions 0
  81 set_interface_property control_port readWaitTime 1
  82 set_interface_property control_port readLatency 0
  83 set_interface_property control_port printableDevice false
  84
  85 set_interface_property control_port ASSOCIATED_CLOCK clock
  86
  87 add_interface_port control_port av_address address Input 10
  88 add_interface_port control_port av_chipselect chipselect Input 1
  89 add_interface_port control_port av_write write Input 1
  90 add_interface_port control_port av_read read Input 1
  91 add_interface_port control_port av_writedata writedata Input 32
  92 add_interface_port control_port av_readdata readdata Output 32
  93 add_interface_port control_port av_waitrequest_n waitrequest_n Output 1
  94 # |
  95 # +-----------------------------------
  96
  97 # +-----------------------------------
  98 # | connection point clock
  99 # |
 100 add_interface clock clock end
 101 set_interface_property clock ptfSchematicName ""
 102
 103 add_interface_port clock av_clk clk Input 1
 104 add_interface_port clock av_reset reset Input 1
 105 # |
 106 # +-----------------------------------
 107
 108 # +-----------------------------------
 109 # | connection point tx_master
 110 # |
 111 add_interface tx_master avalon start
 112 set_interface_property tx_master linewrapBursts false
 113 set_interface_property tx_master adaptsTo ""
 114 set_interface_property tx_master doStreamReads false
 115 set_interface_property tx_master doStreamWrites false
 116 set_interface_property tx_master burstOnBurstBoundariesOnly false
 117
 118 set_interface_property tx_master ASSOCIATED_CLOCK clock
 119
 120 add_interface_port tx_master av_tx_readdata readdata Input 32
 121 add_interface_port tx_master av_tx_waitrequest waitrequest Input 1
 122 add_interface_port tx_master av_tx_readdatavalid readdatavalid Input 1
 123 add_interface_port tx_master av_tx_address address Output 32
 124 add_interface_port tx_master av_tx_read read Output 1
 125 # |
 126 # +-----------------------------------
 127
 128 # +-----------------------------------
 129 # | connection point rx_master
 130 # |
 131 add_interface rx_master avalon start
 132 set_interface_property rx_master linewrapBursts false
 133 set_interface_property rx_master adaptsTo ""
 134 set_interface_property rx_master doStreamReads false
 135 set_interface_property rx_master doStreamWrites false
 136 set_interface_property rx_master burstOnBurstBoundariesOnly false
 137
 138 set_interface_property rx_master ASSOCIATED_CLOCK clock
 139
 140 add_interface_port rx_master av_rx_waitrequest waitrequest Input 1
 141 add_interface_port rx_master av_rx_address address Output 32
 142 add_interface_port rx_master av_rx_write write Output 1
 143 add_interface_port rx_master av_rx_writedata writedata Output 32
 144 add_interface_port rx_master av_rx_byteenable byteenable Output 4
 145 # |
 146 # +-----------------------------------
 147
 148 # +-----------------------------------
 149 # | connection point global
 150 # |
 151 add_interface global conduit end
 152
 153 set_interface_property global ASSOCIATED_CLOCK clock
 154
 155 add_interface_port global mtx_clk_pad_i export Input 1
 156 add_interface_port global mtxd_pad_o export Output 4
 157 add_interface_port global mtxen_pad_o export Output 1
 158 add_interface_port global mtxerr_pad_o export Output 1
 159 add_interface_port global mrx_clk_pad_i export Input 1
 160 add_interface_port global mrxd_pad_i export Input 4
 161 add_interface_port global mrxdv_pad_i export Input 1
 162 add_interface_port global mrxerr_pad_i export Input 1
 163 add_interface_port global mcoll_pad_i export Input 1
 164 add_interface_port global mcrs_pad_i export Input 1
 165 add_interface_port global mdc_pad_o export Output 1
 166 add_interface_port global md_pad_i export Input 1
 167 add_interface_port global md_pad_o export Output 1
 168 add_interface_port global md_padoe_o export Output 1
 169 # |
 170 # +-----------------------------------
 171
 172 # +-----------------------------------
 173 # | connection point control_port_irq
 174 # |
 175 add_interface control_port_irq interrupt end
 176 set_interface_property control_port_irq associatedAddressablePoint control_port
 177
 178 set_interface_property control_port_irq ASSOCIATED_CLOCK clock
 179
 180 add_interface_port control_port_irq av_irq irq Output 1
 181 # |
 182 # +-----------------------------------