eth_ocm/eth_maccontrol.v

   1 //////////////////////////////////////////////////////////////////////
   2 ////                                                              ////
   3 ////  eth_maccontrol.v                                            ////
   4 ////                                                              ////
   5 ////  This file is part of the Ethernet IP core project           ////
   6 ////  http://www.opencores.org/projects/ethmac/                   ////
   7 ////                                                              ////
   8 ////  Author(s):                                                  ////
   9 ////      - Igor Mohor (igorM@opencores.org)                      ////
  10 ////                                                              ////
  11 ////  All additional information is avaliable in the Readme.txt   ////
  12 ////  file.                                                       ////
  13 ////                                                              ////
  14 //////////////////////////////////////////////////////////////////////
  15 ////                                                              ////
  16 //// Copyright (C) 2001 Authors                                   ////
  17 ////                                                              ////
  18 //// This source file may be used and distributed without         ////
  19 //// restriction provided that this copyright statement is not    ////
  20 //// removed from the file and that any derivative work contains  ////
  21 //// the original copyright notice and the associated disclaimer. ////
  22 ////                                                              ////
  23 //// This source file is free software; you can redistribute it   ////
  24 //// and/or modify it under the terms of the GNU Lesser General   ////
  25 //// Public License as published by the Free Software Foundation; ////
  26 //// either version 2.1 of the License, or (at your option) any   ////
  27 //// later version.                                               ////
  28 ////                                                              ////
  29 //// This source is distributed in the hope that it will be       ////
  30 //// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
  31 //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
  32 //// PURPOSE.  See the GNU Lesser General Public License for more ////
  33 //// details.                                                     ////
  34 ////                                                              ////
  35 //// You should have received a copy of the GNU Lesser General    ////
  36 //// Public License along with this source; if not, download it   ////
  37 //// from http://www.opencores.org/lgpl.shtml                     ////
  38 ////                                                              ////
  39 //////////////////////////////////////////////////////////////////////
  40 //
  41 // CVS Revision History
  42 //
  43 // $Log: eth_maccontrol.v,v $
  44 // Revision 1.7  2003/01/22 13:49:26  tadejm
  45 // When control packets were received, they were ignored in some cases.
  46 //
  47 // Revision 1.6  2002/11/22 01:57:06  mohor
  48 // Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
  49 // synchronized.
  50 //
  51 // Revision 1.5  2002/11/21 00:14:39  mohor
  52 // TxDone and TxAbort changed so they're not propagated to the wishbone
  53 // module when control frame is transmitted.
  54 //
  55 // Revision 1.4  2002/11/19 17:37:32  mohor
  56 // When control frame (PAUSE) was sent, status was written in the
  57 // eth_wishbone module and both TXB and TXC interrupts were set. Fixed.
  58 // Only TXC interrupt is set.
  59 //
  60 // Revision 1.3  2002/01/23 10:28:16  mohor
  61 // Link in the header changed.
  62 //
  63 // Revision 1.2  2001/10/19 08:43:51  mohor
  64 // eth_timescale.v changed to timescale.v This is done because of the
  65 // simulation of the few cores in a one joined project.
  66 //
  67 // Revision 1.1  2001/08/06 14:44:29  mohor
  68 // A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
  69 // Include files fixed to contain no path.
  70 // File names and module names changed ta have a eth_ prologue in the name.
  71 // File eth_timescale.v is used to define timescale
  72 // All pin names on the top module are changed to contain _I, _O or _OE at the end.
  73 // Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
  74 // and Mdo_OE. The bidirectional signal must be created on the top level. This
  75 // is done due to the ASIC tools.
  76 //
  77 // Revision 1.1  2001/07/30 21:23:42  mohor
  78 // Directory structure changed. Files checked and joind together.
  79 //
  80 // Revision 1.1  2001/07/03 12:51:54  mohor
  81 // Initial release of the MAC Control module.
  82 //
  83 //
  84 //
  85 //
  86
  87
  88 `include "timescale.v"
  89
  90
  91 module eth_maccontrol (MTxClk, MRxClk, TxReset, RxReset, TPauseRq, TxDataIn, TxStartFrmIn, TxUsedDataIn,
  92                        TxEndFrmIn, TxDoneIn, TxAbortIn, RxData, RxValid, RxStartFrm, RxEndFrm, ReceiveEnd,
  93                        ReceivedPacketGood, ReceivedLengthOK, TxFlow, RxFlow, DlyCrcEn, TxPauseTV,
  94                        MAC, PadIn, PadOut, CrcEnIn, CrcEnOut, TxDataOut, TxStartFrmOut, TxEndFrmOut,
  95                        TxDoneOut, TxAbortOut, TxUsedDataOut, WillSendControlFrame, TxCtrlEndFrm,
  96                        ReceivedPauseFrm, ControlFrmAddressOK, SetPauseTimer, r_PassAll, RxStatusWriteLatched_sync2
  97                       );
  98
  99
 100 parameter   Tp = 1;
 101
 102
 103 input         MTxClk;                   // Transmit clock (from PHY)
 104 input         MRxClk;                   // Receive clock (from PHY)
 105 input         TxReset;                  // Transmit reset
 106 input         RxReset;                  // Receive reset
 107 input         TPauseRq;                 // Transmit control frame (from host)
 108 input   [7:0] TxDataIn;                 // Transmit packet data byte (from host)
 109 input         TxStartFrmIn;             // Transmit packet start frame input (from host)
 110 input         TxUsedDataIn;             // Transmit packet used data (from TxEthMAC)
 111 input         TxEndFrmIn;               // Transmit packet end frame input (from host)
 112 input         TxDoneIn;                 // Transmit packet done (from TxEthMAC)
 113 input         TxAbortIn;                // Transmit packet abort (input from TxEthMAC)
 114 input         PadIn;                    // Padding (input from registers)
 115 input         CrcEnIn;                  // Crc append (input from registers)
 116 input   [7:0] RxData;                   // Receive Packet Data (from RxEthMAC)
 117 input         RxValid;                  // Received a valid packet
 118 input         RxStartFrm;               // Receive packet start frame (input from RxEthMAC)
 119 input         RxEndFrm;                 // Receive packet end frame (input from RxEthMAC)
 120 input         ReceiveEnd;               // End of receiving of the current packet (input from RxEthMAC)
 121 input         ReceivedPacketGood;       // Received packet is good
 122 input         ReceivedLengthOK;         // Length of the received packet is OK
 123 input         TxFlow;                   // Tx flow control (from registers)
 124 input         RxFlow;                   // Rx flow control (from registers)
 125 input         DlyCrcEn;                 // Delayed CRC enabled (from registers)
 126 input  [15:0] TxPauseTV;                // Transmit Pause Timer Value (from registers)
 127 input  [47:0] MAC;                      // MAC address (from registers)
 128 input         RxStatusWriteLatched_sync2;
 129 input         r_PassAll;
 130
 131 output  [7:0] TxDataOut;                // Transmit Packet Data (to TxEthMAC)
 132 output        TxStartFrmOut;            // Transmit packet start frame (output to TxEthMAC)
 133 output        TxEndFrmOut;              // Transmit packet end frame (output to TxEthMAC)
 134 output        TxDoneOut;                // Transmit packet done (to host)
 135 output        TxAbortOut;               // Transmit packet aborted (to host)
 136 output        TxUsedDataOut;            // Transmit packet used data (to host)
 137 output        PadOut;                   // Padding (output to TxEthMAC)
 138 output        CrcEnOut;                 // Crc append (output to TxEthMAC)
 139 output        WillSendControlFrame;
 140 output        TxCtrlEndFrm;
 141 output        ReceivedPauseFrm;
 142 output        ControlFrmAddressOK;
 143 output        SetPauseTimer;
 144
 145 reg           TxUsedDataOutDetected;
 146 reg           TxAbortInLatched;
 147 reg           TxDoneInLatched;
 148 reg           MuxedDone;
 149 reg           MuxedAbort;
 150
 151 wire          Pause;
 152 wire          TxCtrlStartFrm;
 153 wire    [7:0] ControlData;
 154 wire          CtrlMux;
 155 wire          SendingCtrlFrm;           // Sending Control Frame (enables padding and CRC)
 156 wire          BlockTxDone;
 157
 158
 159 // Signal TxUsedDataOut was detected (a transfer is already in progress)
 160 always @ (posedge MTxClk or posedge TxReset)
 161 begin
 162   if(TxReset)
 163     TxUsedDataOutDetected <= #Tp 1'b0;
 164   else
 165   if(TxDoneIn | TxAbortIn)
 166     TxUsedDataOutDetected <= #Tp 1'b0;
 167   else
 168   if(TxUsedDataOut)
 169     TxUsedDataOutDetected <= #Tp 1'b1;
 170 end
 171
 172
 173 // Latching variables
 174 always @ (posedge MTxClk or posedge TxReset)
 175 begin
 176   if(TxReset)
 177     begin
 178       TxAbortInLatched <= #Tp 1'b0;
 179       TxDoneInLatched  <= #Tp 1'b0;
 180     end
 181   else
 182     begin
 183       TxAbortInLatched <= #Tp TxAbortIn;
 184       TxDoneInLatched  <= #Tp TxDoneIn;
 185     end
 186 end
 187
 188
 189
 190 // Generating muxed abort signal
 191 always @ (posedge MTxClk or posedge TxReset)
 192 begin
 193   if(TxReset)
 194     MuxedAbort <= #Tp 1'b0;
 195   else
 196   if(TxStartFrmIn)
 197     MuxedAbort <= #Tp 1'b0;
 198   else
 199   if(TxAbortIn & ~TxAbortInLatched & TxUsedDataOutDetected)
 200     MuxedAbort <= #Tp 1'b1;
 201 end
 202
 203
 204 // Generating muxed done signal
 205 always @ (posedge MTxClk or posedge TxReset)
 206 begin
 207   if(TxReset)
 208     MuxedDone <= #Tp 1'b0;
 209   else
 210   if(TxStartFrmIn)
 211     MuxedDone <= #Tp 1'b0;
 212   else
 213   if(TxDoneIn & (~TxDoneInLatched) & TxUsedDataOutDetected)
 214     MuxedDone <= #Tp 1'b1;
 215 end
 216
 217
 218 // TxDoneOut
 219 assign TxDoneOut  = CtrlMux? ((~TxStartFrmIn) & (~BlockTxDone) & MuxedDone) :
 220                              ((~TxStartFrmIn) & (~BlockTxDone) & TxDoneIn);
 221
 222 // TxAbortOut
 223 assign TxAbortOut  = CtrlMux? ((~TxStartFrmIn) & (~BlockTxDone) & MuxedAbort) :
 224                               ((~TxStartFrmIn) & (~BlockTxDone) & TxAbortIn);
 225
 226 // TxUsedDataOut
 227 assign TxUsedDataOut  = ~CtrlMux & TxUsedDataIn;
 228
 229 // TxStartFrmOut
 230 assign TxStartFrmOut = CtrlMux? TxCtrlStartFrm : (TxStartFrmIn & ~Pause);
 231
 232
 233 // TxEndFrmOut
 234 assign TxEndFrmOut = CtrlMux? TxCtrlEndFrm : TxEndFrmIn;
 235
 236
 237 // TxDataOut[7:0]
 238 assign TxDataOut[7:0] = CtrlMux? ControlData[7:0] : TxDataIn[7:0];
 239
 240
 241 // PadOut
 242 assign PadOut = PadIn | SendingCtrlFrm;
 243
 244
 245 // CrcEnOut
 246 assign CrcEnOut = CrcEnIn | SendingCtrlFrm;
 247
 248
 249
 250 // Connecting receivecontrol module
 251 eth_receivecontrol receivecontrol1
 252 (
 253  .MTxClk(MTxClk), .MRxClk(MRxClk), .TxReset(TxReset), .RxReset(RxReset), .RxData(RxData),
 254  .RxValid(RxValid), .RxStartFrm(RxStartFrm), .RxEndFrm(RxEndFrm), .RxFlow(RxFlow),
 255  .ReceiveEnd(ReceiveEnd), .MAC(MAC), .DlyCrcEn(DlyCrcEn), .TxDoneIn(TxDoneIn),
 256  .TxAbortIn(TxAbortIn), .TxStartFrmOut(TxStartFrmOut), .ReceivedLengthOK(ReceivedLengthOK),
 257  .ReceivedPacketGood(ReceivedPacketGood), .TxUsedDataOutDetected(TxUsedDataOutDetected),
 258  .Pause(Pause), .ReceivedPauseFrm(ReceivedPauseFrm), .AddressOK(ControlFrmAddressOK),
 259  .r_PassAll(r_PassAll), .RxStatusWriteLatched_sync2(RxStatusWriteLatched_sync2), .SetPauseTimer(SetPauseTimer)
 260 );
 261
 262
 263 eth_transmitcontrol transmitcontrol1
 264 (
 265  .MTxClk(MTxClk), .TxReset(TxReset), .TxUsedDataIn(TxUsedDataIn), .TxUsedDataOut(TxUsedDataOut),
 266  .TxDoneIn(TxDoneIn), .TxAbortIn(TxAbortIn), .TxStartFrmIn(TxStartFrmIn), .TPauseRq(TPauseRq),
 267  .TxUsedDataOutDetected(TxUsedDataOutDetected), .TxFlow(TxFlow), .DlyCrcEn(DlyCrcEn), .TxPauseTV(TxPauseTV),
 268  .MAC(MAC), .TxCtrlStartFrm(TxCtrlStartFrm), .TxCtrlEndFrm(TxCtrlEndFrm), .SendingCtrlFrm(SendingCtrlFrm),
 269  .CtrlMux(CtrlMux), .ControlData(ControlData), .WillSendControlFrame(WillSendControlFrame), .BlockTxDone(BlockTxDone)
 270 );
 271
 272
 273
 274 endmodule