eth_ocm/HAL/inc/eth_ocm_phy.h

   1 #ifndef __ETH_OCM_PHY_H__
   2 #define __ETH_OCM_PHY_H__
   3
   4 #include "eth_ocm_regs.h"
   5 #include "eth_ocm.h"
   6
   7 /* Enumeration of commonly-used PHY registers */
   8 #define ETH_OCM_PHY_ADDR_CONTROL    0x0
   9 #define ETH_OCM_PHY_ADDR_STATUS     0x1
  10 #define ETH_OCM_PHY_ADDR_PHY_ID1    0x2
  11 #define ETH_OCM_PHY_ADDR_PHY_ID2    0x3
  12 #define ETH_OCM_PHY_ADDR_ADV        0x4
  13 #define ETH_OCM_PHY_ADDR_PHY_REMADV 0x5
  14
  15 #define ETH_OCM_USE_INTERNAL_PHY_INIT
  16
  17 // Various PHY IDs
  18 #define ETH_OCM_PHYID_LXT972A       0x001378E2  /* Intel LXT972A */
  19 #define ETH_OCM_PHYID_MVL                   0x0141              /* Marvell 88E1111 */
  20 #define ETH_OCM_PHYID_DP83848C      0x20005C90  /* National DP83848C */
  21 #define ETH_OCM_PHYID_VCS8641       0x00070431  /* Vitesse 8641 Gigabit */
  22
  23 #define ETH_OCM_PHY_TIMEOUT_THRESHOLD   100000
  24
  25 void eth_ocm_set_phy_addr(int base, int phyad, int reg);
  26 void eth_ocm_write_phy_reg(int base, int phyad, int reg, int data);
  27 int  eth_ocm_read_phy_reg(int base, int phyad, int reg);
  28
  29 enum {
  30         PCS_CTL_speed1           = 1<<6,        // speed select
  31         PCS_CTL_speed0           = 1<<13,
  32         PCS_CTL_fullduplex       = 1<<8,        // fullduplex mode select
  33         PCS_CTL_an_restart       = 1<<9,        // Autonegotiation restart command
  34         PCS_CTL_isolate          = 1<<10,       // isolate command
  35         PCS_CTL_powerdown        = 1<<11,       // powerdown command
  36         PCS_CTL_an_enable        = 1<<12,       // Autonegotiation enable
  37         PCS_CTL_rx_slpbk         = 1<<14,       // Serial Loopback enable
  38         PCS_CTL_sw_reset         = 1<<15        // perform soft reset
  39
  40 };
  41
  42 /** PCS Status Register Bits. IEEE 801.2 Clause 22.2.4.2
  43  */
  44 enum {
  45         PCS_ST_has_extcap   = 1<<0,             // PHY has extended capabilities registers
  46         PCS_ST_rx_sync      = 1<<2,             // RX is in sync (8B/10B codes o.k.)
  47         PCS_ST_an_ability   = 1<<3,             // PHY supports autonegotiation
  48         PCS_ST_rem_fault    = 1<<4,             // Autonegotiation completed
  49         PCS_ST_an_done      = 1<<5
  50
  51 };
  52
  53
  54 #endif  //__ETH_OCM_PHY_H__