| blob | 3359193b18dcddfca6c169fd38215805da45d946 |
1 #\r
2 # This class.ptf file built by Component Editor\r
3 # 2008.02.19.16:45:25\r
4 #\r
5 # DO NOT MODIFY THIS FILE\r
6 # If you hand-modify this file you will likely\r
7 # interfere with Component Editor's ability to\r
8 # read and edit it. And then Component Editor\r
9 # will overwrite your changes anyway. So, for\r
10 # the very best results, just relax and\r
11 # DO NOT MODIFY THIS FILE\r
12 #\r
13 CLASS eth_ocm\r
14 {\r
15 CB_GENERATOR \r
16 {\r
17 HDL_FILES \r
18 {\r
19 FILE \r
20 {\r
21 use_in_simulation = "1";\r
22 use_in_synthesis = "1";\r
23 type = "verilog";\r
24 filepath = "eth_ocm.v";\r
25 }\r
26 \r
27 }\r
28 top_module_name = "eth_ocm.v:eth_ocm";\r
29 emit_system_h = "0";\r
30 }\r
31 MODULE_DEFAULTS global_signals\r
32 {\r
33 class = "eth_ocm";\r
34 class_version = "8.0";\r
35 SYSTEM_BUILDER_INFO \r
36 {\r
37 Instantiate_In_System_Module = "1";\r
38 Has_Clock = "1";\r
39 Top_Level_Ports_Are_Enumerated = "1";\r
40 }\r
41 COMPONENT_BUILDER \r
42 {\r
43 GLS_SETTINGS \r
44 {\r
45 }\r
46 }\r
47 PORT_WIRING \r
48 {\r
49 PORT av_clk\r
50 {\r
51 width = "1";\r
52 width_expression = "";\r
53 direction = "input";\r
54 type = "clk";\r
55 is_shared = "0";\r
56 vhdl_record_name = "";\r
57 vhdl_record_type = "";\r
58 }\r
59 PORT av_reset\r
60 {\r
61 width = "1";\r
62 width_expression = "";\r
63 direction = "input";\r
64 type = "reset";\r
65 is_shared = "0";\r
66 vhdl_record_name = "";\r
67 vhdl_record_type = "";\r
68 }\r
69 PORT mtx_clk_pad_i\r
70 {\r
71 width = "1";\r
72 width_expression = "";\r
73 direction = "input";\r
74 type = "export";\r
75 is_shared = "0";\r
76 vhdl_record_name = "";\r
77 vhdl_record_type = "";\r
78 }\r
79 PORT mtxd_pad_o\r
80 {\r
81 width = "4";\r
82 width_expression = "";\r
83 direction = "output";\r
84 type = "export";\r
85 is_shared = "0";\r
86 vhdl_record_name = "";\r
87 vhdl_record_type = "";\r
88 }\r
89 PORT mtxen_pad_o\r
90 {\r
91 width = "1";\r
92 width_expression = "";\r
93 direction = "output";\r
94 type = "export";\r
95 is_shared = "0";\r
96 vhdl_record_name = "";\r
97 vhdl_record_type = "";\r
98 }\r
99 PORT mtxerr_pad_o\r
100 {\r
101 width = "1";\r
102 width_expression = "";\r
103 direction = "output";\r
104 type = "export";\r
105 is_shared = "0";\r
106 vhdl_record_name = "";\r
107 vhdl_record_type = "";\r
108 }\r
109 PORT mrx_clk_pad_i\r
110 {\r
111 width = "1";\r
112 width_expression = "";\r
113 direction = "input";\r
114 type = "export";\r
115 is_shared = "0";\r
116 vhdl_record_name = "";\r
117 vhdl_record_type = "";\r
118 }\r
119 PORT mrxd_pad_i\r
120 {\r
121 width = "4";\r
122 width_expression = "";\r
123 direction = "input";\r
124 type = "export";\r
125 is_shared = "0";\r
126 vhdl_record_name = "";\r
127 vhdl_record_type = "";\r
128 }\r
129 PORT mrxdv_pad_i\r
130 {\r
131 width = "1";\r
132 width_expression = "";\r
133 direction = "input";\r
134 type = "export";\r
135 is_shared = "0";\r
136 vhdl_record_name = "";\r
137 vhdl_record_type = "";\r
138 }\r
139 PORT mrxerr_pad_i\r
140 {\r
141 width = "1";\r
142 width_expression = "";\r
143 direction = "input";\r
144 type = "export";\r
145 is_shared = "0";\r
146 vhdl_record_name = "";\r
147 vhdl_record_type = "";\r
148 }\r
149 PORT mcoll_pad_i\r
150 {\r
151 width = "1";\r
152 width_expression = "";\r
153 direction = "input";\r
154 type = "export";\r
155 is_shared = "0";\r
156 vhdl_record_name = "";\r
157 vhdl_record_type = "";\r
158 }\r
159 PORT mcrs_pad_i\r
160 {\r
161 width = "1";\r
162 width_expression = "";\r
163 direction = "input";\r
164 type = "export";\r
165 is_shared = "0";\r
166 vhdl_record_name = "";\r
167 vhdl_record_type = "";\r
168 }\r
169 PORT mdc_pad_o\r
170 {\r
171 width = "1";\r
172 width_expression = "";\r
173 direction = "output";\r
174 type = "export";\r
175 is_shared = "0";\r
176 vhdl_record_name = "";\r
177 vhdl_record_type = "";\r
178 }\r
179 PORT md_pad_i\r
180 {\r
181 width = "1";\r
182 width_expression = "";\r
183 direction = "input";\r
184 type = "export";\r
185 is_shared = "0";\r
186 vhdl_record_name = "";\r
187 vhdl_record_type = "";\r
188 }\r
189 PORT md_pad_o\r
190 {\r
191 width = "1";\r
192 width_expression = "";\r
193 direction = "output";\r
194 type = "export";\r
195 is_shared = "0";\r
196 vhdl_record_name = "";\r
197 vhdl_record_type = "";\r
198 }\r
199 PORT md_padoe_o\r
200 {\r
201 width = "1";\r
202 width_expression = "";\r
203 direction = "output";\r
204 type = "export";\r
205 is_shared = "0";\r
206 vhdl_record_name = "";\r
207 vhdl_record_type = "";\r
208 }\r
209 }\r
210 WIZARD_SCRIPT_ARGUMENTS \r
211 {\r
212 Is_Ethernet_Mac = "1";\r
213 hdl_parameters \r
214 {\r
215 total_descriptors = "128";\r
216 tx_fifo_size_in_bytes = "128";\r
217 rx_fifo_size_in_bytes = "4096";\r
218 }\r
219 }\r
220 SIMULATION \r
221 {\r
222 DISPLAY \r
223 {\r
224 SIGNAL x101\r
225 {\r
226 name = "eth_ocm/global_signals";\r
227 format = "Divider";\r
228 }\r
229 SIGNAL x102\r
230 {\r
231 name = "av_clk";\r
232 }\r
233 SIGNAL x103\r
234 {\r
235 name = "av_reset";\r
236 }\r
237 SIGNAL x104\r
238 {\r
239 name = "mtx_clk_pad_i";\r
240 }\r
241 SIGNAL x105\r
242 {\r
243 name = "mtxd_pad_o";\r
244 radix = "hexadecimal";\r
245 }\r
246 SIGNAL x106\r
247 {\r
248 name = "mtxen_pad_o";\r
249 }\r
250 SIGNAL x107\r
251 {\r
252 name = "mtxerr_pad_o";\r
253 }\r
254 SIGNAL x108\r
255 {\r
256 name = "mrx_clk_pad_i";\r
257 }\r
258 SIGNAL x109\r
259 {\r
260 name = "mrxd_pad_i";\r
261 radix = "hexadecimal";\r
262 }\r
263 SIGNAL x110\r
264 {\r
265 name = "mrxdv_pad_i";\r
266 }\r
267 SIGNAL x111\r
268 {\r
269 name = "mrxerr_pad_i";\r
270 }\r
271 SIGNAL x112\r
272 {\r
273 name = "mcoll_pad_i";\r
274 }\r
275 SIGNAL x113\r
276 {\r
277 name = "mcrs_pad_i";\r
278 }\r
279 SIGNAL x114\r
280 {\r
281 name = "mdc_pad_o";\r
282 }\r
283 SIGNAL x115\r
284 {\r
285 name = "md_pad_i";\r
286 }\r
287 SIGNAL x116\r
288 {\r
289 name = "md_pad_o";\r
290 }\r
291 SIGNAL x117\r
292 {\r
293 name = "md_padoe_o";\r
294 }\r
295 SIGNAL x118\r
296 {\r
297 name = "eth_ocm/control_port";\r
298 format = "Divider";\r
299 }\r
300 SIGNAL x119\r
301 {\r
302 name = "av_address";\r
303 radix = "hexadecimal";\r
304 }\r
305 SIGNAL x120\r
306 {\r
307 name = "av_read";\r
308 }\r
309 SIGNAL x121\r
310 {\r
311 name = "av_readdata";\r
312 radix = "hexadecimal";\r
313 }\r
314 SIGNAL x122\r
315 {\r
316 name = "av_write";\r
317 }\r
318 SIGNAL x123\r
319 {\r
320 name = "av_writedata";\r
321 radix = "hexadecimal";\r
322 }\r
323 SIGNAL x124\r
324 {\r
325 name = "av_chipselect";\r
326 }\r
327 SIGNAL x125\r
328 {\r
329 name = "av_waitrequest_n";\r
330 }\r
331 SIGNAL x126\r
332 {\r
333 name = "av_irq";\r
334 }\r
335 SIGNAL x127\r
336 {\r
337 name = "eth_ocm/rx_master";\r
338 format = "Divider";\r
339 }\r
340 SIGNAL x128\r
341 {\r
342 name = "av_rx_address";\r
343 radix = "hexadecimal";\r
344 }\r
345 SIGNAL x129\r
346 {\r
347 name = "av_rx_waitrequest";\r
348 }\r
349 SIGNAL x130\r
350 {\r
351 name = "av_rx_write";\r
352 }\r
353 SIGNAL x131\r
354 {\r
355 name = "av_rx_writedata";\r
356 radix = "hexadecimal";\r
357 }\r
358 SIGNAL x132\r
359 {\r
360 name = "av_rx_byteenable";\r
361 radix = "hexadecimal";\r
362 }\r
363 SIGNAL x133\r
364 {\r
365 name = "eth_ocm/tx_master";\r
366 format = "Divider";\r
367 }\r
368 SIGNAL x134\r
369 {\r
370 name = "av_tx_address";\r
371 radix = "hexadecimal";\r
372 }\r
373 SIGNAL x135\r
374 {\r
375 name = "av_tx_read";\r
376 }\r
377 SIGNAL x136\r
378 {\r
379 name = "av_tx_waitrequest";\r
380 }\r
381 SIGNAL x137\r
382 {\r
383 name = "av_tx_readdata";\r
384 radix = "hexadecimal";\r
385 }\r
386 SIGNAL x138\r
387 {\r
388 name = "av_tx_readdatavalid";\r
389 }\r
390 }\r
391 }\r
392 SLAVE control_port\r
393 {\r
394 SYSTEM_BUILDER_INFO \r
395 {\r
396 Bus_Type = "avalon";\r
397 Address_Group = "1";\r
398 Has_Clock = "0";\r
399 Address_Width = "10";\r
400 Address_Alignment = "native";\r
401 Data_Width = "32";\r
402 Has_Base_Address = "1";\r
403 Has_IRQ = "1";\r
404 Setup_Time = "0";\r
405 Hold_Time = "0";\r
406 Read_Wait_States = "peripheral_controlled";\r
407 Write_Wait_States = "peripheral_controlled";\r
408 Read_Latency = "0";\r
409 Maximum_Pending_Read_Transactions = "0";\r
410 Active_CS_Through_Read_Latency = "0";\r
411 Is_Printable_Device = "0";\r
412 Is_Memory_Device = "0";\r
413 Is_Readable = "1";\r
414 Is_Writable = "1";\r
415 Minimum_Uninterrupted_Run_Length = "1";\r
416 }\r
417 COMPONENT_BUILDER \r
418 {\r
419 AVS_SETTINGS \r
420 {\r
421 Setup_Value = "0";\r
422 Read_Wait_Value = "0";\r
423 Write_Wait_Value = "0";\r
424 Hold_Value = "0";\r
425 Timing_Units = "cycles";\r
426 Read_Latency_Value = "0";\r
427 Minimum_Arbitration_Shares = "1";\r
428 Active_CS_Through_Read_Latency = "0";\r
429 Max_Pending_Read_Transactions_Value = "1";\r
430 Address_Alignment = "native";\r
431 Is_Printable_Device = "0";\r
432 Interleave_Bursts = "0";\r
433 interface_name = "Avalon Slave";\r
434 external_wait = "1";\r
435 Is_Memory_Device = "0";\r
436 }\r
437 }\r
438 PORT_WIRING \r
439 {\r
440 PORT av_address\r
441 {\r
442 width = "10";\r
443 width_expression = "";\r
444 direction = "input";\r
445 type = "address";\r
446 is_shared = "0";\r
447 vhdl_record_name = "";\r
448 vhdl_record_type = "";\r
449 }\r
450 PORT av_read\r
451 {\r
452 width = "1";\r
453 width_expression = "";\r
454 direction = "input";\r
455 type = "read";\r
456 is_shared = "0";\r
457 vhdl_record_name = "";\r
458 vhdl_record_type = "";\r
459 }\r
460 PORT av_readdata\r
461 {\r
462 width = "32";\r
463 width_expression = "";\r
464 direction = "output";\r
465 type = "readdata";\r
466 is_shared = "0";\r
467 vhdl_record_name = "";\r
468 vhdl_record_type = "";\r
469 }\r
470 PORT av_write\r
471 {\r
472 width = "1";\r
473 width_expression = "";\r
474 direction = "input";\r
475 type = "write";\r
476 is_shared = "0";\r
477 vhdl_record_name = "";\r
478 vhdl_record_type = "";\r
479 }\r
480 PORT av_writedata\r
481 {\r
482 width = "32";\r
483 width_expression = "";\r
484 direction = "input";\r
485 type = "writedata";\r
486 is_shared = "0";\r
487 vhdl_record_name = "";\r
488 vhdl_record_type = "";\r
489 }\r
490 PORT av_chipselect\r
491 {\r
492 width = "1";\r
493 width_expression = "";\r
494 direction = "input";\r
495 type = "chipselect";\r
496 is_shared = "0";\r
497 vhdl_record_name = "";\r
498 vhdl_record_type = "";\r
499 }\r
500 PORT av_waitrequest_n\r
501 {\r
502 width = "1";\r
503 width_expression = "";\r
504 direction = "output";\r
505 type = "waitrequest_n";\r
506 is_shared = "0";\r
507 vhdl_record_name = "";\r
508 vhdl_record_type = "";\r
509 }\r
510 PORT av_irq\r
511 {\r
512 width = "1";\r
513 width_expression = "";\r
514 direction = "output";\r
515 type = "irq";\r
516 is_shared = "0";\r
517 vhdl_record_name = "";\r
518 vhdl_record_type = "";\r
519 }\r
520 }\r
521 }\r
522 MASTER rx_master\r
523 {\r
524 SYSTEM_BUILDER_INFO \r
525 {\r
526 Bus_Type = "avalon";\r
527 Address_Group = "2";\r
528 Has_Clock = "0";\r
529 Address_Width = "32";\r
530 Data_Width = "32";\r
531 Do_Stream_Reads = "0";\r
532 Do_Stream_Writes = "0";\r
533 Is_Asynchronous = "0";\r
534 Has_IRQ = "0";\r
535 Irq_Scheme = "none";\r
536 Interrupt_Range = "";\r
537 Is_Readable = "0";\r
538 Is_Writable = "1";\r
539 Is_Big_Endian = "0";\r
540 Register_Outgoing_Signals = "0";\r
541 }\r
542 COMPONENT_BUILDER \r
543 {\r
544 AVM_SETTINGS \r
545 {\r
546 stream_reads = "0";\r
547 stream_writes = "0";\r
548 irq_width = "0";\r
549 irq_number_width = "0";\r
550 irq_scheme = "none";\r
551 Is_Asynchronous = "0";\r
552 Is_Big_Endian = "0";\r
553 }\r
554 }\r
555 PORT_WIRING \r
556 {\r
557 PORT av_rx_address\r
558 {\r
559 width = "32";\r
560 width_expression = "";\r
561 direction = "output";\r
562 type = "address";\r
563 is_shared = "0";\r
564 vhdl_record_name = "";\r
565 vhdl_record_type = "";\r
566 }\r
567 PORT av_rx_waitrequest\r
568 {\r
569 width = "1";\r
570 width_expression = "";\r
571 direction = "input";\r
572 type = "waitrequest";\r
573 is_shared = "0";\r
574 vhdl_record_name = "";\r
575 vhdl_record_type = "";\r
576 }\r
577 PORT av_rx_write\r
578 {\r
579 width = "1";\r
580 width_expression = "";\r
581 direction = "output";\r
582 type = "write";\r
583 is_shared = "0";\r
584 vhdl_record_name = "";\r
585 vhdl_record_type = "";\r
586 }\r
587 PORT av_rx_writedata\r
588 {\r
589 width = "32";\r
590 width_expression = "";\r
591 direction = "output";\r
592 type = "writedata";\r
593 is_shared = "0";\r
594 vhdl_record_name = "";\r
595 vhdl_record_type = "";\r
596 }\r
597 PORT av_rx_byteenable\r
598 {\r
599 width = "4";\r
600 width_expression = "";\r
601 direction = "output";\r
602 type = "byteenable";\r
603 is_shared = "0";\r
604 vhdl_record_name = "";\r
605 vhdl_record_type = "";\r
606 }\r
607 }\r
608 }\r
609 MASTER tx_master\r
610 {\r
611 SYSTEM_BUILDER_INFO \r
612 {\r
613 Bus_Type = "avalon";\r
614 Address_Group = "3";\r
615 Has_Clock = "0";\r
616 Address_Width = "32";\r
617 Data_Width = "32";\r
618 Do_Stream_Reads = "0";\r
619 Do_Stream_Writes = "0";\r
620 Is_Asynchronous = "0";\r
621 Has_IRQ = "0";\r
622 Irq_Scheme = "none";\r
623 Interrupt_Range = "";\r
624 Is_Readable = "1";\r
625 Is_Writable = "0";\r
626 Is_Big_Endian = "0";\r
627 Register_Outgoing_Signals = "0";\r
628 }\r
629 COMPONENT_BUILDER \r
630 {\r
631 AVM_SETTINGS \r
632 {\r
633 stream_reads = "0";\r
634 stream_writes = "0";\r
635 irq_width = "0";\r
636 irq_number_width = "0";\r
637 irq_scheme = "none";\r
638 Is_Asynchronous = "0";\r
639 Is_Big_Endian = "0";\r
640 }\r
641 }\r
642 PORT_WIRING \r
643 {\r
644 PORT av_tx_address\r
645 {\r
646 width = "32";\r
647 width_expression = "";\r
648 direction = "output";\r
649 type = "address";\r
650 is_shared = "0";\r
651 vhdl_record_name = "";\r
652 vhdl_record_type = "";\r
653 }\r
654 PORT av_tx_read\r
655 {\r
656 width = "1";\r
657 width_expression = "";\r
658 direction = "output";\r
659 type = "read";\r
660 is_shared = "0";\r
661 vhdl_record_name = "";\r
662 vhdl_record_type = "";\r
663 }\r
664 PORT av_tx_waitrequest\r
665 {\r
666 width = "1";\r
667 width_expression = "";\r
668 direction = "input";\r
669 type = "waitrequest";\r
670 is_shared = "0";\r
671 vhdl_record_name = "";\r
672 vhdl_record_type = "";\r
673 }\r
674 PORT av_tx_readdata\r
675 {\r
676 width = "32";\r
677 width_expression = "";\r
678 direction = "input";\r
679 type = "readdata";\r
680 is_shared = "0";\r
681 vhdl_record_name = "";\r
682 vhdl_record_type = "";\r
683 }\r
684 PORT av_tx_readdatavalid\r
685 {\r
686 width = "1";\r
687 width_expression = "";\r
688 direction = "input";\r
689 type = "readdatavalid";\r
690 is_shared = "0";\r
691 vhdl_record_name = "";\r
692 vhdl_record_type = "";\r
693 }\r
694 }\r
695 }\r
696 }\r
697 USER_INTERFACE \r
698 {\r
699 USER_LABELS \r
700 {\r
701 name = "OpenCores 10/100 Ethernet MAC Avalon";\r
702 technology = "Interface Protocols/Ethernet";\r
703 }\r
704 WIZARD_UI the_wizard_ui\r
705 {\r
706 title = "OpenCores 10/100 Ethernet MAC Avalon - {{ $MOD }}";\r
707 CONTEXT \r
708 {\r
709 H = "WIZARD_SCRIPT_ARGUMENTS/hdl_parameters";\r
710 M = "";\r
711 SBI_global_signals = "SYSTEM_BUILDER_INFO";\r
712 SBI_control_port = "SLAVE control_port/SYSTEM_BUILDER_INFO";\r
713 SBI_rx_master = "MASTER rx_master/SYSTEM_BUILDER_INFO";\r
714 SBI_tx_master = "MASTER tx_master/SYSTEM_BUILDER_INFO";\r
715 }\r
716 PAGES main\r
717 {\r
718 PAGE 1\r
719 {\r
720 align = "left";\r
721 title = "<b>eth_ocm 7.2</b> Settings";\r
722 layout = "vertical";\r
723 TEXT \r
724 {\r
725 title = "Built on: 2008.02.19.16:45:25";\r
726 }\r
727 TEXT \r
728 {\r
729 title = "Class name: eth_ocm";\r
730 }\r
731 TEXT \r
732 {\r
733 title = "Class version: 7.2";\r
734 }\r
735 TEXT \r
736 {\r
737 title = "Component name: eth_ocm";\r
738 }\r
739 TEXT \r
740 {\r
741 title = "Component Group: Interface Protocols/Ethernet";\r
742 }\r
743 GROUP parameters\r
744 {\r
745 title = "Parameters";\r
746 layout = "form";\r
747 align = "left";\r
748 EDIT e1\r
749 {\r
750 id = "TOTAL_DESCRIPTORS";\r
751 editable = "1";\r
752 title = "TOTAL_DESCRIPTORS:";\r
753 columns = "40";\r
754 tooltip = "default value: 128";\r
755 DATA \r
756 {\r
757 $H/total_descriptors = "$";\r
758 }\r
759 q = "'";\r
760 warning = "{{ if(!(regexp('ugly_'+$H/total_descriptors,'ugly_[0-9]*'+$q+'[bB][01][_01]*')||regexp('ugly_'+$H/total_descriptors,'ugly_[0-9]*'+$q+'[hH][0-9a-fA-F][_0-9a-fA-F]*')||regexp('ugly_'+$H/total_descriptors,'ugly_[0-9]*'+$q+'[oO][0-7][_0-7]*')||regexp('ugly_'+$H/total_descriptors,'ugly_0x[0-9a-fA-F]+')||regexp('ugly_'+$H/total_descriptors,'ugly_-?[0-9]+')))'TOTAL_DESCRIPTORS must be numeric constant, not '+$H/total_descriptors; }}";\r
761 }\r
762 EDIT e2\r
763 {\r
764 id = "TX_FIFO_SIZE_IN_BYTES";\r
765 editable = "1";\r
766 title = "TX_FIFO_SIZE_IN_BYTES:";\r
767 columns = "40";\r
768 tooltip = "default value: 128";\r
769 DATA \r
770 {\r
771 $H/tx_fifo_size_in_bytes = "$";\r
772 }\r
773 q = "'";\r
774 warning = "{{ if(!(regexp('ugly_'+$H/tx_fifo_size_in_bytes,'ugly_[0-9]*'+$q+'[bB][01][_01]*')||regexp('ugly_'+$H/tx_fifo_size_in_bytes,'ugly_[0-9]*'+$q+'[hH][0-9a-fA-F][_0-9a-fA-F]*')||regexp('ugly_'+$H/tx_fifo_size_in_bytes,'ugly_[0-9]*'+$q+'[oO][0-7][_0-7]*')||regexp('ugly_'+$H/tx_fifo_size_in_bytes,'ugly_0x[0-9a-fA-F]+')||regexp('ugly_'+$H/tx_fifo_size_in_bytes,'ugly_-?[0-9]+')))'TX_FIFO_SIZE_IN_BYTES must be numeric constant, not '+$H/tx_fifo_size_in_bytes; }}";\r
775 }\r
776 EDIT e3\r
777 {\r
778 id = "RX_FIFO_SIZE_IN_BYTES";\r
779 editable = "1";\r
780 title = "RX_FIFO_SIZE_IN_BYTES:";\r
781 columns = "40";\r
782 tooltip = "default value: 4096";\r
783 DATA \r
784 {\r
785 $H/rx_fifo_size_in_bytes = "$";\r
786 }\r
787 q = "'";\r
788 warning = "{{ if(!(regexp('ugly_'+$H/rx_fifo_size_in_bytes,'ugly_[0-9]*'+$q+'[bB][01][_01]*')||regexp('ugly_'+$H/rx_fifo_size_in_bytes,'ugly_[0-9]*'+$q+'[hH][0-9a-fA-F][_0-9a-fA-F]*')||regexp('ugly_'+$H/rx_fifo_size_in_bytes,'ugly_[0-9]*'+$q+'[oO][0-7][_0-7]*')||regexp('ugly_'+$H/rx_fifo_size_in_bytes,'ugly_0x[0-9a-fA-F]+')||regexp('ugly_'+$H/rx_fifo_size_in_bytes,'ugly_-?[0-9]+')))'RX_FIFO_SIZE_IN_BYTES must be numeric constant, not '+$H/rx_fifo_size_in_bytes; }}";\r
789 }\r
790 }\r
791 }\r
792 }\r
793 }\r
794 }\r
795 SOPC_Builder_Version = "7.20";\r
796 COMPONENT_BUILDER \r
797 {\r
798 HDL_PARAMETERS \r
799 {\r
800 # generated by CBDocument.getParameterContainer\r
801 # used only by Component Editor\r
802 HDL_PARAMETER total_descriptors\r
803 {\r
804 parameter_name = "TOTAL_DESCRIPTORS";\r
805 type = "integer";\r
806 default_value = "128";\r
807 editable = "1";\r
808 tooltip = "";\r
809 }\r
810 HDL_PARAMETER tx_fifo_size_in_bytes\r
811 {\r
812 parameter_name = "TX_FIFO_SIZE_IN_BYTES";\r
813 type = "integer";\r
814 default_value = "128";\r
815 editable = "1";\r
816 tooltip = "";\r
817 }\r
818 HDL_PARAMETER rx_fifo_size_in_bytes\r
819 {\r
820 parameter_name = "RX_FIFO_SIZE_IN_BYTES";\r
821 type = "integer";\r
822 default_value = "4096";\r
823 editable = "1";\r
824 tooltip = "";\r
825 }\r
826 }\r
827 SW_FILES \r
828 {\r
829 }\r
830 built_on = "2008.02.19.16:45:25";\r
831 CACHED_HDL_INFO \r
832 {\r
833 # cached hdl info, emitted by CBFrameRealtime.getDocumentCachedHDLInfoSection\r
834 # used only by Component Builder\r
835 }\r
836 }\r
837 ASSOCIATED_FILES \r
838 {\r
839 Add_Program = "the_wizard_ui";\r
840 Edit_Program = "the_wizard_ui";\r
841 Generator_Program = "cb_generator.pl";\r
842 }\r
843 }\r