ee_core/src/spu.c

   1 /*
   2   spu.c Open PS2 Loader
   3
   4   Copyright 2009-2010, Ifcaro, jimmikaelkael & Polo
   5   Copyright 2006-2008 Polo
   6   Licenced under Academic Free License version 3.0
   7   Review OpenUsbLd README & LICENSE files for further details.
   8
   9   Reset SPU function taken from PS2SDK freesd.
  10   Copyright (c) 2004 TyRaNiD <tiraniddo@hotmail.com>
  11   Copyright (c) 2004,2007 Lukasz Bruun <mail@lukasz.dk>
  12 */
  13
  14 #include "ee_core.h"
  15 #include "util.h"
  16
  17
  18 // SPU2 Registers
  19 #define U16_REGISTER(x)    ((volatile u16 *) (0xBF900000 | (x)))
  20 #define U32_REGISTER(x)    ((volatile u32 *) (0xBF800000 | (x)))
  21 // SD_CORE_ATTR Macros
  22 #define SD_SPU2_ON                                      (1 << 15)
  23 // SPU DMA Channels 0,1 - 1088 bytes apart
  24 #define SD_DMA_CHCR(ch)     ((volatile u32*)(0xBF8010C8+(ch*1088)))
  25 #define SD_DMA_START                (1 << 24)
  26 // SPDIF OUT
  27 #define SD_C_SPDIF_OUT                  ((volatile u16*)0xBF9007C0)
  28 // Base of SPU2 regs is 0x0xBF900000
  29 #define SD_BASE_REG(reg)    ((volatile u16 *)(0xBF900000 + reg))
  30 #define SD_A_REG(core, reg) SD_BASE_REG(0x1A0 + ((core) << 10) + (reg))
  31 #define SD_A_KOFF_HI(core)  SD_A_REG((core), 0x04)
  32 #define SD_A_KOFF_LO(core)  SD_A_REG((core), 0x06)
  33 #define SD_P_REG(core, reg) SD_BASE_REG(0x760 + ((core) * 40) + (reg))
  34 #define SD_P_MVOLL(core)    SD_P_REG((core), 0x00)
  35 #define SD_P_MVOLR(core)    SD_P_REG((core), 0x02)
  36 #define SD_S_REG(core, reg) SD_BASE_REG(0x180 + ((core) << 10) + (reg))
  37 #define SD_S_PMON_HI(core)  SD_S_REG((core), 0x00)
  38 #define SD_S_PMON_LO(core)  SD_S_REG((core), 0x02)
  39 #define SD_S_NON_HI(core)   SD_S_REG((core), 0x04)
  40 #define SD_S_NON_LO(core)   SD_S_REG((core), 0x06)
  41 #define SD_CORE_ATTR(core)  SD_S_REG((core), 0x1A)
  42
  43
  44 // Reset SPU sound processor
  45 void ResetSPU()
  46 {
  47         u32 core;
  48         volatile u16 *statx;
  49
  50         DIntr();
  51         ee_kmode_enter();
  52
  53         // Stop SPU Dma Core 0
  54         *SD_DMA_CHCR(0) &= ~SD_DMA_START;
  55         *U16_REGISTER(0x1B0) = 0;
  56
  57         // Stop SPU Dma Core 1
  58         *SD_DMA_CHCR(1) &= ~SD_DMA_START;
  59         *U16_REGISTER(0x1B0 +  1024) = 0;
  60
  61         // Initialize SPU2
  62         *U32_REGISTER(0x1404)  = 0xBF900000;
  63         *U32_REGISTER(0x140C)  = 0xBF900800;
  64         *U32_REGISTER(0x10F0) |= 0x80000;
  65         *U32_REGISTER(0x1570) |= 8;
  66         *U32_REGISTER(0x1014)  = 0x200B31E1;
  67         *U32_REGISTER(0x1414)  = 0x200B31E1;
  68
  69         *SD_C_SPDIF_OUT = 0;
  70         delay(1);
  71         *SD_C_SPDIF_OUT = 0x8000;
  72         delay(1);
  73
  74         *U32_REGISTER(0x10F0) |= 0xB0000;
  75
  76         for(core=0; core < 2; core++)
  77         {
  78                 *U16_REGISTER(0x1B0)    = 0;
  79                 *SD_CORE_ATTR(core)             = 0;
  80                 delay(1);
  81                 *SD_CORE_ATTR(core)             = SD_SPU2_ON;
  82
  83                 *SD_P_MVOLL(core)               = 0;
  84                 *SD_P_MVOLR(core)               = 0;
  85
  86                 statx = U16_REGISTER(0x344 + (core * 1024));
  87
  88                 int i;
  89                 for (i=0; i<=0xf00; i++) {
  90                         if (!(*statx & 0x7FF))
  91                                 break;
  92                 }
  93
  94                 *SD_A_KOFF_HI(core)             = 0xFFFF;
  95                 *SD_A_KOFF_LO(core)             = 0xFFFF; // Should probably only be 0xFF
  96         }
  97
  98         *SD_S_PMON_HI(1)        = 0;
  99         *SD_S_PMON_LO(1)        = 0;
 100         *SD_S_NON_HI(1)         = 0;
 101         *SD_S_NON_LO(1)         = 0;
 102
 103         ee_kmode_exit();
 104         EIntr();
 105 }
 106