| blob | 9cc6bdc13966991e4d272188f89d3fe93aee77ed |
1 /dts-v1/;
3 / {
4 #address-cells = <0x1>;
5 #size-cells = <0x1>;
6 compatible = "xlnx,microblaze";
7 model = "testing";
9 memory@90000000 {
10 device_type = "memory";
11 reg = <0x90000000 0x8000000>;
12 };
14 chosen {
15 bootargs = "console=ttyUL0,115200";
16 linux,stdout-path = "/plb@0/serial@84000000";
17 };
19 cpus {
20 #address-cells = <0x1>;
21 #cpus = <0x1>;
22 #size-cells = <0x0>;
24 cpu@0 {
25 clock-frequency = <0x3b9aca0>;
26 compatible = "xlnx,microblaze-7.10.d";
27 d-cache-baseaddr = <0x90000000>;
28 d-cache-highaddr = <0x97ffffff>;
29 d-cache-line-size = <0x10>;
30 d-cache-size = <0x800>;
31 device_type = "cpu";
32 i-cache-baseaddr = <0x90000000>;
33 i-cache-highaddr = <0x97ffffff>;
34 i-cache-line-size = <0x10>;
35 i-cache-size = <0x800>;
36 model = "microblaze,7.10.d";
37 reg = <0x0>;
38 timebase-frequency = <0x3b9aca0>;
39 xlnx,addr-tag-bits = <0x10>;
40 xlnx,allow-dcache-wr = <0x1>;
41 xlnx,allow-icache-wr = <0x1>;
42 xlnx,area-optimized = <0x0>;
43 xlnx,cache-byte-size = <0x800>;
44 xlnx,d-lmb = <0x1>;
45 xlnx,d-opb = <0x0>;
46 xlnx,d-plb = <0x1>;
47 xlnx,data-size = <0x20>;
48 xlnx,dcache-addr-tag = <0x10>;
49 xlnx,dcache-always-used = <0x0>;
50 xlnx,dcache-byte-size = <0x800>;
51 xlnx,dcache-line-len = <0x4>;
52 xlnx,dcache-use-fsl = <0x1>;
53 xlnx,debug-enabled = <0x1>;
54 xlnx,div-zero-exception = <0x0>;
55 xlnx,dopb-bus-exception = <0x0>;
56 xlnx,dynamic-bus-sizing = <0x1>;
57 xlnx,edge-is-positive = <0x1>;
58 xlnx,family = "spartan3adsp";
59 xlnx,fpu-exception = <0x0>;
60 xlnx,fsl-data-size = <0x20>;
61 xlnx,fsl-exception = <0x0>;
62 xlnx,fsl-links = <0x0>;
63 xlnx,i-lmb = <0x1>;
64 xlnx,i-opb = <0x0>;
65 xlnx,i-plb = <0x1>;
66 xlnx,icache-always-used = <0x0>;
67 xlnx,icache-line-len = <0x4>;
68 xlnx,icache-use-fsl = <0x1>;
69 xlnx,ill-opcode-exception = <0x0>;
70 xlnx,instance = "microblaze_0";
71 xlnx,interconnect = <0x1>;
72 xlnx,interrupt-is-edge = <0x0>;
73 xlnx,iopb-bus-exception = <0x0>;
74 xlnx,mmu-dtlb-size = <0x4>;
75 xlnx,mmu-itlb-size = <0x2>;
76 xlnx,mmu-tlb-access = <0x3>;
77 xlnx,mmu-zones = <0x10>;
78 xlnx,number-of-pc-brk = <0x3>;
79 xlnx,number-of-rd-addr-brk = <0x2>;
80 xlnx,number-of-wr-addr-brk = <0x2>;
81 xlnx,opcode-0x0-illegal = <0x0>;
82 xlnx,pvr = <0x1>;
83 xlnx,pvr-user1 = <0x0>;
84 xlnx,pvr-user2 = <0x0>;
85 xlnx,reset-msr = <0x0>;
86 xlnx,sco = <0x0>;
87 xlnx,unaligned-exceptions = <0x1>;
88 xlnx,use-barrel = <0x1>;
89 xlnx,use-dcache = <0x1>;
90 xlnx,use-div = <0x0>;
91 xlnx,use-ext-brk = <0x1>;
92 xlnx,use-ext-nm-brk = <0x1>;
93 xlnx,use-extended-fsl-instr = <0x0>;
94 xlnx,use-fpu = <0x0>;
95 xlnx,use-hw-mul = <0x1>;
96 xlnx,use-icache = <0x1>;
97 xlnx,use-interrupt = <0x1>;
98 xlnx,use-mmu = <0x3>;
99 xlnx,use-msr-instr = <0x1>;
100 xlnx,use-pcmp-instr = <0x1>;
101 };
102 };
104 plb@0 {
105 #address-cells = <0x1>;
106 #size-cells = <0x1>;
107 compatible = "xlnx,plb-v46-1.03.a", "simple-bus";
108 ranges;
110 ethernet@81000000 {
111 compatible = "xlnx,xps-ethernetlite-2.00.b";
112 device_type = "network";
113 interrupt-parent = <0x1>;
114 interrupts = <0x1 0x0>;
115 local-mac-address = [02 00 00 00 00 00];
116 reg = <0x81000000 0x10000>;
117 xlnx,duplex = <0x1>;
118 xlnx,family = "spartan3adsp";
119 xlnx,rx-ping-pong = <0x0>;
120 xlnx,tx-ping-pong = <0x0>;
121 };
123 flash@a0000000 {
124 #address-cells = <1>;
125 #size-cells = <1>;
126 bank-width = <0x1>;
127 compatible = "xlnx,xps-mch-emc-2.00.a", "cfi-flash";
128 reg = <0xa0000000 0x1000000>;
129 xlnx,family = "spartan3adsp";
130 xlnx,include-datawidth-matching-0 = <0x1>;
131 xlnx,include-datawidth-matching-1 = <0x0>;
132 xlnx,include-datawidth-matching-2 = <0x0>;
133 xlnx,include-datawidth-matching-3 = <0x0>;
134 xlnx,include-negedge-ioregs = <0x0>;
135 xlnx,include-plb-ipif = <0x1>;
136 xlnx,include-wrbuf = <0x1>;
137 xlnx,max-mem-width = <0x8>;
138 xlnx,mch-native-dwidth = <0x20>;
139 xlnx,mch-plb-clk-period-ps = <0x3e80>;
140 xlnx,mch-splb-awidth = <0x20>;
141 xlnx,mch0-accessbuf-depth = <0x10>;
142 xlnx,mch0-protocol = <0x0>;
143 xlnx,mch0-rddatabuf-depth = <0x10>;
144 xlnx,mch1-accessbuf-depth = <0x10>;
145 xlnx,mch1-protocol = <0x0>;
146 xlnx,mch1-rddatabuf-depth = <0x10>;
147 xlnx,mch2-accessbuf-depth = <0x10>;
148 xlnx,mch2-protocol = <0x0>;
149 xlnx,mch2-rddatabuf-depth = <0x10>;
150 xlnx,mch3-accessbuf-depth = <0x10>;
151 xlnx,mch3-protocol = <0x0>;
152 xlnx,mch3-rddatabuf-depth = <0x10>;
153 xlnx,mem0-width = <0x8>;
154 xlnx,mem1-width = <0x20>;
155 xlnx,mem2-width = <0x20>;
156 xlnx,mem3-width = <0x20>;
157 xlnx,num-banks-mem = <0x1>;
158 xlnx,num-channels = <0x0>;
159 xlnx,priority-mode = <0x0>;
160 xlnx,synch-mem-0 = <0x0>;
161 xlnx,synch-mem-1 = <0x0>;
162 xlnx,synch-mem-2 = <0x0>;
163 xlnx,synch-mem-3 = <0x0>;
164 xlnx,synch-pipedelay-0 = <0x2>;
165 xlnx,synch-pipedelay-1 = <0x2>;
166 xlnx,synch-pipedelay-2 = <0x2>;
167 xlnx,synch-pipedelay-3 = <0x2>;
168 xlnx,tavdv-ps-mem-0 = <0x11170>;
169 xlnx,tavdv-ps-mem-1 = <0x3a98>;
170 xlnx,tavdv-ps-mem-2 = <0x3a98>;
171 xlnx,tavdv-ps-mem-3 = <0x3a98>;
172 xlnx,tcedv-ps-mem-0 = <0x11170>;
173 xlnx,tcedv-ps-mem-1 = <0x3a98>;
174 xlnx,tcedv-ps-mem-2 = <0x3a98>;
175 xlnx,tcedv-ps-mem-3 = <0x3a98>;
176 xlnx,thzce-ps-mem-0 = <0x61a8>;
177 xlnx,thzce-ps-mem-1 = <0x1b58>;
178 xlnx,thzce-ps-mem-2 = <0x1b58>;
179 xlnx,thzce-ps-mem-3 = <0x1b58>;
180 xlnx,thzoe-ps-mem-0 = <0x61a8>;
181 xlnx,thzoe-ps-mem-1 = <0x1b58>;
182 xlnx,thzoe-ps-mem-2 = <0x1b58>;
183 xlnx,thzoe-ps-mem-3 = <0x1b58>;
184 xlnx,tlzwe-ps-mem-0 = <0x1388>;
185 xlnx,tlzwe-ps-mem-1 = <0x0>;
186 xlnx,tlzwe-ps-mem-2 = <0x0>;
187 xlnx,tlzwe-ps-mem-3 = <0x0>;
188 xlnx,twc-ps-mem-0 = <0x11170>;
189 xlnx,twc-ps-mem-1 = <0x3a98>;
190 xlnx,twc-ps-mem-2 = <0x3a98>;
191 xlnx,twc-ps-mem-3 = <0x3a98>;
192 xlnx,twp-ps-mem-0 = <0xafc8>;
193 xlnx,twp-ps-mem-1 = <0x2ee0>;
194 xlnx,twp-ps-mem-2 = <0x2ee0>;
195 xlnx,twp-ps-mem-3 = <0x2ee0>;
196 xlnx,xcl0-linesize = <0x4>;
197 xlnx,xcl0-writexfer = <0x1>;
198 xlnx,xcl1-linesize = <0x4>;
199 xlnx,xcl1-writexfer = <0x1>;
200 xlnx,xcl2-linesize = <0x4>;
201 xlnx,xcl2-writexfer = <0x1>;
202 xlnx,xcl3-linesize = <0x4>;
203 xlnx,xcl3-writexfer = <0x1>;
204 partition@0x00000000 {
205 label = "rootfs";
206 reg = <0x00000000 0x01000000>;
207 };
208 };
210 gpio@81400000 {
211 compatible = "xlnx,xps-gpio-1.00.a";
212 interrupt-parent = <0x1>;
213 interrupts = <0x2 0x2>;
214 reg = <0x81400000 0x10000>;
215 xlnx,all-inputs = <0x0>;
216 xlnx,all-inputs-2 = <0x0>;
217 xlnx,dout-default = <0x0>;
218 xlnx,dout-default-2 = <0x0>;
219 xlnx,family = "spartan3adsp";
220 xlnx,gpio-width = <0x8>;
221 xlnx,interrupt-present = <0x1>;
222 xlnx,is-bidir = <0x0>;
223 xlnx,is-bidir-2 = <0x1>;
224 xlnx,is-dual = <0x0>;
225 xlnx,tri-default = <0xffffffff>;
226 xlnx,tri-default-2 = <0xffffffff>;
227 };
229 serial@84000000 {
230 clock-frequency = <0x3b9aca0>;
231 compatible = "xlnx,xps-uartlite-1.00.a";
232 current-speed = <0x1c200>;
233 device_type = "serial";
234 interrupt-parent = <0x1>;
235 interrupts = <0x3 0x0>;
236 port-number = <0x0>;
237 reg = <0x84000000 0x10000>;
238 xlnx,baudrate = <0x1c200>;
239 xlnx,data-bits = <0x8>;
240 xlnx,family = "spartan3adsp";
241 xlnx,odd-parity = <0x0>;
242 xlnx,use-parity = <0x0>;
243 };
245 debug@84400000 {
246 compatible = "xlnx,mdm-1.00.d";
247 reg = <0x84400000 0x10000>;
248 xlnx,family = "spartan3adsp";
249 xlnx,interconnect = <0x1>;
250 xlnx,jtag-chain = <0x2>;
251 xlnx,mb-dbg-ports = <0x1>;
252 xlnx,uart-width = <0x8>;
253 xlnx,use-uart = <0x1>;
254 xlnx,write-fsl-ports = <0x0>;
255 };
257 mpmc@90000000 {
258 #address-cells = <0x1>;
259 #size-cells = <0x1>;
260 compatible = "xlnx,mpmc-4.03.a";
261 };
263 interrupt-controller@81800000 {
264 #interrupt-cells = <0x2>;
265 compatible = "xlnx,xps-intc-1.00.a";
266 interrupt-controller;
267 reg = <0x81800000 0x10000>;
268 xlnx,kind-of-intr = <0xa>;
269 xlnx,num-intr-inputs = <0x4>;
270 linux,phandle = <0x1>;
271 };
273 timer@83c00000 {
274 compatible = "xlnx,xps-timer-1.00.a";
275 interrupt-parent = <0x1>;
276 interrupts = <0x0 0x2>;
277 reg = <0x83c00000 0x10000>;
278 xlnx,count-width = <0x20>;
279 xlnx,family = "spartan3adsp";
280 xlnx,gen0-assert = <0x1>;
281 xlnx,gen1-assert = <0x1>;
282 xlnx,one-timer-only = <0x0>;
283 xlnx,trig0-assert = <0x1>;
284 xlnx,trig1-assert = <0x1>;
285 };
286 };
287 };