Modified virtual silicon instantiations.

[or1200.git] / sim / run.sh

verilog +overwrite +turbo+3 ../rtl/verilog/*.v ../bench/wb_sram.v ../bench/tb_or1200.v ../bench/monitor.v +incdir+../bench +incdir+../rtl/verilog \
../lib/art_hssp_512x19/art_hssp_512x19.v ../lib/art_hssp_2048x8/art_hssp_2048x8.v ../lib/art_hdsp_2048x32/art_hdsp_2048x32.v \
../lib/art_hsdp_32x32/art_hsdp_32x32.v ../lib/art_hssp_128x34/art_hssp_128x34.v