Fixed Xilinx trace buffer address. REported by Taylor Su.
commit2b9580376b9b5cc0db4a0eaa21b7e2e031f37ca8
authorlampret <lampret>
Thu, 15 Aug 2002 06:04:11 +0000 (15 06:04 +0000)
committerlampret <lampret>
Thu, 15 Aug 2002 06:04:11 +0000 (15 06:04 +0000)
tree3b22e786afc01461291562179e23fd146a1cc11e
parented21030d5cadaa0eb07edf2858c3848585dcddde
Fixed Xilinx trace buffer address. REported by Taylor Su.
rtl/verilog/or1200_defines.v