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(parent: 335ad4d) | patch
Added variable ack of WB transfers (see NODELAY_WBx).
commit33af307cbca31aacc56e65cebb9a4479278dd9cc
authorlampret <lampret>
Sun, 22 Jul 2001 03:30:05 +0000 (22 03:30 +0000)
committerlampret <lampret>
Sun, 22 Jul 2001 03:30:05 +0000 (22 03:30 +0000)
tree29b66ef38749756e32b97c6a7d35a3eed2e7d037tree | snapshot (tar.gz zip)
parent335ad4d51f71f79372167a5c314b56864cc91f94commit | diff
Added variable ack of WB transfers (see NODELAY_WBx).
bench/wb_sram.v diff | blob | blame | history
32-bit scalar RISC with Harvard microarchitecture, 5 stage integer pipeline, virtual memory support (MMU) and basic DSP capabilities