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(parent: a25e7f3) | patch
Fixed VS RAM instantiation - again.
commit50e99ff92eea409d187a9e30c640d8b9a9a2e4c4
authorlampret <lampret>
Tue, 27 Nov 2001 19:45:04 +0000 (27 19:45 +0000)
committerlampret <lampret>
Tue, 27 Nov 2001 19:45:04 +0000 (27 19:45 +0000)
tree799a0f4ef6b048d6d52071e1997987ec3f34e093tree | snapshot (tar.gz zip)
parenta25e7f3802a082c2c4e5d286423b0bffb5fbd423commit | diff
Fixed VS RAM instantiation - again.
rtl/verilog/generic_spram_512x20.v diff | blob | blame | history
32-bit scalar RISC with Harvard microarchitecture, 5 stage integer pipeline, virtual memory support (MMU) and basic DSP capabilities