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(parent: 00970f5) | patch

commit	ac15e755e1b9a32542693cc53d436bb890d7e8f7
author	lampret <lampret>
	Sat, 7 Sep 2002 05:42:02 +0000 (7 05:42 +0000)
committer	lampret <lampret>
	Sat, 7 Sep 2002 05:42:02 +0000 (7 05:42 +0000)
tree	5fce1696b9929a3760b5a2e5121177a684fdb406	tree \| snapshot (tar.gz zip)
parent	00970f593494d1794b5d3a9e4865405e74b8370e	commit \| diff

Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS.

rtl/verilog/or1200_alu.v		diff \| blob \| blame \| history
rtl/verilog/or1200_cpu.v		diff \| blob \| blame \| history
rtl/verilog/or1200_ctrl.v		diff \| blob \| blame \| history
rtl/verilog/or1200_defines.v		diff \| blob \| blame \| history
rtl/verilog/or1200_sprs.v		diff \| blob \| blame \| history

32-bit scalar RISC with Harvard microarchitecture, 5 stage integer pipeline, virtual memory support (MMU) and basic DSP capabilities