Fixed some ports in instnatiations that were removed from the modules
commitbfb703d186edd692908c7ee60536cb18715d102b
authorlampret <lampret>
Fri, 29 Mar 2002 16:29:37 +0000 (29 16:29 +0000)
committerlampret <lampret>
Fri, 29 Mar 2002 16:29:37 +0000 (29 16:29 +0000)
treec60679a17c95ca27e956e981efb60983ca6bd07c
parentd496e28c68158ac1c787f249498e5a3b397698b3
Fixed some ports in instnatiations that were removed from the modules
rtl/verilog/or1200_cpu.v