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(parent: c4798c3) | patch
Changed define name from OR1200_MEM2REG_FAST to OR1200_IMPL_MEM2REG2
commitfcae54393b7fd0e09915d3299f0fc03f62e29214
authorlampret <lampret>
Thu, 28 Mar 2002 19:14:10 +0000 (28 19:14 +0000)
committerlampret <lampret>
Thu, 28 Mar 2002 19:14:10 +0000 (28 19:14 +0000)
tree44af85ce911f262f39005ec6ec13dad79f801b65tree | snapshot (tar.gz zip)
parentc4798c31943375e32d366a10f5046c48f1a153adcommit | diff
Changed define name from OR1200_MEM2REG_FAST to OR1200_IMPL_MEM2REG2
rtl/verilog/or1200_mem2reg.v diff | blob | blame | history
32-bit scalar RISC with Harvard microarchitecture, 5 stage integer pipeline, virtual memory support (MMU) and basic DSP capabilities