From 7887a25a478e827ba2f6fe2b89e84e7a14d39913 Mon Sep 17 00:00:00 2001 From: lampret Date: Fri, 6 Jun 2003 02:54:47 +0000 Subject: [PATCH] When OR1200_NO_IMMU and OR1200_NO_IC are not both defined or undefined at the same time, results in a IC bug. Fixed. --- rtl/verilog/or1200_ic_fsm.v | 5 ++++- rtl/verilog/or1200_immu_top.v | 40 ++++++++++++++++++++++------------------ 2 files changed, 26 insertions(+), 19 deletions(-) diff --git a/rtl/verilog/or1200_ic_fsm.v b/rtl/verilog/or1200_ic_fsm.v index aa8603c..3fe9f2e 100644 --- a/rtl/verilog/or1200_ic_fsm.v +++ b/rtl/verilog/or1200_ic_fsm.v @@ -44,6 +44,9 @@ // CVS Revision History // // $Log$ +// Revision 1.8 2003/06/06 02:54:47 lampret +// When OR1200_NO_IMMU and OR1200_NO_IC are not both defined or undefined at the same time, results in a IC bug. Fixed. +// // Revision 1.7 2002/03/29 15:16:55 lampret // Some of the warnings fixed. // @@ -148,7 +151,7 @@ reg cache_inhibit; // // Generate of ICRAM write enables // -assign icram_we = {4{load & biudata_valid & !cache_inhibit}}; +assign icram_we = {4{biu_read & biudata_valid & !cache_inhibit}}; assign tag_we = biu_read & biudata_valid & !cache_inhibit; // diff --git a/rtl/verilog/or1200_immu_top.v b/rtl/verilog/or1200_immu_top.v index d05a560..0ecc9f5 100644 --- a/rtl/verilog/or1200_immu_top.v +++ b/rtl/verilog/or1200_immu_top.v @@ -44,6 +44,9 @@ // CVS Revision History // // $Log$ +// Revision 1.12 2003/06/06 02:54:47 lampret +// When OR1200_NO_IMMU and OR1200_NO_IC are not both defined or undefined at the same time, results in a IC bug. Fixed. +// // Revision 1.11 2002/10/17 20:04:40 lampret // Added BIST scan. Special VS RAMs need to be used to implement BIST. // @@ -198,11 +201,11 @@ wire fault; wire miss; wire page_cross; reg [31:0] icpu_adr_o; +reg [31:`OR1200_IMMU_PS] icpu_vpn_r; `ifdef OR1200_NO_IMMU `else reg itlb_en_r; reg dis_spr_access; -reg [31:`OR1200_IMMU_PS] icpu_vpn_r; `endif // @@ -231,6 +234,23 @@ always @(posedge rst or posedge clk) Unsupported !!! `endif +// +// Page cross +// +// Asserted when CPU address crosses page boundary. Most of the time it is zero. +// +assign page_cross = icpu_adr_i[31:`OR1200_IMMU_PS] != icpu_vpn_r; + +// +// Register icpu_adr_i's VPN for use when IMMU is not enabled but PPN is expected to come +// one clock cycle after offset part. +// +always @(posedge clk or posedge rst) + if (rst) + icpu_vpn_r <= #1 {31-`OR1200_IMMU_PS{1'b0}}; + else + icpu_vpn_r <= #1 icpu_adr_i[31:`OR1200_IMMU_PS]; + `ifdef OR1200_NO_IMMU // @@ -239,7 +259,7 @@ Unsupported !!! assign spr_dat_o = 32'h00000000; assign icimmu_adr_o = icpu_adr_i; assign icpu_tag_o = icimmu_tag_i; -assign icimmu_cycstb_o = icpu_cycstb_i; +assign icimmu_cycstb_o = icpu_cycstb_i & ~page_cross; assign icpu_rty_o = icimmu_rty_i; assign icpu_err_o = icimmu_err_i; assign icimmu_ci_o = `OR1200_IMMU_CI; @@ -329,22 +349,6 @@ assign icimmu_cycstb_o = immu_en ? ~(miss | fault) & icpu_cycstb_i & ~page_cross // no cache inhibit. assign icimmu_ci_o = `OR1200_IMMU_CI; -// -// Page cross -// -// Asserted when CPU address crosses page boundary. Most of the time it is zero. -// -assign page_cross = icpu_adr_i[31:`OR1200_IMMU_PS] != icpu_vpn_r; - -// -// Register icpu_adr_i's VPN for use when IMMU is not enabled but PPN is expected to come -// one clock cycle after offset part. -// -always @(posedge clk or posedge rst) - if (rst) - icpu_vpn_r <= #1 {31-`OR1200_IMMU_PS{1'b0}}; - else - icpu_vpn_r <= #1 icpu_adr_i[31:`OR1200_IMMU_PS]; // // Physical address is either translated virtual address or -- 2.11.4.GIT