From ac6b6cf9f128e60e3c2d5227831d46a1d2050207 Mon Sep 17 00:00:00 2001
From: lampret <lampret>
Date: Fri, 18 Jan 2002 14:21:43 +0000
Subject: [PATCH] Fixed 'the NPC single-step fix'.

---
 rtl/verilog/or1200_cpu.v    |  7 ++++++-
 rtl/verilog/or1200_ctrl.v   | 11 +++++++++--
 rtl/verilog/or1200_except.v |  9 ++++++---
 3 files changed, 21 insertions(+), 6 deletions(-)

diff --git a/rtl/verilog/or1200_cpu.v b/rtl/verilog/or1200_cpu.v
index 849e819..7aa1775 100644
--- a/rtl/verilog/or1200_cpu.v
+++ b/rtl/verilog/or1200_cpu.v
@@ -45,6 +45,9 @@
 // CVS Revision History
 //
 // $Log$
+// Revision 1.4  2002/01/18 14:21:43  lampret
+// Fixed 'the NPC single-step fix'.
+//
 // Revision 1.3  2002/01/18 07:56:00  lampret
 // No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
 //
@@ -297,6 +300,7 @@ wire	[31:0]			spr_dat_ppc;
 wire	[31:0]			spr_dat_mac;
 wire				force_dslot_fetch;
 wire				has_dslot;
+wire				ex_void;
 wire				if_stall;
 wire				id_macrc_op;
 wire				ex_macrc_op;
@@ -448,6 +452,7 @@ or1200_ctrl or1200_ctrl(
 	.sig_trap(sig_trap),
 	.force_dslot_fetch(force_dslot_fetch),
 	.has_dslot(has_dslot),
+	.ex_void(ex_void),
 	.id_macrc_op(id_macrc_op),
 	.ex_macrc_op(ex_macrc_op),
 	.rfe(rfe),
@@ -693,7 +698,7 @@ or1200_except or1200_except(
 	.except_start(except_start),
 	.except_started(except_started),
 	.except_stop(except_stop),
-	.has_dslot(has_dslot),
+	.ex_void(ex_void),
 	.spr_dat_ppc(spr_dat_ppc),
 	.spr_dat_npc(spr_dat_npc),
 
diff --git a/rtl/verilog/or1200_ctrl.v b/rtl/verilog/or1200_ctrl.v
index 5e008fd..27ac659 100644
--- a/rtl/verilog/or1200_ctrl.v
+++ b/rtl/verilog/or1200_ctrl.v
@@ -44,6 +44,9 @@
 // CVS Revision History
 //
 // $Log$
+// Revision 1.3  2002/01/18 14:21:43  lampret
+// Fixed 'the NPC single-step fix'.
+//
 // Revision 1.2  2002/01/14 06:18:22  lampret
 // Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
 //
@@ -99,7 +102,7 @@ module or1200_ctrl(
 	rf_addra, rf_addrb, rf_rda, rf_rdb, alu_op, mac_op, shrot_op, comp_op, rf_addrw, rfwb_op,
 	wb_insn, simm, branch_addrofs, lsu_addrofs, sel_a, sel_b, lsu_op,
 	multicycle, spr_addrimm, wbforw_valid, sig_syscall, sig_trap,
-	force_dslot_fetch, has_dslot, id_macrc_op, ex_macrc_op, rfe, except_illegal
+	force_dslot_fetch, has_dslot, ex_void, id_macrc_op, ex_macrc_op, rfe, except_illegal
 );
 
 //
@@ -138,6 +141,7 @@ output					sig_syscall;
 output					sig_trap;
 output					force_dslot_fetch;
 output					has_dslot;
+output					ex_void;
 output					id_macrc_op;
 output					ex_macrc_op;
 output					rfe;
@@ -170,6 +174,7 @@ reg					sig_syscall;
 reg					sig_trap;
 reg					except_illegal;
 reg					ex_macrc_op;
+wire					id_void;
 
 //
 // Register file read addresses
@@ -186,7 +191,9 @@ assign rf_rdb = if_insn[30];
 // SIMON
 // assign force_dslot_fetch = ((|pre_branch_op) & (|lsu_op));
 assign force_dslot_fetch = 1'b0;
-assign has_dslot = |branch_op & ((id_insn[31:26] != `OR1200_OR32_NOP) | !id_insn[0]);
+assign has_dslot = |branch_op & !id_void;
+assign id_void = (id_insn[31:26] == `OR1200_OR32_NOP) & id_insn[0];
+assign ex_void = (ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[0];
 
 //
 // Sign/Zero extension of immediates
diff --git a/rtl/verilog/or1200_except.v b/rtl/verilog/or1200_except.v
index 2a8c496..a4c4cae 100644
--- a/rtl/verilog/or1200_except.v
+++ b/rtl/verilog/or1200_except.v
@@ -44,6 +44,9 @@
 // CVS Revision History
 //
 // $Log$
+// Revision 1.6  2002/01/18 14:21:43  lampret
+// Fixed 'the NPC single-step fix'.
+//
 // Revision 1.5  2002/01/18 07:56:00  lampret
 // No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
 //
@@ -123,7 +126,7 @@ module or1200_except(
 	sig_int, sig_syscall, sig_trap, sig_itlbmiss, sig_immufault, sig_tick,
 	branch_taken, id_freeze, ex_freeze, wb_freeze, if_stall,
 	if_pc, lr_sav, flushpipe, extend_flush, except_type, except_start,
-	except_started, except_stop, has_dslot,
+	except_started, except_stop, ex_void,
 	spr_dat_ppc, spr_dat_npc, datain, du_dsr, epcr_we, eear_we, esr_we, pc_we, epcr, eear,
 	esr, sr, lsu_addr
 );
@@ -170,7 +173,7 @@ output	[`OR1200_EXCEPT_WIDTH-1:0]	except_type;
 output				except_start;
 output				except_started;
 output	[12:0]			except_stop;
-input				has_dslot;
+input				ex_void;
 output	[31:0]			spr_dat_ppc;
 output	[31:0]			spr_dat_npc;
 
@@ -206,7 +209,7 @@ wire				tick_pending;
 assign except_started = extend_flush & except_start;
 assign lr_sav = ex_pc[31:2];
 assign spr_dat_ppc = wb_pc;
-assign spr_dat_npc = has_dslot ? ex_pc : id_pc;
+assign spr_dat_npc = ex_void ? id_pc : ex_pc;
 //assign except_start = (except_type != `OR1200_EXCEPT_NONE);  // damjan
 assign except_start = (except_type != `OR1200_EXCEPT_NONE) & extend_flush;
 assign int_pending = sig_int & sr[`OR1200_SR_IEE] & delayed_iee[2] & ~ex_freeze & ~branch_taken & ~ex_dslot;
-- 
2.11.4.GIT