src/target/firmware/calypso/clock.c

   1 /* Driver for Calypso clock management */
   2
   3 /* (C) 2010 by Harald Welte <laforge@gnumonks.org>
   4  *
   5  * All Rights Reserved
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  */
  18
  19 #include <stdint.h>
  20 #include <stdio.h>
  21
  22 //#define DEBUG
  23 #include <debug.h>
  24
  25 #include <memory.h>
  26 #include <calypso/clock.h>
  27
  28 #define REG_DPLL                0xffff9800
  29 #define DPLL_LOCK               (1 << 0)
  30 #define DPLL_BREAKLN            (1 << 1)
  31 #define DPLL_BYPASS_DIV_SHIFT   2               /* 2 bits */
  32 #define DPLL_PLL_ENABLE         (1 << 4)
  33 #define DPLL_PLL_DIV_SHIFT      5               /* 2 bits */
  34 #define DPLL_PLL_MULT_SHIFT     7               /* 5 bits */
  35 #define DPLL_TEST               (1 << 12)
  36 #define DPLL_IOB                (1 << 13)       /* Initialize on break */
  37 #define DPLL_IAI                (1 << 14)       /* Initialize after Idle */
  38
  39 #define BASE_ADDR_CLKM  0xfffffd00
  40 #define CLKM_REG(m)     (BASE_ADDR_CLKM+(m))
  41
  42 enum clkm_reg {
  43         CNTL_ARM_CLK    = 0,
  44         CNTL_CLK        = 2,
  45         CNTL_RST        = 4,
  46         CNTL_ARM_DIV    = 8,
  47 };
  48
  49 /* CNTL_ARM_CLK */
  50 #define ARM_CLK_BIG_SLEEP       (1 << 0)        /* MCU Master Clock enabled? */
  51 #define ARM_CLK_CLKIN_SEL0      (1 << 1)        /* MCU source clock (0 = DPLL output, 1 = VTCXO or CLKIN */
  52 #define ARM_CLK_CLKIN_SEL       (1 << 2)        /* 0 = VTCXO or 1 = CLKIN */
  53 #define ARM_CLK_MCLK_DIV5       (1 << 3)        /* enable 1.5 or 2.5 division factor */
  54 #define ARM_CLK_MCLK_DIV_SHIFT  4               /* 3 bits */
  55 #define ARM_CLK_DEEP_POWER_SHIFT        8
  56 #define ARM_CLK_DEEP_SLEEP      12
  57
  58 /* CNTL_CLK */
  59 #define CLK_IRQ_CLK_DIS         (1 << 0)        /* IRQ clock control (0 always, 1 according ARM_MCLK_EN) */
  60 #define CLK_BRIDGE_CLK_DIS      (1 << 1)
  61 #define CLK_TIMER_CLK_DIS       (1 << 2)
  62 #define CLK_DPLL_DIS            (1 << 3)        /* 0: DPLL is not stopped during SLEEP */
  63 #define CLK_CLKOUT_EN           (1 << 4)        /* Enable CLKOUT output pins */
  64 #define CLK_EN_IDLE3_FLG        (1 << 5)        /* DSP idle flag control (1 =
  65                                                  * SAM/HOM register forced to HOM when DSP IDLE3) */
  66 #define CLK_VCLKOUT_DIV2        (1 << 6)        /* 1: VCLKOUT-FR is divided by 2 */
  67 #define CLK_VTCXO_DIV2          (1 << 7)        /* 1: VTCXO is dividied by 2 */
  68
  69 #define BASE_ADDR_MEMIF         0xfffffb00
  70 #define MEMIF_REG(x)            (BASE_ADDR_MEMIF+(x))
  71
  72 enum memif_reg {
  73         API_RHEA_CTL    = 0x0e,
  74         EXTRA_CONF      = 0x10,
  75 };
  76
  77 static void dump_reg16(uint32_t addr, char *name)
  78 {
  79         printf("%s=0x%04x\n", name, readw(addr));
  80 }
  81
  82 void calypso_clk_dump(void)
  83 {
  84         dump_reg16(REG_DPLL, "REG_DPLL");
  85         dump_reg16(CLKM_REG(CNTL_ARM_CLK), "CNTL_ARM_CLK");
  86         dump_reg16(CLKM_REG(CNTL_CLK), "CNTL_CLK");
  87         dump_reg16(CLKM_REG(CNTL_RST), "CNTL_RST");
  88         dump_reg16(CLKM_REG(CNTL_ARM_DIV), "CNTL_ARM_DIV");
  89 }
  90
  91 void calypso_pll_set(uint16_t inp)
  92 {
  93         uint8_t mult = inp >> 8;
  94         uint8_t div = inp & 0xff;
  95         uint16_t reg = readw(REG_DPLL);
  96
  97         reg &= ~0x0fe0;
  98         reg |= (div & 0x3) << DPLL_PLL_DIV_SHIFT;
  99         reg |= (mult & 0x1f) << DPLL_PLL_MULT_SHIFT;
 100         reg |= DPLL_PLL_ENABLE;
 101
 102         writew(reg, REG_DPLL);
 103 }
 104
 105 void calypso_reset_set(enum calypso_rst calypso_rst, int active)
 106 {
 107         uint8_t reg = readb(CLKM_REG(CNTL_RST));
 108
 109         if (active)
 110                 reg |= calypso_rst;
 111         else
 112                 reg &= ~calypso_rst;
 113
 114         writeb(reg, CLKM_REG(CNTL_RST));
 115 }
 116
 117 int calypso_reset_get(enum calypso_rst calypso_rst)
 118 {
 119         uint8_t reg = readb(CLKM_REG(CNTL_RST));
 120
 121         if (reg & calypso_rst)
 122                 return 1;
 123         else
 124                 return 0;
 125 }
 126
 127 void calypso_clock_set(uint8_t vtcxo_div2, uint16_t inp, enum mclk_div mclk_div)
 128 {
 129         uint16_t cntl_clock = readw(CLKM_REG(CNTL_CLK));
 130         uint16_t cntl_arm_clk = readw(CLKM_REG(CNTL_ARM_CLK));
 131
 132         /* First set the vtcxo_div2 */
 133         cntl_clock &= ~CLK_VCLKOUT_DIV2;
 134         if (vtcxo_div2)
 135                 cntl_clock |= CLK_VTCXO_DIV2;
 136         else
 137                 cntl_clock &= ~CLK_VTCXO_DIV2;
 138         writew(cntl_clock, CLKM_REG(CNTL_CLK));
 139
 140         /* Then configure the MCLK divider */
 141         cntl_arm_clk &= ~ARM_CLK_CLKIN_SEL0;
 142         if (mclk_div & 0x80) {
 143                 mclk_div &= ~0x80;
 144                 cntl_arm_clk |= ARM_CLK_MCLK_DIV5;
 145         } else
 146                 cntl_arm_clk &= ~ARM_CLK_MCLK_DIV5;
 147         cntl_arm_clk &= ~(0x7 << ARM_CLK_MCLK_DIV_SHIFT);
 148         cntl_arm_clk |= (mclk_div << ARM_CLK_MCLK_DIV_SHIFT);
 149         writew(cntl_arm_clk, CLKM_REG(CNTL_ARM_CLK));
 150
 151         /* Then finally set the PLL */
 152         calypso_pll_set(inp);
 153 }
 154
 155 void calypso_mem_cfg(enum calypso_bank bank, uint8_t ws,
 156                      enum calypso_mem_width width, int we)
 157 {
 158         writew((ws & 0x1f) | ((width & 3) << 5) | ((we & 1) << 7),
 159                BASE_ADDR_MEMIF + bank);
 160 }
 161
 162 void calypso_bootrom(int enable)
 163 {
 164         uint16_t conf = readw(MEMIF_REG(EXTRA_CONF));
 165
 166         conf |= (3 << 8);
 167
 168         if (enable)
 169                 conf &= ~(1 << 9);
 170
 171         writew(conf, MEMIF_REG(EXTRA_CONF));
 172 }
 173
 174 void calypso_debugunit(int enable)
 175 {
 176         uint16_t conf = readw(MEMIF_REG(EXTRA_CONF));
 177
 178         if (enable)
 179                 conf &= ~(1 << 11);
 180         else
 181                 conf |= (1 << 11);
 182
 183         writew(conf, MEMIF_REG(EXTRA_CONF));
 184 }
 185
 186 #define REG_RHEA_CNTL   0xfffff900
 187 #define REG_API_CNTL    0xfffff902
 188 #define REG_ARM_RHEA    0xfffff904
 189
 190 void calypso_rhea_cfg(uint8_t fac0, uint8_t fac1, uint8_t timeout,
 191                       uint8_t ws_h, uint8_t ws_l, uint8_t w_en0, uint8_t w_en1)
 192 {
 193         writew(fac0 | (fac1 << 4) | (timeout << 8), REG_RHEA_CNTL);
 194         writew(ws_h | (ws_l << 5), REG_API_CNTL);
 195         writew(w_en0 | (w_en1 << 1), REG_ARM_RHEA);
 196 }