src/mcas/amd64_defns.h

   1 /*
   2 Copyright (c) 2003, Keir Fraser All rights reserved.
   3
   4 Redistribution and use in source and binary forms, with or without
   5 modification, are permitted provided that the following conditions are
   6 met:
   7
   8     * Redistributions of source code must retain the above copyright
   9     * notice, this list of conditions and the following disclaimer.
  10     * Redistributions in binary form must reproduce the above
  11     * copyright notice, this list of conditions and the following
  12     * disclaimer in the documentation and/or other materials provided
  13     * with the distribution.  Neither the name of the Keir Fraser
  14     * nor the names of its contributors may be used to endorse or
  15     * promote products derived from this software without specific
  16     * prior written permission.
  17
  18 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  19 "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  20 LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  21 A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  22 OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  23 SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  24 LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  25 DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  26 THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  27 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  28 OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  29 */
  30
  31 #ifndef __INTEL_DEFNS_H__
  32 #define __INTEL_DEFNS_H__
  33
  34 #include <pthread.h>
  35 #include <sched.h>
  36
  37 #ifndef X86_64
  38 #define X86_64
  39 #endif
  40
  41 #define CACHE_LINE_SIZE 64
  42
  43 #if 0
  44 #define pthread_mutex_init(_m,_i) \
  45 ({ pthread_mutex_init(_m,_i); (_m)->__m_kind = PTHREAD_MUTEX_ADAPTIVE_NP; })
  46 #endif
  47
  48
  49 /*
  50  * I. Compare-and-swap.
  51  */
  52
  53 /*
  54  * This is a strong barrier! Reads cannot be delayed beyond a later store.
  55  * Reads cannot be hoisted beyond a LOCK prefix. Stores always in-order.
  56  */
  57 #define CAS32(_a, _o, _n)                                    \
  58 ({ __typeof__(_o) __o = _o;                                \
  59    __asm__ __volatile__(                                   \
  60        "lock cmpxchg %3,%1"                                \
  61        : "=a" (__o), "=m" (*(volatile unsigned int *)(_a)) \
  62        :  "0" (__o), "r" (_n) );                           \
  63    __o;                                                    \
  64 })
  65
  66 #define FAS32(_a, _n)                                        \
  67 ({ __typeof__(_n) __o;                                     \
  68    __asm__ __volatile__(                                   \
  69        "lock xchg %0,%1"                                   \
  70        : "=r" (__o), "=m" (*(volatile unsigned int *)(_a)) \
  71        :  "0" (_n) );                                      \
  72    __o;                                                    \
  73 })
  74
  75 #define FAS64(_a, _n)                                      \
  76     ({ __typeof__(_n) __o;                                 \
  77       __asm__ __volatile__(                                \
  78        "xchgq %0,%1"                                       \
  79        : "=r" (__o), "=m" (*(volatile unsigned long long *)(_a)) \
  80        :  "0" (_n)                                         \
  81     );                                                     \
  82    __o;                                                    \
  83 })
  84
  85 /* Valid, but not preferred */
  86 #define CAS64_x86_style(_a, _o, _n)                                        \
  87 ({ __typeof__(_o) __o = _o;                                      \
  88    __asm__ __volatile__(                                         \
  89        "movl %3, %%ecx;"                                         \
  90        "movl %4, %%ebx;"                                         \
  91        "lock cmpxchg8b %1"                                       \
  92        : "=A" (__o), "=m" (*(volatile unsigned long long *)(_a)) \
  93        : "0" (__o), "m" (_n >> 32), "m" (_n)                     \
  94        : "ebx", "ecx" );                                         \
  95    __o;                                                          \
  96 })
  97
  98 #define CAS64(_a, _o, _n)                                        \
  99     ({ __typeof__(_o) __o = _o;                                         \
 100   __asm__ __volatile__ ("lock cmpxchgq %1,%2"                           \
 101                         : "=a" (__o)                                    \
 102                         :"r" (_n),                                      \
 103                          "m" (*(volatile unsigned long long *)(_a)),    \
 104                          "0" (__o)                                      \
 105                         : "memory");                                    \
 106   __o;                                                                  \
 107  })
 108
 109 #define CAS(_x,_o,_n) ((sizeof (*_x) == 4)?CAS32(_x,_o,_n):CAS64(_x,_o,_n))
 110 #define FAS(_x,_n)    ((sizeof (*_x) == 4)?FAS32(_x,_n)   :FAS64(_x,_n))
 111
 112 /* Update Integer location, return Old value. */
 113 #define CASIO CAS
 114 #define FASIO FAS
 115 /* Update Pointer location, return Old value. */
 116 #define CASPO CAS64
 117 #define FASPO FAS64
 118 /* Update 32/64-bit location, return Old value. */
 119 #define CAS32O CAS
 120 #define CAS64O CAS64
 121
 122 /*
 123  * II. Memory barriers.
 124  *  WMB(): All preceding write operations must commit before any later writes.
 125  *  RMB(): All preceding read operations must commit before any later reads.
 126  *  MB():  All preceding memory accesses must commit before any later accesses.
 127  *
 128  *  If the compiler does not observe these barriers (but any sane compiler
 129  *  will!), then VOLATILE should be defined as 'volatile'.
 130  */
 131
 132 #define MB()  __asm__ __volatile__("" : : : "memory")
 133 #define WMB() MB()
 134 #define RMB() MB()
 135 #define VOLATILE                /*volatile */
 136
 137 /* On Intel, CAS is a strong barrier, but not a compile barrier. */
 138 #define RMB_NEAR_CAS() WMB()
 139 #define WMB_NEAR_CAS() WMB()
 140 #define MB_NEAR_CAS()  WMB()
 141
 142
 143 /*
 144  * III. Cycle counter access.
 145  */
 146
 147 typedef unsigned long long tick_t;
 148
 149 #define RDTICK() \
 150   ({ unsigned __a, __d; tick_t __t; \
 151     __asm__ __volatile__ ("rdtsc" : "=a" (__a), "=d" (__d)); \
 152     __t=((unsigned long long) __a) | (((unsigned long long) __d) << 32); \
 153     __t; })
 154
 155
 156 /*
 157  * IV. Types.
 158  */
 159
 160 typedef unsigned char _u8;
 161 typedef unsigned short _u16;
 162 typedef unsigned int _u32;
 163 typedef unsigned long long _u64;
 164
 165 #endif /* __INTEL_DEFNS_H__ */