src/mcas/ia64_defns.h

   1 /*
   2 Copyright (c) 2003, Keir Fraser All rights reserved.
   3
   4 Redistribution and use in source and binary forms, with or without
   5 modification, are permitted provided that the following conditions are
   6 met:
   7
   8     * Redistributions of source code must retain the above copyright
   9     * notice, this list of conditions and the following disclaimer.
  10     * Redistributions in binary form must reproduce the above
  11     * copyright notice, this list of conditions and the following
  12     * disclaimer in the documentation and/or other materials provided
  13     * with the distribution.  Neither the name of the Keir Fraser
  14     * nor the names of its contributors may be used to endorse or
  15     * promote products derived from this software without specific
  16     * prior written permission.
  17
  18 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  19 "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  20 LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  21 A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  22 OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  23 SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  24 LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  25 DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  26 THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  27 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  28 OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  29 */
  30
  31 #ifndef __IA64_DEFNS_H__
  32 #define __IA64_DEFNS_H__
  33
  34 #include <pthread.h>
  35 #include <sched.h>
  36
  37 #ifndef IA64
  38 #define IA64
  39 #endif
  40
  41 #define CACHE_LINE_SIZE 64
  42
  43 /*
  44  * I. Compare-and-swap.
  45  */
  46
  47 #define CAS32(_a, _o, _n)                                               \
  48 ({ __typeof__(_o) __o = _o;                                     \
  49    __asm__ __volatile__("mov ar.ccv=%0 ;;" :: "rO" (_o));       \
  50    __asm__ __volatile__("cmpxchg4.acq %0=%1,%2,ar.ccv ;; "      \
  51        : "=r" (__o), "=m" (*(_a))                               \
  52        :  "r"(_n));                             \
  53    __o;                                                         \
  54 })
  55
  56 #define CAS64(_a, _o, _n)                                               \
  57 ({ __typeof__(_o) __o = _o;                                     \
  58    __asm__ __volatile__("mov ar.ccv=%0 ;;" :: "rO" (_o));       \
  59    __asm__ __volatile__("cmpxchg8.acq %0=%1,%2,ar.ccv ;; "      \
  60        : "=r" (__o), "=m" (*(_a))                               \
  61        :  "r"(_n));                             \
  62    __o;                                                         \
  63 })
  64
  65 #define FAS32(_a, _n)                                           \
  66 ({ __typeof__(_n) __o;                                          \
  67    __asm__ __volatile__("xchg4 %0=%1,%2 ;; "    \
  68        : "=r" (__o), "=m" (*(_a))                               \
  69        :  "r"(_n));                             \
  70    __o;                                                         \
  71 })
  72
  73 #define FAS64(_a, _n)                                           \
  74 ({ __typeof__(_n) __o;                                          \
  75    __asm__ __volatile__("xchg8 %0=%1,%2 ;; "    \
  76        : "=r" (__o), "=m" (*(_a))                               \
  77        :  "r"(_n));                             \
  78    __o;                                                         \
  79 })
  80
  81 #define CAS(_x,_o,_n) ((sizeof (*_x) == 4)?CAS32(_x,_o,_n):CAS64(_x,_o,_n))
  82 #define FAS(_x,_n)    ((sizeof (*_x) == 4)?FAS32(_x,_n)   :FAS64(_x,_n))
  83
  84 /* Update Integer location, return Old value. */
  85 #define CASIO CAS
  86 #define FASIO FAS
  87 /* Update Pointer location, return Old value. */
  88 #define CASPO CAS64
  89 #define FASPO FAS64
  90 /* Update 32/64-bit location, return Old value. */
  91 #define CAS32O CAS32
  92 #define CAS64O CAS64
  93
  94
  95 /*
  96  * II. Memory barriers.
  97  *  WMB(): All preceding write operations must commit before any later writes.
  98  *  RMB(): All preceding read operations must commit before any later reads.
  99  *  MB():  All preceding memory accesses must commit before any later accesses.
 100  *
 101  *  If the compiler does not observe these barriers (but any sane compiler
 102  *  will!), then VOLATILE should be defined as 'volatile'.
 103  */
 104
 105 #define MB()  __asm__ __volatile__ (";; mf ;; " : : : "memory")
 106 #define WMB() MB()
 107 #define RMB() MB()
 108 #define VOLATILE /*volatile*/
 109
 110 /*
 111  * III. Cycle counter access.
 112  */
 113
 114 typedef unsigned long long tick_t;
 115 #define RDTICK() \
 116     ({ tick_t __t; __asm__ __volatile__ ("mov %0=ar.itc ;;" : "=rO" (__t)); __t; })
 117
 118
 119
 120 /*
 121  * IV. Types.
 122  */
 123
 124 typedef unsigned char      _u8;
 125 typedef unsigned short     _u16;
 126 typedef unsigned int       _u32;
 127 typedef unsigned long long _u64;
 128
 129 #endif /* __IA64_DEFNS_H__ */