drivers/serial/bfin_sport_uart.h

   1 /*
   2  * Blackfin On-Chip Sport Emulated UART Driver
   3  *
   4  * Copyright 2006-2008 Analog Devices Inc.
   5  *
   6  * Enter bugs at http://blackfin.uclinux.org/
   7  *
   8  * Licensed under the GPL-2 or later.
   9  */
  10
  11 /*
  12  * This driver and the hardware supported are in term of EE-191 of ADI.
  13  * http://www.analog.com/UploadedFiles/Application_Notes/399447663EE191.pdf
  14  * This application note describe how to implement a UART on a Sharc DSP,
  15  * but this driver is implemented on Blackfin Processor.
  16  * Transmit Frame Sync is not used by this driver to transfer data out.
  17  */
  18
  19 #ifndef _BFIN_SPORT_UART_H
  20 #define _BFIN_SPORT_UART_H
  21
  22 #define OFFSET_TCR1             0x00    /* Transmit Configuration 1 Register */
  23 #define OFFSET_TCR2             0x04    /* Transmit Configuration 2 Register */
  24 #define OFFSET_TCLKDIV          0x08    /* Transmit Serial Clock Divider Register */
  25 #define OFFSET_TFSDIV           0x0C    /* Transmit Frame Sync Divider Register */
  26 #define OFFSET_TX               0x10    /* Transmit Data Register               */
  27 #define OFFSET_RX               0x18    /* Receive Data Register                */
  28 #define OFFSET_RCR1             0x20    /* Receive Configuration 1 Register     */
  29 #define OFFSET_RCR2             0x24    /* Receive Configuration 2 Register     */
  30 #define OFFSET_RCLKDIV          0x28    /* Receive Serial Clock Divider Register */
  31 #define OFFSET_RFSDIV           0x2c    /* Receive Frame Sync Divider Register */
  32 #define OFFSET_STAT             0x30    /* Status Register                      */
  33
  34 #define SPORT_GET_TCR1(sport)           bfin_read16(((sport)->port.membase + OFFSET_TCR1))
  35 #define SPORT_GET_TCR2(sport)           bfin_read16(((sport)->port.membase + OFFSET_TCR2))
  36 #define SPORT_GET_TCLKDIV(sport)        bfin_read16(((sport)->port.membase + OFFSET_TCLKDIV))
  37 #define SPORT_GET_TFSDIV(sport)         bfin_read16(((sport)->port.membase + OFFSET_TFSDIV))
  38 #define SPORT_GET_TX(sport)             bfin_read16(((sport)->port.membase + OFFSET_TX))
  39 #define SPORT_GET_RX(sport)             bfin_read16(((sport)->port.membase + OFFSET_RX))
  40 #define SPORT_GET_RX32(sport)           bfin_read32(((sport)->port.membase + OFFSET_RX))
  41 #define SPORT_GET_RCR1(sport)           bfin_read16(((sport)->port.membase + OFFSET_RCR1))
  42 #define SPORT_GET_RCR2(sport)           bfin_read16(((sport)->port.membase + OFFSET_RCR2))
  43 #define SPORT_GET_RCLKDIV(sport)        bfin_read16(((sport)->port.membase + OFFSET_RCLKDIV))
  44 #define SPORT_GET_RFSDIV(sport)         bfin_read16(((sport)->port.membase + OFFSET_RFSDIV))
  45 #define SPORT_GET_STAT(sport)           bfin_read16(((sport)->port.membase + OFFSET_STAT))
  46
  47 #define SPORT_PUT_TCR1(sport, v)        bfin_write16(((sport)->port.membase + OFFSET_TCR1), v)
  48 #define SPORT_PUT_TCR2(sport, v)        bfin_write16(((sport)->port.membase + OFFSET_TCR2), v)
  49 #define SPORT_PUT_TCLKDIV(sport, v)     bfin_write16(((sport)->port.membase + OFFSET_TCLKDIV), v)
  50 #define SPORT_PUT_TFSDIV(sport, v)      bfin_write16(((sport)->port.membase + OFFSET_TFSDIV), v)
  51 #define SPORT_PUT_TX(sport, v)          bfin_write16(((sport)->port.membase + OFFSET_TX), v)
  52 #define SPORT_PUT_RX(sport, v)          bfin_write16(((sport)->port.membase + OFFSET_RX), v)
  53 #define SPORT_PUT_RCR1(sport, v)        bfin_write16(((sport)->port.membase + OFFSET_RCR1), v)
  54 #define SPORT_PUT_RCR2(sport, v)        bfin_write16(((sport)->port.membase + OFFSET_RCR2), v)
  55 #define SPORT_PUT_RCLKDIV(sport, v)     bfin_write16(((sport)->port.membase + OFFSET_RCLKDIV), v)
  56 #define SPORT_PUT_RFSDIV(sport, v)      bfin_write16(((sport)->port.membase + OFFSET_RFSDIV), v)
  57 #define SPORT_PUT_STAT(sport, v)        bfin_write16(((sport)->port.membase + OFFSET_STAT), v)
  58
  59 #define SPORT_TX_FIFO_SIZE      8
  60
  61 #endif /* _BFIN_SPORT_UART_H */