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Linux 2.6.34-rc3
[pohmelfs.git] / drivers / video / omap2 / dss / dsi.c
blob3af207b2bde385989125ad2639b567dc74e01fa2
1 /*
2 * linux/drivers/video/omap2/dss/dsi.c
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #define DSS_SUBSYS_NAME "DSI"
21
22 #include <linux/kernel.h>
23 #include <linux/io.h>
24 #include <linux/clk.h>
25 #include <linux/device.h>
26 #include <linux/err.h>
27 #include <linux/interrupt.h>
28 #include <linux/delay.h>
29 #include <linux/mutex.h>
30 #include <linux/semaphore.h>
31 #include <linux/seq_file.h>
32 #include <linux/platform_device.h>
33 #include <linux/regulator/consumer.h>
34 #include <linux/wait.h>
35 #include <linux/workqueue.h>
36
37 #include <plat/display.h>
38 #include <plat/clock.h>
39
40 #include "dss.h"
41
42 /*#define VERBOSE_IRQ*/
43 #define DSI_CATCH_MISSING_TE
44
45 #define DSI_BASE 0x4804FC00
46
47 struct dsi_reg { u16 idx; };
48
49 #define DSI_REG(idx) ((const struct dsi_reg) { idx })
50
51 #define DSI_SZ_REGS SZ_1K
52 /* DSI Protocol Engine */
53
54 #define DSI_REVISION DSI_REG(0x0000)
55 #define DSI_SYSCONFIG DSI_REG(0x0010)
56 #define DSI_SYSSTATUS DSI_REG(0x0014)
57 #define DSI_IRQSTATUS DSI_REG(0x0018)
58 #define DSI_IRQENABLE DSI_REG(0x001C)
59 #define DSI_CTRL DSI_REG(0x0040)
60 #define DSI_COMPLEXIO_CFG1 DSI_REG(0x0048)
61 #define DSI_COMPLEXIO_IRQ_STATUS DSI_REG(0x004C)
62 #define DSI_COMPLEXIO_IRQ_ENABLE DSI_REG(0x0050)
63 #define DSI_CLK_CTRL DSI_REG(0x0054)
64 #define DSI_TIMING1 DSI_REG(0x0058)
65 #define DSI_TIMING2 DSI_REG(0x005C)
66 #define DSI_VM_TIMING1 DSI_REG(0x0060)
67 #define DSI_VM_TIMING2 DSI_REG(0x0064)
68 #define DSI_VM_TIMING3 DSI_REG(0x0068)
69 #define DSI_CLK_TIMING DSI_REG(0x006C)
70 #define DSI_TX_FIFO_VC_SIZE DSI_REG(0x0070)
71 #define DSI_RX_FIFO_VC_SIZE DSI_REG(0x0074)
72 #define DSI_COMPLEXIO_CFG2 DSI_REG(0x0078)
73 #define DSI_RX_FIFO_VC_FULLNESS DSI_REG(0x007C)
74 #define DSI_VM_TIMING4 DSI_REG(0x0080)
75 #define DSI_TX_FIFO_VC_EMPTINESS DSI_REG(0x0084)
76 #define DSI_VM_TIMING5 DSI_REG(0x0088)
77 #define DSI_VM_TIMING6 DSI_REG(0x008C)
78 #define DSI_VM_TIMING7 DSI_REG(0x0090)
79 #define DSI_STOPCLK_TIMING DSI_REG(0x0094)
80 #define DSI_VC_CTRL(n) DSI_REG(0x0100 + (n * 0x20))
81 #define DSI_VC_TE(n) DSI_REG(0x0104 + (n * 0x20))
82 #define DSI_VC_LONG_PACKET_HEADER(n) DSI_REG(0x0108 + (n * 0x20))
83 #define DSI_VC_LONG_PACKET_PAYLOAD(n) DSI_REG(0x010C + (n * 0x20))
84 #define DSI_VC_SHORT_PACKET_HEADER(n) DSI_REG(0x0110 + (n * 0x20))
85 #define DSI_VC_IRQSTATUS(n) DSI_REG(0x0118 + (n * 0x20))
86 #define DSI_VC_IRQENABLE(n) DSI_REG(0x011C + (n * 0x20))
87
88 /* DSIPHY_SCP */
89
90 #define DSI_DSIPHY_CFG0 DSI_REG(0x200 + 0x0000)
91 #define DSI_DSIPHY_CFG1 DSI_REG(0x200 + 0x0004)
92 #define DSI_DSIPHY_CFG2 DSI_REG(0x200 + 0x0008)
93 #define DSI_DSIPHY_CFG5 DSI_REG(0x200 + 0x0014)
94
95 /* DSI_PLL_CTRL_SCP */
96
97 #define DSI_PLL_CONTROL DSI_REG(0x300 + 0x0000)
98 #define DSI_PLL_STATUS DSI_REG(0x300 + 0x0004)
99 #define DSI_PLL_GO DSI_REG(0x300 + 0x0008)
100 #define DSI_PLL_CONFIGURATION1 DSI_REG(0x300 + 0x000C)
101 #define DSI_PLL_CONFIGURATION2 DSI_REG(0x300 + 0x0010)
102
103 #define REG_GET(idx, start, end) \
104 FLD_GET(dsi_read_reg(idx), start, end)
105
106 #define REG_FLD_MOD(idx, val, start, end) \
107 dsi_write_reg(idx, FLD_MOD(dsi_read_reg(idx), val, start, end))
108
109 /* Global interrupts */
110 #define DSI_IRQ_VC0 (1 << 0)
111 #define DSI_IRQ_VC1 (1 << 1)
112 #define DSI_IRQ_VC2 (1 << 2)
113 #define DSI_IRQ_VC3 (1 << 3)
114 #define DSI_IRQ_WAKEUP (1 << 4)
115 #define DSI_IRQ_RESYNC (1 << 5)
116 #define DSI_IRQ_PLL_LOCK (1 << 7)
117 #define DSI_IRQ_PLL_UNLOCK (1 << 8)
118 #define DSI_IRQ_PLL_RECALL (1 << 9)
119 #define DSI_IRQ_COMPLEXIO_ERR (1 << 10)
120 #define DSI_IRQ_HS_TX_TIMEOUT (1 << 14)
121 #define DSI_IRQ_LP_RX_TIMEOUT (1 << 15)
122 #define DSI_IRQ_TE_TRIGGER (1 << 16)
123 #define DSI_IRQ_ACK_TRIGGER (1 << 17)
124 #define DSI_IRQ_SYNC_LOST (1 << 18)
125 #define DSI_IRQ_LDO_POWER_GOOD (1 << 19)
126 #define DSI_IRQ_TA_TIMEOUT (1 << 20)
127 #define DSI_IRQ_ERROR_MASK \
128 (DSI_IRQ_HS_TX_TIMEOUT | DSI_IRQ_LP_RX_TIMEOUT | DSI_IRQ_SYNC_LOST | \
129 DSI_IRQ_TA_TIMEOUT)
130 #define DSI_IRQ_CHANNEL_MASK 0xf
131
132 /* Virtual channel interrupts */
133 #define DSI_VC_IRQ_CS (1 << 0)
134 #define DSI_VC_IRQ_ECC_CORR (1 << 1)
135 #define DSI_VC_IRQ_PACKET_SENT (1 << 2)
136 #define DSI_VC_IRQ_FIFO_TX_OVF (1 << 3)
137 #define DSI_VC_IRQ_FIFO_RX_OVF (1 << 4)
138 #define DSI_VC_IRQ_BTA (1 << 5)
139 #define DSI_VC_IRQ_ECC_NO_CORR (1 << 6)
140 #define DSI_VC_IRQ_FIFO_TX_UDF (1 << 7)
141 #define DSI_VC_IRQ_PP_BUSY_CHANGE (1 << 8)
142 #define DSI_VC_IRQ_ERROR_MASK \
143 (DSI_VC_IRQ_CS | DSI_VC_IRQ_ECC_CORR | DSI_VC_IRQ_FIFO_TX_OVF | \
144 DSI_VC_IRQ_FIFO_RX_OVF | DSI_VC_IRQ_ECC_NO_CORR | \
145 DSI_VC_IRQ_FIFO_TX_UDF)
146
147 /* ComplexIO interrupts */
148 #define DSI_CIO_IRQ_ERRSYNCESC1 (1 << 0)
149 #define DSI_CIO_IRQ_ERRSYNCESC2 (1 << 1)
150 #define DSI_CIO_IRQ_ERRSYNCESC3 (1 << 2)
151 #define DSI_CIO_IRQ_ERRESC1 (1 << 5)
152 #define DSI_CIO_IRQ_ERRESC2 (1 << 6)
153 #define DSI_CIO_IRQ_ERRESC3 (1 << 7)
154 #define DSI_CIO_IRQ_ERRCONTROL1 (1 << 10)
155 #define DSI_CIO_IRQ_ERRCONTROL2 (1 << 11)
156 #define DSI_CIO_IRQ_ERRCONTROL3 (1 << 12)
157 #define DSI_CIO_IRQ_STATEULPS1 (1 << 15)
158 #define DSI_CIO_IRQ_STATEULPS2 (1 << 16)
159 #define DSI_CIO_IRQ_STATEULPS3 (1 << 17)
160 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_1 (1 << 20)
161 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_1 (1 << 21)
162 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_2 (1 << 22)
163 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_2 (1 << 23)
164 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_3 (1 << 24)
165 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_3 (1 << 25)
166 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL0 (1 << 30)
167 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL1 (1 << 31)
168
169 #define DSI_DT_DCS_SHORT_WRITE_0 0x05
170 #define DSI_DT_DCS_SHORT_WRITE_1 0x15
171 #define DSI_DT_DCS_READ 0x06
172 #define DSI_DT_SET_MAX_RET_PKG_SIZE 0x37
173 #define DSI_DT_NULL_PACKET 0x09
174 #define DSI_DT_DCS_LONG_WRITE 0x39
175
176 #define DSI_DT_RX_ACK_WITH_ERR 0x02
177 #define DSI_DT_RX_DCS_LONG_READ 0x1c
178 #define DSI_DT_RX_SHORT_READ_1 0x21
179 #define DSI_DT_RX_SHORT_READ_2 0x22
180
181 #define FINT_MAX 2100000
182 #define FINT_MIN 750000
183 #define REGN_MAX (1 << 7)
184 #define REGM_MAX ((1 << 11) - 1)
185 #define REGM3_MAX (1 << 4)
186 #define REGM4_MAX (1 << 4)
187 #define LP_DIV_MAX ((1 << 13) - 1)
188
189 enum fifo_size {
190 DSI_FIFO_SIZE_0 = 0,
191 DSI_FIFO_SIZE_32 = 1,
192 DSI_FIFO_SIZE_64 = 2,
193 DSI_FIFO_SIZE_96 = 3,
194 DSI_FIFO_SIZE_128 = 4,
195 };
196
197 enum dsi_vc_mode {
198 DSI_VC_MODE_L4 = 0,
199 DSI_VC_MODE_VP,
200 };
201
202 struct dsi_update_region {
203 u16 x, y, w, h;
204 struct omap_dss_device *device;
205 };
206
207 struct dsi_irq_stats {
208 unsigned long last_reset;
209 unsigned irq_count;
210 unsigned dsi_irqs[32];
211 unsigned vc_irqs[4][32];
212 unsigned cio_irqs[32];
213 };
214
215 static struct
216 {
217 void __iomem *base;
218
219 struct dsi_clock_info current_cinfo;
220
221 struct regulator *vdds_dsi_reg;
222
223 struct {
224 enum dsi_vc_mode mode;
225 struct omap_dss_device *dssdev;
226 enum fifo_size fifo_size;
227 } vc[4];
228
229 struct mutex lock;
230 struct semaphore bus_lock;
231
232 unsigned pll_locked;
233
234 struct completion bta_completion;
235
236 int update_channel;
237 struct dsi_update_region update_region;
238
239 bool te_enabled;
240
241 struct work_struct framedone_work;
242 void (*framedone_callback)(int, void *);
243 void *framedone_data;
244
245 struct delayed_work framedone_timeout_work;
246
247 #ifdef DSI_CATCH_MISSING_TE
248 struct timer_list te_timer;
249 #endif
250
251 unsigned long cache_req_pck;
252 unsigned long cache_clk_freq;
253 struct dsi_clock_info cache_cinfo;
254
255 u32 errors;
256 spinlock_t errors_lock;
257 #ifdef DEBUG
258 ktime_t perf_setup_time;
259 ktime_t perf_start_time;
260 #endif
261 int debug_read;
262 int debug_write;
263
264 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
265 spinlock_t irq_stats_lock;
266 struct dsi_irq_stats irq_stats;
267 #endif
268 } dsi;
269
270 #ifdef DEBUG
271 static unsigned int dsi_perf;
272 module_param_named(dsi_perf, dsi_perf, bool, 0644);
273 #endif
274
275 static inline void dsi_write_reg(const struct dsi_reg idx, u32 val)
276 {
277 __raw_writel(val, dsi.base + idx.idx);
278 }
279
280 static inline u32 dsi_read_reg(const struct dsi_reg idx)
281 {
282 return __raw_readl(dsi.base + idx.idx);
283 }
284
285
286 void dsi_save_context(void)
287 {
288 }
289
290 void dsi_restore_context(void)
291 {
292 }
293
294 void dsi_bus_lock(void)
295 {
296 down(&dsi.bus_lock);
297 }
298 EXPORT_SYMBOL(dsi_bus_lock);
299
300 void dsi_bus_unlock(void)
301 {
302 up(&dsi.bus_lock);
303 }
304 EXPORT_SYMBOL(dsi_bus_unlock);
305
306 static bool dsi_bus_is_locked(void)
307 {
308 return dsi.bus_lock.count == 0;
309 }
310
311 static inline int wait_for_bit_change(const struct dsi_reg idx, int bitnum,
312 int value)
313 {
314 int t = 100000;
315
316 while (REG_GET(idx, bitnum, bitnum) != value) {
317 if (--t == 0)
318 return !value;
319 }
320
321 return value;
322 }
323
324 #ifdef DEBUG
325 static void dsi_perf_mark_setup(void)
326 {
327 dsi.perf_setup_time = ktime_get();
328 }
329
330 static void dsi_perf_mark_start(void)
331 {
332 dsi.perf_start_time = ktime_get();
333 }
334
335 static void dsi_perf_show(const char *name)
336 {
337 ktime_t t, setup_time, trans_time;
338 u32 total_bytes;
339 u32 setup_us, trans_us, total_us;
340
341 if (!dsi_perf)
342 return;
343
344 t = ktime_get();
345
346 setup_time = ktime_sub(dsi.perf_start_time, dsi.perf_setup_time);
347 setup_us = (u32)ktime_to_us(setup_time);
348 if (setup_us == 0)
349 setup_us = 1;
350
351 trans_time = ktime_sub(t, dsi.perf_start_time);
352 trans_us = (u32)ktime_to_us(trans_time);
353 if (trans_us == 0)
354 trans_us = 1;
355
356 total_us = setup_us + trans_us;
357
358 total_bytes = dsi.update_region.w *
359 dsi.update_region.h *
360 dsi.update_region.device->ctrl.pixel_size / 8;
361
362 printk(KERN_INFO "DSI(%s): %u us + %u us = %u us (%uHz), "
363 "%u bytes, %u kbytes/sec\n",
364 name,
365 setup_us,
366 trans_us,
367 total_us,
368 1000*1000 / total_us,
369 total_bytes,
370 total_bytes * 1000 / total_us);
371 }
372 #else
373 #define dsi_perf_mark_setup()
374 #define dsi_perf_mark_start()
375 #define dsi_perf_show(x)
376 #endif
377
378 static void print_irq_status(u32 status)
379 {
380 #ifndef VERBOSE_IRQ
381 if ((status & ~DSI_IRQ_CHANNEL_MASK) == 0)
382 return;
383 #endif
384 printk(KERN_DEBUG "DSI IRQ: 0x%x: ", status);
385
386 #define PIS(x) \
387 if (status & DSI_IRQ_##x) \
388 printk(#x " ");
389 #ifdef VERBOSE_IRQ
390 PIS(VC0);
391 PIS(VC1);
392 PIS(VC2);
393 PIS(VC3);
394 #endif
395 PIS(WAKEUP);
396 PIS(RESYNC);
397 PIS(PLL_LOCK);
398 PIS(PLL_UNLOCK);
399 PIS(PLL_RECALL);
400 PIS(COMPLEXIO_ERR);
401 PIS(HS_TX_TIMEOUT);
402 PIS(LP_RX_TIMEOUT);
403 PIS(TE_TRIGGER);
404 PIS(ACK_TRIGGER);
405 PIS(SYNC_LOST);
406 PIS(LDO_POWER_GOOD);
407 PIS(TA_TIMEOUT);
408 #undef PIS
409
410 printk("\n");
411 }
412
413 static void print_irq_status_vc(int channel, u32 status)
414 {
415 #ifndef VERBOSE_IRQ
416 if ((status & ~DSI_VC_IRQ_PACKET_SENT) == 0)
417 return;
418 #endif
419 printk(KERN_DEBUG "DSI VC(%d) IRQ 0x%x: ", channel, status);
420
421 #define PIS(x) \
422 if (status & DSI_VC_IRQ_##x) \
423 printk(#x " ");
424 PIS(CS);
425 PIS(ECC_CORR);
426 #ifdef VERBOSE_IRQ
427 PIS(PACKET_SENT);
428 #endif
429 PIS(FIFO_TX_OVF);
430 PIS(FIFO_RX_OVF);
431 PIS(BTA);
432 PIS(ECC_NO_CORR);
433 PIS(FIFO_TX_UDF);
434 PIS(PP_BUSY_CHANGE);
435 #undef PIS
436 printk("\n");
437 }
438
439 static void print_irq_status_cio(u32 status)
440 {
441 printk(KERN_DEBUG "DSI CIO IRQ 0x%x: ", status);
442
443 #define PIS(x) \
444 if (status & DSI_CIO_IRQ_##x) \
445 printk(#x " ");
446 PIS(ERRSYNCESC1);
447 PIS(ERRSYNCESC2);
448 PIS(ERRSYNCESC3);
449 PIS(ERRESC1);
450 PIS(ERRESC2);
451 PIS(ERRESC3);
452 PIS(ERRCONTROL1);
453 PIS(ERRCONTROL2);
454 PIS(ERRCONTROL3);
455 PIS(STATEULPS1);
456 PIS(STATEULPS2);
457 PIS(STATEULPS3);
458 PIS(ERRCONTENTIONLP0_1);
459 PIS(ERRCONTENTIONLP1_1);
460 PIS(ERRCONTENTIONLP0_2);
461 PIS(ERRCONTENTIONLP1_2);
462 PIS(ERRCONTENTIONLP0_3);
463 PIS(ERRCONTENTIONLP1_3);
464 PIS(ULPSACTIVENOT_ALL0);
465 PIS(ULPSACTIVENOT_ALL1);
466 #undef PIS
467
468 printk("\n");
469 }
470
471 static int debug_irq;
472
473 /* called from dss */
474 void dsi_irq_handler(void)
475 {
476 u32 irqstatus, vcstatus, ciostatus;
477 int i;
478
479 irqstatus = dsi_read_reg(DSI_IRQSTATUS);
480
481 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
482 spin_lock(&dsi.irq_stats_lock);
483 dsi.irq_stats.irq_count++;
484 dss_collect_irq_stats(irqstatus, dsi.irq_stats.dsi_irqs);
485 #endif
486
487 if (irqstatus & DSI_IRQ_ERROR_MASK) {
488 DSSERR("DSI error, irqstatus %x\n", irqstatus);
489 print_irq_status(irqstatus);
490 spin_lock(&dsi.errors_lock);
491 dsi.errors |= irqstatus & DSI_IRQ_ERROR_MASK;
492 spin_unlock(&dsi.errors_lock);
493 } else if (debug_irq) {
494 print_irq_status(irqstatus);
495 }
496
497 #ifdef DSI_CATCH_MISSING_TE
498 if (irqstatus & DSI_IRQ_TE_TRIGGER)
499 del_timer(&dsi.te_timer);
500 #endif
501
502 for (i = 0; i < 4; ++i) {
503 if ((irqstatus & (1<<i)) == 0)
504 continue;
505
506 vcstatus = dsi_read_reg(DSI_VC_IRQSTATUS(i));
507
508 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
509 dss_collect_irq_stats(vcstatus, dsi.irq_stats.vc_irqs[i]);
510 #endif
511
512 if (vcstatus & DSI_VC_IRQ_BTA)
513 complete(&dsi.bta_completion);
514
515 if (vcstatus & DSI_VC_IRQ_ERROR_MASK) {
516 DSSERR("DSI VC(%d) error, vc irqstatus %x\n",
517 i, vcstatus);
518 print_irq_status_vc(i, vcstatus);
519 } else if (debug_irq) {
520 print_irq_status_vc(i, vcstatus);
521 }
522
523 dsi_write_reg(DSI_VC_IRQSTATUS(i), vcstatus);
524 /* flush posted write */
525 dsi_read_reg(DSI_VC_IRQSTATUS(i));
526 }
527
528 if (irqstatus & DSI_IRQ_COMPLEXIO_ERR) {
529 ciostatus = dsi_read_reg(DSI_COMPLEXIO_IRQ_STATUS);
530
531 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
532 dss_collect_irq_stats(ciostatus, dsi.irq_stats.cio_irqs);
533 #endif
534
535 dsi_write_reg(DSI_COMPLEXIO_IRQ_STATUS, ciostatus);
536 /* flush posted write */
537 dsi_read_reg(DSI_COMPLEXIO_IRQ_STATUS);
538
539 DSSERR("DSI CIO error, cio irqstatus %x\n", ciostatus);
540 print_irq_status_cio(ciostatus);
541 }
542
543 dsi_write_reg(DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK);
544 /* flush posted write */
545 dsi_read_reg(DSI_IRQSTATUS);
546
547 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
548 spin_unlock(&dsi.irq_stats_lock);
549 #endif
550 }
551
552
553 static void _dsi_initialize_irq(void)
554 {
555 u32 l;
556 int i;
557
558 /* disable all interrupts */
559 dsi_write_reg(DSI_IRQENABLE, 0);
560 for (i = 0; i < 4; ++i)
561 dsi_write_reg(DSI_VC_IRQENABLE(i), 0);
562 dsi_write_reg(DSI_COMPLEXIO_IRQ_ENABLE, 0);
563
564 /* clear interrupt status */
565 l = dsi_read_reg(DSI_IRQSTATUS);
566 dsi_write_reg(DSI_IRQSTATUS, l & ~DSI_IRQ_CHANNEL_MASK);
567
568 for (i = 0; i < 4; ++i) {
569 l = dsi_read_reg(DSI_VC_IRQSTATUS(i));
570 dsi_write_reg(DSI_VC_IRQSTATUS(i), l);
571 }
572
573 l = dsi_read_reg(DSI_COMPLEXIO_IRQ_STATUS);
574 dsi_write_reg(DSI_COMPLEXIO_IRQ_STATUS, l);
575
576 /* enable error irqs */
577 l = DSI_IRQ_ERROR_MASK;
578 #ifdef DSI_CATCH_MISSING_TE
579 l |= DSI_IRQ_TE_TRIGGER;
580 #endif
581 dsi_write_reg(DSI_IRQENABLE, l);
582
583 l = DSI_VC_IRQ_ERROR_MASK;
584 for (i = 0; i < 4; ++i)
585 dsi_write_reg(DSI_VC_IRQENABLE(i), l);
586
587 /* XXX zonda responds incorrectly, causing control error:
588 Exit from LP-ESC mode to LP11 uses wrong transition states on the
589 data lines LP0 and LN0. */
590 dsi_write_reg(DSI_COMPLEXIO_IRQ_ENABLE,
591 -1 & (~DSI_CIO_IRQ_ERRCONTROL2));
592 }
593
594 static u32 dsi_get_errors(void)
595 {
596 unsigned long flags;
597 u32 e;
598 spin_lock_irqsave(&dsi.errors_lock, flags);
599 e = dsi.errors;
600 dsi.errors = 0;
601 spin_unlock_irqrestore(&dsi.errors_lock, flags);
602 return e;
603 }
604
605 static void dsi_vc_enable_bta_irq(int channel)
606 {
607 u32 l;
608
609 dsi_write_reg(DSI_VC_IRQSTATUS(channel), DSI_VC_IRQ_BTA);
610
611 l = dsi_read_reg(DSI_VC_IRQENABLE(channel));
612 l |= DSI_VC_IRQ_BTA;
613 dsi_write_reg(DSI_VC_IRQENABLE(channel), l);
614 }
615
616 static void dsi_vc_disable_bta_irq(int channel)
617 {
618 u32 l;
619
620 l = dsi_read_reg(DSI_VC_IRQENABLE(channel));
621 l &= ~DSI_VC_IRQ_BTA;
622 dsi_write_reg(DSI_VC_IRQENABLE(channel), l);
623 }
624
625 /* DSI func clock. this could also be DSI2_PLL_FCLK */
626 static inline void enable_clocks(bool enable)
627 {
628 if (enable)
629 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
630 else
631 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
632 }
633
634 /* source clock for DSI PLL. this could also be PCLKFREE */
635 static inline void dsi_enable_pll_clock(bool enable)
636 {
637 if (enable)
638 dss_clk_enable(DSS_CLK_FCK2);
639 else
640 dss_clk_disable(DSS_CLK_FCK2);
641
642 if (enable && dsi.pll_locked) {
643 if (wait_for_bit_change(DSI_PLL_STATUS, 1, 1) != 1)
644 DSSERR("cannot lock PLL when enabling clocks\n");
645 }
646 }
647
648 #ifdef DEBUG
649 static void _dsi_print_reset_status(void)
650 {
651 u32 l;
652
653 if (!dss_debug)
654 return;
655
656 /* A dummy read using the SCP interface to any DSIPHY register is
657 * required after DSIPHY reset to complete the reset of the DSI complex
658 * I/O. */
659 l = dsi_read_reg(DSI_DSIPHY_CFG5);
660
661 printk(KERN_DEBUG "DSI resets: ");
662
663 l = dsi_read_reg(DSI_PLL_STATUS);
664 printk("PLL (%d) ", FLD_GET(l, 0, 0));
665
666 l = dsi_read_reg(DSI_COMPLEXIO_CFG1);
667 printk("CIO (%d) ", FLD_GET(l, 29, 29));
668
669 l = dsi_read_reg(DSI_DSIPHY_CFG5);
670 printk("PHY (%x, %d, %d, %d)\n",
671 FLD_GET(l, 28, 26),
672 FLD_GET(l, 29, 29),
673 FLD_GET(l, 30, 30),
674 FLD_GET(l, 31, 31));
675 }
676 #else
677 #define _dsi_print_reset_status()
678 #endif
679
680 static inline int dsi_if_enable(bool enable)
681 {
682 DSSDBG("dsi_if_enable(%d)\n", enable);
683
684 enable = enable ? 1 : 0;
685 REG_FLD_MOD(DSI_CTRL, enable, 0, 0); /* IF_EN */
686
687 if (wait_for_bit_change(DSI_CTRL, 0, enable) != enable) {
688 DSSERR("Failed to set dsi_if_enable to %d\n", enable);
689 return -EIO;
690 }
691
692 return 0;
693 }
694
695 unsigned long dsi_get_dsi1_pll_rate(void)
696 {
697 return dsi.current_cinfo.dsi1_pll_fclk;
698 }
699
700 static unsigned long dsi_get_dsi2_pll_rate(void)
701 {
702 return dsi.current_cinfo.dsi2_pll_fclk;
703 }
704
705 static unsigned long dsi_get_txbyteclkhs(void)
706 {
707 return dsi.current_cinfo.clkin4ddr / 16;
708 }
709
710 static unsigned long dsi_fclk_rate(void)
711 {
712 unsigned long r;
713
714 if (dss_get_dsi_clk_source() == DSS_SRC_DSS1_ALWON_FCLK) {
715 /* DSI FCLK source is DSS1_ALWON_FCK, which is dss1_fck */
716 r = dss_clk_get_rate(DSS_CLK_FCK1);
717 } else {
718 /* DSI FCLK source is DSI2_PLL_FCLK */
719 r = dsi_get_dsi2_pll_rate();
720 }
721
722 return r;
723 }
724
725 static int dsi_set_lp_clk_divisor(struct omap_dss_device *dssdev)
726 {
727 unsigned long dsi_fclk;
728 unsigned lp_clk_div;
729 unsigned long lp_clk;
730
731 lp_clk_div = dssdev->phy.dsi.div.lp_clk_div;
732
733 if (lp_clk_div == 0 || lp_clk_div > LP_DIV_MAX)
734 return -EINVAL;
735
736 dsi_fclk = dsi_fclk_rate();
737
738 lp_clk = dsi_fclk / 2 / lp_clk_div;
739
740 DSSDBG("LP_CLK_DIV %u, LP_CLK %lu\n", lp_clk_div, lp_clk);
741 dsi.current_cinfo.lp_clk = lp_clk;
742 dsi.current_cinfo.lp_clk_div = lp_clk_div;
743
744 REG_FLD_MOD(DSI_CLK_CTRL, lp_clk_div, 12, 0); /* LP_CLK_DIVISOR */
745
746 REG_FLD_MOD(DSI_CLK_CTRL, dsi_fclk > 30000000 ? 1 : 0,
747 21, 21); /* LP_RX_SYNCHRO_ENABLE */
748
749 return 0;
750 }
751
752
753 enum dsi_pll_power_state {
754 DSI_PLL_POWER_OFF = 0x0,
755 DSI_PLL_POWER_ON_HSCLK = 0x1,
756 DSI_PLL_POWER_ON_ALL = 0x2,
757 DSI_PLL_POWER_ON_DIV = 0x3,
758 };
759
760 static int dsi_pll_power(enum dsi_pll_power_state state)
761 {
762 int t = 0;
763
764 REG_FLD_MOD(DSI_CLK_CTRL, state, 31, 30); /* PLL_PWR_CMD */
765
766 /* PLL_PWR_STATUS */
767 while (FLD_GET(dsi_read_reg(DSI_CLK_CTRL), 29, 28) != state) {
768 if (++t > 1000) {
769 DSSERR("Failed to set DSI PLL power mode to %d\n",
770 state);
771 return -ENODEV;
772 }
773 udelay(1);
774 }
775
776 return 0;
777 }
778
779 /* calculate clock rates using dividers in cinfo */
780 static int dsi_calc_clock_rates(struct dsi_clock_info *cinfo)
781 {
782 if (cinfo->regn == 0 || cinfo->regn > REGN_MAX)
783 return -EINVAL;
784
785 if (cinfo->regm == 0 || cinfo->regm > REGM_MAX)
786 return -EINVAL;
787
788 if (cinfo->regm3 > REGM3_MAX)
789 return -EINVAL;
790
791 if (cinfo->regm4 > REGM4_MAX)
792 return -EINVAL;
793
794 if (cinfo->use_dss2_fck) {
795 cinfo->clkin = dss_clk_get_rate(DSS_CLK_FCK2);
796 /* XXX it is unclear if highfreq should be used
797 * with DSS2_FCK source also */
798 cinfo->highfreq = 0;
799 } else {
800 cinfo->clkin = dispc_pclk_rate();
801
802 if (cinfo->clkin < 32000000)
803 cinfo->highfreq = 0;
804 else
805 cinfo->highfreq = 1;
806 }
807
808 cinfo->fint = cinfo->clkin / (cinfo->regn * (cinfo->highfreq ? 2 : 1));
809
810 if (cinfo->fint > FINT_MAX || cinfo->fint < FINT_MIN)
811 return -EINVAL;
812
813 cinfo->clkin4ddr = 2 * cinfo->regm * cinfo->fint;
814
815 if (cinfo->clkin4ddr > 1800 * 1000 * 1000)
816 return -EINVAL;
817
818 if (cinfo->regm3 > 0)
819 cinfo->dsi1_pll_fclk = cinfo->clkin4ddr / cinfo->regm3;
820 else
821 cinfo->dsi1_pll_fclk = 0;
822
823 if (cinfo->regm4 > 0)
824 cinfo->dsi2_pll_fclk = cinfo->clkin4ddr / cinfo->regm4;
825 else
826 cinfo->dsi2_pll_fclk = 0;
827
828 return 0;
829 }
830
831 int dsi_pll_calc_clock_div_pck(bool is_tft, unsigned long req_pck,
832 struct dsi_clock_info *dsi_cinfo,
833 struct dispc_clock_info *dispc_cinfo)
834 {
835 struct dsi_clock_info cur, best;
836 struct dispc_clock_info best_dispc;
837 int min_fck_per_pck;
838 int match = 0;
839 unsigned long dss_clk_fck2;
840
841 dss_clk_fck2 = dss_clk_get_rate(DSS_CLK_FCK2);
842
843 if (req_pck == dsi.cache_req_pck &&
844 dsi.cache_cinfo.clkin == dss_clk_fck2) {
845 DSSDBG("DSI clock info found from cache\n");
846 *dsi_cinfo = dsi.cache_cinfo;
847 dispc_find_clk_divs(is_tft, req_pck, dsi_cinfo->dsi1_pll_fclk,
848 dispc_cinfo);
849 return 0;
850 }
851
852 min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
853
854 if (min_fck_per_pck &&
855 req_pck * min_fck_per_pck > DISPC_MAX_FCK) {
856 DSSERR("Requested pixel clock not possible with the current "
857 "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "
858 "the constraint off.\n");
859 min_fck_per_pck = 0;
860 }
861
862 DSSDBG("dsi_pll_calc\n");
863
864 retry:
865 memset(&best, 0, sizeof(best));
866 memset(&best_dispc, 0, sizeof(best_dispc));
867
868 memset(&cur, 0, sizeof(cur));
869 cur.clkin = dss_clk_fck2;
870 cur.use_dss2_fck = 1;
871 cur.highfreq = 0;
872
873 /* no highfreq: 0.75MHz < Fint = clkin / regn < 2.1MHz */
874 /* highfreq: 0.75MHz < Fint = clkin / (2*regn) < 2.1MHz */
875 /* To reduce PLL lock time, keep Fint high (around 2 MHz) */
876 for (cur.regn = 1; cur.regn < REGN_MAX; ++cur.regn) {
877 if (cur.highfreq == 0)
878 cur.fint = cur.clkin / cur.regn;
879 else
880 cur.fint = cur.clkin / (2 * cur.regn);
881
882 if (cur.fint > FINT_MAX || cur.fint < FINT_MIN)
883 continue;
884
885 /* DSIPHY(MHz) = (2 * regm / regn) * (clkin / (highfreq + 1)) */
886 for (cur.regm = 1; cur.regm < REGM_MAX; ++cur.regm) {
887 unsigned long a, b;
888
889 a = 2 * cur.regm * (cur.clkin/1000);
890 b = cur.regn * (cur.highfreq + 1);
891 cur.clkin4ddr = a / b * 1000;
892
893 if (cur.clkin4ddr > 1800 * 1000 * 1000)
894 break;
895
896 /* DSI1_PLL_FCLK(MHz) = DSIPHY(MHz) / regm3 < 173MHz */
897 for (cur.regm3 = 1; cur.regm3 < REGM3_MAX;
898 ++cur.regm3) {
899 struct dispc_clock_info cur_dispc;
900 cur.dsi1_pll_fclk = cur.clkin4ddr / cur.regm3;
901
902 /* this will narrow down the search a bit,
903 * but still give pixclocks below what was
904 * requested */
905 if (cur.dsi1_pll_fclk < req_pck)
906 break;
907
908 if (cur.dsi1_pll_fclk > DISPC_MAX_FCK)
909 continue;
910
911 if (min_fck_per_pck &&
912 cur.dsi1_pll_fclk <
913 req_pck * min_fck_per_pck)
914 continue;
915
916 match = 1;
917
918 dispc_find_clk_divs(is_tft, req_pck,
919 cur.dsi1_pll_fclk,
920 &cur_dispc);
921
922 if (abs(cur_dispc.pck - req_pck) <
923 abs(best_dispc.pck - req_pck)) {
924 best = cur;
925 best_dispc = cur_dispc;
926
927 if (cur_dispc.pck == req_pck)
928 goto found;
929 }
930 }
931 }
932 }
933 found:
934 if (!match) {
935 if (min_fck_per_pck) {
936 DSSERR("Could not find suitable clock settings.\n"
937 "Turning FCK/PCK constraint off and"
938 "trying again.\n");
939 min_fck_per_pck = 0;
940 goto retry;
941 }
942
943 DSSERR("Could not find suitable clock settings.\n");
944
945 return -EINVAL;
946 }
947
948 /* DSI2_PLL_FCLK (regm4) is not used */
949 best.regm4 = 0;
950 best.dsi2_pll_fclk = 0;
951
952 if (dsi_cinfo)
953 *dsi_cinfo = best;
954 if (dispc_cinfo)
955 *dispc_cinfo = best_dispc;
956
957 dsi.cache_req_pck = req_pck;
958 dsi.cache_clk_freq = 0;
959 dsi.cache_cinfo = best;
960
961 return 0;
962 }
963
964 int dsi_pll_set_clock_div(struct dsi_clock_info *cinfo)
965 {
966 int r = 0;
967 u32 l;
968 int f;
969
970 DSSDBGF();
971
972 dsi.current_cinfo.fint = cinfo->fint;
973 dsi.current_cinfo.clkin4ddr = cinfo->clkin4ddr;
974 dsi.current_cinfo.dsi1_pll_fclk = cinfo->dsi1_pll_fclk;
975 dsi.current_cinfo.dsi2_pll_fclk = cinfo->dsi2_pll_fclk;
976
977 dsi.current_cinfo.regn = cinfo->regn;
978 dsi.current_cinfo.regm = cinfo->regm;
979 dsi.current_cinfo.regm3 = cinfo->regm3;
980 dsi.current_cinfo.regm4 = cinfo->regm4;
981
982 DSSDBG("DSI Fint %ld\n", cinfo->fint);
983
984 DSSDBG("clkin (%s) rate %ld, highfreq %d\n",
985 cinfo->use_dss2_fck ? "dss2_fck" : "pclkfree",
986 cinfo->clkin,
987 cinfo->highfreq);
988
989 /* DSIPHY == CLKIN4DDR */
990 DSSDBG("CLKIN4DDR = 2 * %d / %d * %lu / %d = %lu\n",
991 cinfo->regm,
992 cinfo->regn,
993 cinfo->clkin,
994 cinfo->highfreq + 1,
995 cinfo->clkin4ddr);
996
997 DSSDBG("Data rate on 1 DSI lane %ld Mbps\n",
998 cinfo->clkin4ddr / 1000 / 1000 / 2);
999
1000 DSSDBG("Clock lane freq %ld Hz\n", cinfo->clkin4ddr / 4);
1001
1002 DSSDBG("regm3 = %d, dsi1_pll_fclk = %lu\n",
1003 cinfo->regm3, cinfo->dsi1_pll_fclk);
1004 DSSDBG("regm4 = %d, dsi2_pll_fclk = %lu\n",
1005 cinfo->regm4, cinfo->dsi2_pll_fclk);
1006
1007 REG_FLD_MOD(DSI_PLL_CONTROL, 0, 0, 0); /* DSI_PLL_AUTOMODE = manual */
1008
1009 l = dsi_read_reg(DSI_PLL_CONFIGURATION1);
1010 l = FLD_MOD(l, 1, 0, 0); /* DSI_PLL_STOPMODE */
1011 l = FLD_MOD(l, cinfo->regn - 1, 7, 1); /* DSI_PLL_REGN */
1012 l = FLD_MOD(l, cinfo->regm, 18, 8); /* DSI_PLL_REGM */
1013 l = FLD_MOD(l, cinfo->regm3 > 0 ? cinfo->regm3 - 1 : 0,
1014 22, 19); /* DSI_CLOCK_DIV */
1015 l = FLD_MOD(l, cinfo->regm4 > 0 ? cinfo->regm4 - 1 : 0,
1016 26, 23); /* DSIPROTO_CLOCK_DIV */
1017 dsi_write_reg(DSI_PLL_CONFIGURATION1, l);
1018
1019 BUG_ON(cinfo->fint < 750000 || cinfo->fint > 2100000);
1020 if (cinfo->fint < 1000000)
1021 f = 0x3;
1022 else if (cinfo->fint < 1250000)
1023 f = 0x4;
1024 else if (cinfo->fint < 1500000)
1025 f = 0x5;
1026 else if (cinfo->fint < 1750000)
1027 f = 0x6;
1028 else
1029 f = 0x7;
1030
1031 l = dsi_read_reg(DSI_PLL_CONFIGURATION2);
1032 l = FLD_MOD(l, f, 4, 1); /* DSI_PLL_FREQSEL */
1033 l = FLD_MOD(l, cinfo->use_dss2_fck ? 0 : 1,
1034 11, 11); /* DSI_PLL_CLKSEL */
1035 l = FLD_MOD(l, cinfo->highfreq,
1036 12, 12); /* DSI_PLL_HIGHFREQ */
1037 l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */
1038 l = FLD_MOD(l, 0, 14, 14); /* DSIPHY_CLKINEN */
1039 l = FLD_MOD(l, 1, 20, 20); /* DSI_HSDIVBYPASS */
1040 dsi_write_reg(DSI_PLL_CONFIGURATION2, l);
1041
1042 REG_FLD_MOD(DSI_PLL_GO, 1, 0, 0); /* DSI_PLL_GO */
1043
1044 if (wait_for_bit_change(DSI_PLL_GO, 0, 0) != 0) {
1045 DSSERR("dsi pll go bit not going down.\n");
1046 r = -EIO;
1047 goto err;
1048 }
1049
1050 if (wait_for_bit_change(DSI_PLL_STATUS, 1, 1) != 1) {
1051 DSSERR("cannot lock PLL\n");
1052 r = -EIO;
1053 goto err;
1054 }
1055
1056 dsi.pll_locked = 1;
1057
1058 l = dsi_read_reg(DSI_PLL_CONFIGURATION2);
1059 l = FLD_MOD(l, 0, 0, 0); /* DSI_PLL_IDLE */
1060 l = FLD_MOD(l, 0, 5, 5); /* DSI_PLL_PLLLPMODE */
1061 l = FLD_MOD(l, 0, 6, 6); /* DSI_PLL_LOWCURRSTBY */
1062 l = FLD_MOD(l, 0, 7, 7); /* DSI_PLL_TIGHTPHASELOCK */
1063 l = FLD_MOD(l, 0, 8, 8); /* DSI_PLL_DRIFTGUARDEN */
1064 l = FLD_MOD(l, 0, 10, 9); /* DSI_PLL_LOCKSEL */
1065 l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */
1066 l = FLD_MOD(l, 1, 14, 14); /* DSIPHY_CLKINEN */
1067 l = FLD_MOD(l, 0, 15, 15); /* DSI_BYPASSEN */
1068 l = FLD_MOD(l, 1, 16, 16); /* DSS_CLOCK_EN */
1069 l = FLD_MOD(l, 0, 17, 17); /* DSS_CLOCK_PWDN */
1070 l = FLD_MOD(l, 1, 18, 18); /* DSI_PROTO_CLOCK_EN */
1071 l = FLD_MOD(l, 0, 19, 19); /* DSI_PROTO_CLOCK_PWDN */
1072 l = FLD_MOD(l, 0, 20, 20); /* DSI_HSDIVBYPASS */
1073 dsi_write_reg(DSI_PLL_CONFIGURATION2, l);
1074
1075 DSSDBG("PLL config done\n");
1076 err:
1077 return r;
1078 }
1079
1080 int dsi_pll_init(struct omap_dss_device *dssdev, bool enable_hsclk,
1081 bool enable_hsdiv)
1082 {
1083 int r = 0;
1084 enum dsi_pll_power_state pwstate;
1085
1086 DSSDBG("PLL init\n");
1087
1088 enable_clocks(1);
1089 dsi_enable_pll_clock(1);
1090
1091 r = regulator_enable(dsi.vdds_dsi_reg);
1092 if (r)
1093 goto err0;
1094
1095 /* XXX PLL does not come out of reset without this... */
1096 dispc_pck_free_enable(1);
1097
1098 if (wait_for_bit_change(DSI_PLL_STATUS, 0, 1) != 1) {
1099 DSSERR("PLL not coming out of reset.\n");
1100 r = -ENODEV;
1101 goto err1;
1102 }
1103
1104 /* XXX ... but if left on, we get problems when planes do not
1105 * fill the whole display. No idea about this */
1106 dispc_pck_free_enable(0);
1107
1108 if (enable_hsclk && enable_hsdiv)
1109 pwstate = DSI_PLL_POWER_ON_ALL;
1110 else if (enable_hsclk)
1111 pwstate = DSI_PLL_POWER_ON_HSCLK;
1112 else if (enable_hsdiv)
1113 pwstate = DSI_PLL_POWER_ON_DIV;
1114 else
1115 pwstate = DSI_PLL_POWER_OFF;
1116
1117 r = dsi_pll_power(pwstate);
1118
1119 if (r)
1120 goto err1;
1121
1122 DSSDBG("PLL init done\n");
1123
1124 return 0;
1125 err1:
1126 regulator_disable(dsi.vdds_dsi_reg);
1127 err0:
1128 enable_clocks(0);
1129 dsi_enable_pll_clock(0);
1130 return r;
1131 }
1132
1133 void dsi_pll_uninit(void)
1134 {
1135 enable_clocks(0);
1136 dsi_enable_pll_clock(0);
1137
1138 dsi.pll_locked = 0;
1139 dsi_pll_power(DSI_PLL_POWER_OFF);
1140 regulator_disable(dsi.vdds_dsi_reg);
1141 DSSDBG("PLL uninit done\n");
1142 }
1143
1144 void dsi_dump_clocks(struct seq_file *s)
1145 {
1146 int clksel;
1147 struct dsi_clock_info *cinfo = &dsi.current_cinfo;
1148
1149 enable_clocks(1);
1150
1151 clksel = REG_GET(DSI_PLL_CONFIGURATION2, 11, 11);
1152
1153 seq_printf(s, "- DSI PLL -\n");
1154
1155 seq_printf(s, "dsi pll source = %s\n",
1156 clksel == 0 ?
1157 "dss2_alwon_fclk" : "pclkfree");
1158
1159 seq_printf(s, "Fint\t\t%-16luregn %u\n", cinfo->fint, cinfo->regn);
1160
1161 seq_printf(s, "CLKIN4DDR\t%-16luregm %u\n",
1162 cinfo->clkin4ddr, cinfo->regm);
1163
1164 seq_printf(s, "dsi1_pll_fck\t%-16luregm3 %u\t(%s)\n",
1165 cinfo->dsi1_pll_fclk,
1166 cinfo->regm3,
1167 dss_get_dispc_clk_source() == DSS_SRC_DSS1_ALWON_FCLK ?
1168 "off" : "on");
1169
1170 seq_printf(s, "dsi2_pll_fck\t%-16luregm4 %u\t(%s)\n",
1171 cinfo->dsi2_pll_fclk,
1172 cinfo->regm4,
1173 dss_get_dsi_clk_source() == DSS_SRC_DSS1_ALWON_FCLK ?
1174 "off" : "on");
1175
1176 seq_printf(s, "- DSI -\n");
1177
1178 seq_printf(s, "dsi fclk source = %s\n",
1179 dss_get_dsi_clk_source() == DSS_SRC_DSS1_ALWON_FCLK ?
1180 "dss1_alwon_fclk" : "dsi2_pll_fclk");
1181
1182 seq_printf(s, "DSI_FCLK\t%lu\n", dsi_fclk_rate());
1183
1184 seq_printf(s, "DDR_CLK\t\t%lu\n",
1185 cinfo->clkin4ddr / 4);
1186
1187 seq_printf(s, "TxByteClkHS\t%lu\n", dsi_get_txbyteclkhs());
1188
1189 seq_printf(s, "LP_CLK\t\t%lu\n", cinfo->lp_clk);
1190
1191 seq_printf(s, "VP_CLK\t\t%lu\n"
1192 "VP_PCLK\t\t%lu\n",
1193 dispc_lclk_rate(),
1194 dispc_pclk_rate());
1195
1196 enable_clocks(0);
1197 }
1198
1199 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
1200 void dsi_dump_irqs(struct seq_file *s)
1201 {
1202 unsigned long flags;
1203 struct dsi_irq_stats stats;
1204
1205 spin_lock_irqsave(&dsi.irq_stats_lock, flags);
1206
1207 stats = dsi.irq_stats;
1208 memset(&dsi.irq_stats, 0, sizeof(dsi.irq_stats));
1209 dsi.irq_stats.last_reset = jiffies;
1210
1211 spin_unlock_irqrestore(&dsi.irq_stats_lock, flags);
1212
1213 seq_printf(s, "period %u ms\n",
1214 jiffies_to_msecs(jiffies - stats.last_reset));
1215
1216 seq_printf(s, "irqs %d\n", stats.irq_count);
1217 #define PIS(x) \
1218 seq_printf(s, "%-20s %10d\n", #x, stats.dsi_irqs[ffs(DSI_IRQ_##x)-1]);
1219
1220 seq_printf(s, "-- DSI interrupts --\n");
1221 PIS(VC0);
1222 PIS(VC1);
1223 PIS(VC2);
1224 PIS(VC3);
1225 PIS(WAKEUP);
1226 PIS(RESYNC);
1227 PIS(PLL_LOCK);
1228 PIS(PLL_UNLOCK);
1229 PIS(PLL_RECALL);
1230 PIS(COMPLEXIO_ERR);
1231 PIS(HS_TX_TIMEOUT);
1232 PIS(LP_RX_TIMEOUT);
1233 PIS(TE_TRIGGER);
1234 PIS(ACK_TRIGGER);
1235 PIS(SYNC_LOST);
1236 PIS(LDO_POWER_GOOD);
1237 PIS(TA_TIMEOUT);
1238 #undef PIS
1239
1240 #define PIS(x) \
1241 seq_printf(s, "%-20s %10d %10d %10d %10d\n", #x, \
1242 stats.vc_irqs[0][ffs(DSI_VC_IRQ_##x)-1], \
1243 stats.vc_irqs[1][ffs(DSI_VC_IRQ_##x)-1], \
1244 stats.vc_irqs[2][ffs(DSI_VC_IRQ_##x)-1], \
1245 stats.vc_irqs[3][ffs(DSI_VC_IRQ_##x)-1]);
1246
1247 seq_printf(s, "-- VC interrupts --\n");
1248 PIS(CS);
1249 PIS(ECC_CORR);
1250 PIS(PACKET_SENT);
1251 PIS(FIFO_TX_OVF);
1252 PIS(FIFO_RX_OVF);
1253 PIS(BTA);
1254 PIS(ECC_NO_CORR);
1255 PIS(FIFO_TX_UDF);
1256 PIS(PP_BUSY_CHANGE);
1257 #undef PIS
1258
1259 #define PIS(x) \
1260 seq_printf(s, "%-20s %10d\n", #x, \
1261 stats.cio_irqs[ffs(DSI_CIO_IRQ_##x)-1]);
1262
1263 seq_printf(s, "-- CIO interrupts --\n");
1264 PIS(ERRSYNCESC1);
1265 PIS(ERRSYNCESC2);
1266 PIS(ERRSYNCESC3);
1267 PIS(ERRESC1);
1268 PIS(ERRESC2);
1269 PIS(ERRESC3);
1270 PIS(ERRCONTROL1);
1271 PIS(ERRCONTROL2);
1272 PIS(ERRCONTROL3);
1273 PIS(STATEULPS1);
1274 PIS(STATEULPS2);
1275 PIS(STATEULPS3);
1276 PIS(ERRCONTENTIONLP0_1);
1277 PIS(ERRCONTENTIONLP1_1);
1278 PIS(ERRCONTENTIONLP0_2);
1279 PIS(ERRCONTENTIONLP1_2);
1280 PIS(ERRCONTENTIONLP0_3);
1281 PIS(ERRCONTENTIONLP1_3);
1282 PIS(ULPSACTIVENOT_ALL0);
1283 PIS(ULPSACTIVENOT_ALL1);
1284 #undef PIS
1285 }
1286 #endif
1287
1288 void dsi_dump_regs(struct seq_file *s)
1289 {
1290 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(r))
1291
1292 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
1293
1294 DUMPREG(DSI_REVISION);
1295 DUMPREG(DSI_SYSCONFIG);
1296 DUMPREG(DSI_SYSSTATUS);
1297 DUMPREG(DSI_IRQSTATUS);
1298 DUMPREG(DSI_IRQENABLE);
1299 DUMPREG(DSI_CTRL);
1300 DUMPREG(DSI_COMPLEXIO_CFG1);
1301 DUMPREG(DSI_COMPLEXIO_IRQ_STATUS);
1302 DUMPREG(DSI_COMPLEXIO_IRQ_ENABLE);
1303 DUMPREG(DSI_CLK_CTRL);
1304 DUMPREG(DSI_TIMING1);
1305 DUMPREG(DSI_TIMING2);
1306 DUMPREG(DSI_VM_TIMING1);
1307 DUMPREG(DSI_VM_TIMING2);
1308 DUMPREG(DSI_VM_TIMING3);
1309 DUMPREG(DSI_CLK_TIMING);
1310 DUMPREG(DSI_TX_FIFO_VC_SIZE);
1311 DUMPREG(DSI_RX_FIFO_VC_SIZE);
1312 DUMPREG(DSI_COMPLEXIO_CFG2);
1313 DUMPREG(DSI_RX_FIFO_VC_FULLNESS);
1314 DUMPREG(DSI_VM_TIMING4);
1315 DUMPREG(DSI_TX_FIFO_VC_EMPTINESS);
1316 DUMPREG(DSI_VM_TIMING5);
1317 DUMPREG(DSI_VM_TIMING6);
1318 DUMPREG(DSI_VM_TIMING7);
1319 DUMPREG(DSI_STOPCLK_TIMING);
1320
1321 DUMPREG(DSI_VC_CTRL(0));
1322 DUMPREG(DSI_VC_TE(0));
1323 DUMPREG(DSI_VC_LONG_PACKET_HEADER(0));
1324 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(0));
1325 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(0));
1326 DUMPREG(DSI_VC_IRQSTATUS(0));
1327 DUMPREG(DSI_VC_IRQENABLE(0));
1328
1329 DUMPREG(DSI_VC_CTRL(1));
1330 DUMPREG(DSI_VC_TE(1));
1331 DUMPREG(DSI_VC_LONG_PACKET_HEADER(1));
1332 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(1));
1333 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(1));
1334 DUMPREG(DSI_VC_IRQSTATUS(1));
1335 DUMPREG(DSI_VC_IRQENABLE(1));
1336
1337 DUMPREG(DSI_VC_CTRL(2));
1338 DUMPREG(DSI_VC_TE(2));
1339 DUMPREG(DSI_VC_LONG_PACKET_HEADER(2));
1340 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(2));
1341 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(2));
1342 DUMPREG(DSI_VC_IRQSTATUS(2));
1343 DUMPREG(DSI_VC_IRQENABLE(2));
1344
1345 DUMPREG(DSI_VC_CTRL(3));
1346 DUMPREG(DSI_VC_TE(3));
1347 DUMPREG(DSI_VC_LONG_PACKET_HEADER(3));
1348 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(3));
1349 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(3));
1350 DUMPREG(DSI_VC_IRQSTATUS(3));
1351 DUMPREG(DSI_VC_IRQENABLE(3));
1352
1353 DUMPREG(DSI_DSIPHY_CFG0);
1354 DUMPREG(DSI_DSIPHY_CFG1);
1355 DUMPREG(DSI_DSIPHY_CFG2);
1356 DUMPREG(DSI_DSIPHY_CFG5);
1357
1358 DUMPREG(DSI_PLL_CONTROL);
1359 DUMPREG(DSI_PLL_STATUS);
1360 DUMPREG(DSI_PLL_GO);
1361 DUMPREG(DSI_PLL_CONFIGURATION1);
1362 DUMPREG(DSI_PLL_CONFIGURATION2);
1363
1364 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
1365 #undef DUMPREG
1366 }
1367
1368 enum dsi_complexio_power_state {
1369 DSI_COMPLEXIO_POWER_OFF = 0x0,
1370 DSI_COMPLEXIO_POWER_ON = 0x1,
1371 DSI_COMPLEXIO_POWER_ULPS = 0x2,
1372 };
1373
1374 static int dsi_complexio_power(enum dsi_complexio_power_state state)
1375 {
1376 int t = 0;
1377
1378 /* PWR_CMD */
1379 REG_FLD_MOD(DSI_COMPLEXIO_CFG1, state, 28, 27);
1380
1381 /* PWR_STATUS */
1382 while (FLD_GET(dsi_read_reg(DSI_COMPLEXIO_CFG1), 26, 25) != state) {
1383 if (++t > 1000) {
1384 DSSERR("failed to set complexio power state to "
1385 "%d\n", state);
1386 return -ENODEV;
1387 }
1388 udelay(1);
1389 }
1390
1391 return 0;
1392 }
1393
1394 static void dsi_complexio_config(struct omap_dss_device *dssdev)
1395 {
1396 u32 r;
1397
1398 int clk_lane = dssdev->phy.dsi.clk_lane;
1399 int data1_lane = dssdev->phy.dsi.data1_lane;
1400 int data2_lane = dssdev->phy.dsi.data2_lane;
1401 int clk_pol = dssdev->phy.dsi.clk_pol;
1402 int data1_pol = dssdev->phy.dsi.data1_pol;
1403 int data2_pol = dssdev->phy.dsi.data2_pol;
1404
1405 r = dsi_read_reg(DSI_COMPLEXIO_CFG1);
1406 r = FLD_MOD(r, clk_lane, 2, 0);
1407 r = FLD_MOD(r, clk_pol, 3, 3);
1408 r = FLD_MOD(r, data1_lane, 6, 4);
1409 r = FLD_MOD(r, data1_pol, 7, 7);
1410 r = FLD_MOD(r, data2_lane, 10, 8);
1411 r = FLD_MOD(r, data2_pol, 11, 11);
1412 dsi_write_reg(DSI_COMPLEXIO_CFG1, r);
1413
1414 /* The configuration of the DSI complex I/O (number of data lanes,
1415 position, differential order) should not be changed while
1416 DSS.DSI_CLK_CRTRL[20] LP_CLK_ENABLE bit is set to 1. In order for
1417 the hardware to take into account a new configuration of the complex
1418 I/O (done in DSS.DSI_COMPLEXIO_CFG1 register), it is recommended to
1419 follow this sequence: First set the DSS.DSI_CTRL[0] IF_EN bit to 1,
1420 then reset the DSS.DSI_CTRL[0] IF_EN to 0, then set
1421 DSS.DSI_CLK_CTRL[20] LP_CLK_ENABLE to 1 and finally set again the
1422 DSS.DSI_CTRL[0] IF_EN bit to 1. If the sequence is not followed, the
1423 DSI complex I/O configuration is unknown. */
1424
1425 /*
1426 REG_FLD_MOD(DSI_CTRL, 1, 0, 0);
1427 REG_FLD_MOD(DSI_CTRL, 0, 0, 0);
1428 REG_FLD_MOD(DSI_CLK_CTRL, 1, 20, 20);
1429 REG_FLD_MOD(DSI_CTRL, 1, 0, 0);
1430 */
1431 }
1432
1433 static inline unsigned ns2ddr(unsigned ns)
1434 {
1435 /* convert time in ns to ddr ticks, rounding up */
1436 unsigned long ddr_clk = dsi.current_cinfo.clkin4ddr / 4;
1437 return (ns * (ddr_clk / 1000 / 1000) + 999) / 1000;
1438 }
1439
1440 static inline unsigned ddr2ns(unsigned ddr)
1441 {
1442 unsigned long ddr_clk = dsi.current_cinfo.clkin4ddr / 4;
1443 return ddr * 1000 * 1000 / (ddr_clk / 1000);
1444 }
1445
1446 static void dsi_complexio_timings(void)
1447 {
1448 u32 r;
1449 u32 ths_prepare, ths_prepare_ths_zero, ths_trail, ths_exit;
1450 u32 tlpx_half, tclk_trail, tclk_zero;
1451 u32 tclk_prepare;
1452
1453 /* calculate timings */
1454
1455 /* 1 * DDR_CLK = 2 * UI */
1456
1457 /* min 40ns + 4*UI max 85ns + 6*UI */
1458 ths_prepare = ns2ddr(70) + 2;
1459
1460 /* min 145ns + 10*UI */
1461 ths_prepare_ths_zero = ns2ddr(175) + 2;
1462
1463 /* min max(8*UI, 60ns+4*UI) */
1464 ths_trail = ns2ddr(60) + 5;
1465
1466 /* min 100ns */
1467 ths_exit = ns2ddr(145);
1468
1469 /* tlpx min 50n */
1470 tlpx_half = ns2ddr(25);
1471
1472 /* min 60ns */
1473 tclk_trail = ns2ddr(60) + 2;
1474
1475 /* min 38ns, max 95ns */
1476 tclk_prepare = ns2ddr(65);
1477
1478 /* min tclk-prepare + tclk-zero = 300ns */
1479 tclk_zero = ns2ddr(260);
1480
1481 DSSDBG("ths_prepare %u (%uns), ths_prepare_ths_zero %u (%uns)\n",
1482 ths_prepare, ddr2ns(ths_prepare),
1483 ths_prepare_ths_zero, ddr2ns(ths_prepare_ths_zero));
1484 DSSDBG("ths_trail %u (%uns), ths_exit %u (%uns)\n",
1485 ths_trail, ddr2ns(ths_trail),
1486 ths_exit, ddr2ns(ths_exit));
1487
1488 DSSDBG("tlpx_half %u (%uns), tclk_trail %u (%uns), "
1489 "tclk_zero %u (%uns)\n",
1490 tlpx_half, ddr2ns(tlpx_half),
1491 tclk_trail, ddr2ns(tclk_trail),
1492 tclk_zero, ddr2ns(tclk_zero));
1493 DSSDBG("tclk_prepare %u (%uns)\n",
1494 tclk_prepare, ddr2ns(tclk_prepare));
1495
1496 /* program timings */
1497
1498 r = dsi_read_reg(DSI_DSIPHY_CFG0);
1499 r = FLD_MOD(r, ths_prepare, 31, 24);
1500 r = FLD_MOD(r, ths_prepare_ths_zero, 23, 16);
1501 r = FLD_MOD(r, ths_trail, 15, 8);
1502 r = FLD_MOD(r, ths_exit, 7, 0);
1503 dsi_write_reg(DSI_DSIPHY_CFG0, r);
1504
1505 r = dsi_read_reg(DSI_DSIPHY_CFG1);
1506 r = FLD_MOD(r, tlpx_half, 22, 16);
1507 r = FLD_MOD(r, tclk_trail, 15, 8);
1508 r = FLD_MOD(r, tclk_zero, 7, 0);
1509 dsi_write_reg(DSI_DSIPHY_CFG1, r);
1510
1511 r = dsi_read_reg(DSI_DSIPHY_CFG2);
1512 r = FLD_MOD(r, tclk_prepare, 7, 0);
1513 dsi_write_reg(DSI_DSIPHY_CFG2, r);
1514 }
1515
1516
1517 static int dsi_complexio_init(struct omap_dss_device *dssdev)
1518 {
1519 int r = 0;
1520
1521 DSSDBG("dsi_complexio_init\n");
1522
1523 /* CIO_CLK_ICG, enable L3 clk to CIO */
1524 REG_FLD_MOD(DSI_CLK_CTRL, 1, 14, 14);
1525
1526 /* A dummy read using the SCP interface to any DSIPHY register is
1527 * required after DSIPHY reset to complete the reset of the DSI complex
1528 * I/O. */
1529 dsi_read_reg(DSI_DSIPHY_CFG5);
1530
1531 if (wait_for_bit_change(DSI_DSIPHY_CFG5, 30, 1) != 1) {
1532 DSSERR("ComplexIO PHY not coming out of reset.\n");
1533 r = -ENODEV;
1534 goto err;
1535 }
1536
1537 dsi_complexio_config(dssdev);
1538
1539 r = dsi_complexio_power(DSI_COMPLEXIO_POWER_ON);
1540
1541 if (r)
1542 goto err;
1543
1544 if (wait_for_bit_change(DSI_COMPLEXIO_CFG1, 29, 1) != 1) {
1545 DSSERR("ComplexIO not coming out of reset.\n");
1546 r = -ENODEV;
1547 goto err;
1548 }
1549
1550 if (wait_for_bit_change(DSI_COMPLEXIO_CFG1, 21, 1) != 1) {
1551 DSSERR("ComplexIO LDO power down.\n");
1552 r = -ENODEV;
1553 goto err;
1554 }
1555
1556 dsi_complexio_timings();
1557
1558 /*
1559 The configuration of the DSI complex I/O (number of data lanes,
1560 position, differential order) should not be changed while
1561 DSS.DSI_CLK_CRTRL[20] LP_CLK_ENABLE bit is set to 1. For the
1562 hardware to recognize a new configuration of the complex I/O (done
1563 in DSS.DSI_COMPLEXIO_CFG1 register), it is recommended to follow
1564 this sequence: First set the DSS.DSI_CTRL[0] IF_EN bit to 1, next
1565 reset the DSS.DSI_CTRL[0] IF_EN to 0, then set DSS.DSI_CLK_CTRL[20]
1566 LP_CLK_ENABLE to 1, and finally, set again the DSS.DSI_CTRL[0] IF_EN
1567 bit to 1. If the sequence is not followed, the DSi complex I/O
1568 configuration is undetermined.
1569 */
1570 dsi_if_enable(1);
1571 dsi_if_enable(0);
1572 REG_FLD_MOD(DSI_CLK_CTRL, 1, 20, 20); /* LP_CLK_ENABLE */
1573 dsi_if_enable(1);
1574 dsi_if_enable(0);
1575
1576 DSSDBG("CIO init done\n");
1577 err:
1578 return r;
1579 }
1580
1581 static void dsi_complexio_uninit(void)
1582 {
1583 dsi_complexio_power(DSI_COMPLEXIO_POWER_OFF);
1584 }
1585
1586 static int _dsi_wait_reset(void)
1587 {
1588 int t = 0;
1589
1590 while (REG_GET(DSI_SYSSTATUS, 0, 0) == 0) {
1591 if (++t > 5) {
1592 DSSERR("soft reset failed\n");
1593 return -ENODEV;
1594 }
1595 udelay(1);
1596 }
1597
1598 return 0;
1599 }
1600
1601 static int _dsi_reset(void)
1602 {
1603 /* Soft reset */
1604 REG_FLD_MOD(DSI_SYSCONFIG, 1, 1, 1);
1605 return _dsi_wait_reset();
1606 }
1607
1608 static void dsi_reset_tx_fifo(int channel)
1609 {
1610 u32 mask;
1611 u32 l;
1612
1613 /* set fifosize of the channel to 0, then return the old size */
1614 l = dsi_read_reg(DSI_TX_FIFO_VC_SIZE);
1615
1616 mask = FLD_MASK((8 * channel) + 7, (8 * channel) + 4);
1617 dsi_write_reg(DSI_TX_FIFO_VC_SIZE, l & ~mask);
1618
1619 dsi_write_reg(DSI_TX_FIFO_VC_SIZE, l);
1620 }
1621
1622 static void dsi_config_tx_fifo(enum fifo_size size1, enum fifo_size size2,
1623 enum fifo_size size3, enum fifo_size size4)
1624 {
1625 u32 r = 0;
1626 int add = 0;
1627 int i;
1628
1629 dsi.vc[0].fifo_size = size1;
1630 dsi.vc[1].fifo_size = size2;
1631 dsi.vc[2].fifo_size = size3;
1632 dsi.vc[3].fifo_size = size4;
1633
1634 for (i = 0; i < 4; i++) {
1635 u8 v;
1636 int size = dsi.vc[i].fifo_size;
1637
1638 if (add + size > 4) {
1639 DSSERR("Illegal FIFO configuration\n");
1640 BUG();
1641 }
1642
1643 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
1644 r |= v << (8 * i);
1645 /*DSSDBG("TX FIFO vc %d: size %d, add %d\n", i, size, add); */
1646 add += size;
1647 }
1648
1649 dsi_write_reg(DSI_TX_FIFO_VC_SIZE, r);
1650 }
1651
1652 static void dsi_config_rx_fifo(enum fifo_size size1, enum fifo_size size2,
1653 enum fifo_size size3, enum fifo_size size4)
1654 {
1655 u32 r = 0;
1656 int add = 0;
1657 int i;
1658
1659 dsi.vc[0].fifo_size = size1;
1660 dsi.vc[1].fifo_size = size2;
1661 dsi.vc[2].fifo_size = size3;
1662 dsi.vc[3].fifo_size = size4;
1663
1664 for (i = 0; i < 4; i++) {
1665 u8 v;
1666 int size = dsi.vc[i].fifo_size;
1667
1668 if (add + size > 4) {
1669 DSSERR("Illegal FIFO configuration\n");
1670 BUG();
1671 }
1672
1673 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
1674 r |= v << (8 * i);
1675 /*DSSDBG("RX FIFO vc %d: size %d, add %d\n", i, size, add); */
1676 add += size;
1677 }
1678
1679 dsi_write_reg(DSI_RX_FIFO_VC_SIZE, r);
1680 }
1681
1682 static int dsi_force_tx_stop_mode_io(void)
1683 {
1684 u32 r;
1685
1686 r = dsi_read_reg(DSI_TIMING1);
1687 r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
1688 dsi_write_reg(DSI_TIMING1, r);
1689
1690 if (wait_for_bit_change(DSI_TIMING1, 15, 0) != 0) {
1691 DSSERR("TX_STOP bit not going down\n");
1692 return -EIO;
1693 }
1694
1695 return 0;
1696 }
1697
1698 static int dsi_vc_enable(int channel, bool enable)
1699 {
1700 DSSDBG("dsi_vc_enable channel %d, enable %d\n",
1701 channel, enable);
1702
1703 enable = enable ? 1 : 0;
1704
1705 REG_FLD_MOD(DSI_VC_CTRL(channel), enable, 0, 0);
1706
1707 if (wait_for_bit_change(DSI_VC_CTRL(channel), 0, enable) != enable) {
1708 DSSERR("Failed to set dsi_vc_enable to %d\n", enable);
1709 return -EIO;
1710 }
1711
1712 return 0;
1713 }
1714
1715 static void dsi_vc_initial_config(int channel)
1716 {
1717 u32 r;
1718
1719 DSSDBGF("%d", channel);
1720
1721 r = dsi_read_reg(DSI_VC_CTRL(channel));
1722
1723 if (FLD_GET(r, 15, 15)) /* VC_BUSY */
1724 DSSERR("VC(%d) busy when trying to configure it!\n",
1725 channel);
1726
1727 r = FLD_MOD(r, 0, 1, 1); /* SOURCE, 0 = L4 */
1728 r = FLD_MOD(r, 0, 2, 2); /* BTA_SHORT_EN */
1729 r = FLD_MOD(r, 0, 3, 3); /* BTA_LONG_EN */
1730 r = FLD_MOD(r, 0, 4, 4); /* MODE, 0 = command */
1731 r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */
1732 r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */
1733 r = FLD_MOD(r, 0, 9, 9); /* MODE_SPEED, high speed on/off */
1734
1735 r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */
1736 r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */
1737
1738 dsi_write_reg(DSI_VC_CTRL(channel), r);
1739
1740 dsi.vc[channel].mode = DSI_VC_MODE_L4;
1741 }
1742
1743 static void dsi_vc_config_l4(int channel)
1744 {
1745 if (dsi.vc[channel].mode == DSI_VC_MODE_L4)
1746 return;
1747
1748 DSSDBGF("%d", channel);
1749
1750 dsi_vc_enable(channel, 0);
1751
1752 if (REG_GET(DSI_VC_CTRL(channel), 15, 15)) /* VC_BUSY */
1753 DSSERR("vc(%d) busy when trying to config for L4\n", channel);
1754
1755 REG_FLD_MOD(DSI_VC_CTRL(channel), 0, 1, 1); /* SOURCE, 0 = L4 */
1756
1757 dsi_vc_enable(channel, 1);
1758
1759 dsi.vc[channel].mode = DSI_VC_MODE_L4;
1760 }
1761
1762 static void dsi_vc_config_vp(int channel)
1763 {
1764 if (dsi.vc[channel].mode == DSI_VC_MODE_VP)
1765 return;
1766
1767 DSSDBGF("%d", channel);
1768
1769 dsi_vc_enable(channel, 0);
1770
1771 if (REG_GET(DSI_VC_CTRL(channel), 15, 15)) /* VC_BUSY */
1772 DSSERR("vc(%d) busy when trying to config for VP\n", channel);
1773
1774 REG_FLD_MOD(DSI_VC_CTRL(channel), 1, 1, 1); /* SOURCE, 1 = video port */
1775
1776 dsi_vc_enable(channel, 1);
1777
1778 dsi.vc[channel].mode = DSI_VC_MODE_VP;
1779 }
1780
1781
1782 void omapdss_dsi_vc_enable_hs(int channel, bool enable)
1783 {
1784 DSSDBG("dsi_vc_enable_hs(%d, %d)\n", channel, enable);
1785
1786 WARN_ON(!dsi_bus_is_locked());
1787
1788 dsi_vc_enable(channel, 0);
1789 dsi_if_enable(0);
1790
1791 REG_FLD_MOD(DSI_VC_CTRL(channel), enable, 9, 9);
1792
1793 dsi_vc_enable(channel, 1);
1794 dsi_if_enable(1);
1795
1796 dsi_force_tx_stop_mode_io();
1797 }
1798 EXPORT_SYMBOL(omapdss_dsi_vc_enable_hs);
1799
1800 static void dsi_vc_flush_long_data(int channel)
1801 {
1802 while (REG_GET(DSI_VC_CTRL(channel), 20, 20)) {
1803 u32 val;
1804 val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
1805 DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 %#02x\n",
1806 (val >> 0) & 0xff,
1807 (val >> 8) & 0xff,
1808 (val >> 16) & 0xff,
1809 (val >> 24) & 0xff);
1810 }
1811 }
1812
1813 static void dsi_show_rx_ack_with_err(u16 err)
1814 {
1815 DSSERR("\tACK with ERROR (%#x):\n", err);
1816 if (err & (1 << 0))
1817 DSSERR("\t\tSoT Error\n");
1818 if (err & (1 << 1))
1819 DSSERR("\t\tSoT Sync Error\n");
1820 if (err & (1 << 2))
1821 DSSERR("\t\tEoT Sync Error\n");
1822 if (err & (1 << 3))
1823 DSSERR("\t\tEscape Mode Entry Command Error\n");
1824 if (err & (1 << 4))
1825 DSSERR("\t\tLP Transmit Sync Error\n");
1826 if (err & (1 << 5))
1827 DSSERR("\t\tHS Receive Timeout Error\n");
1828 if (err & (1 << 6))
1829 DSSERR("\t\tFalse Control Error\n");
1830 if (err & (1 << 7))
1831 DSSERR("\t\t(reserved7)\n");
1832 if (err & (1 << 8))
1833 DSSERR("\t\tECC Error, single-bit (corrected)\n");
1834 if (err & (1 << 9))
1835 DSSERR("\t\tECC Error, multi-bit (not corrected)\n");
1836 if (err & (1 << 10))
1837 DSSERR("\t\tChecksum Error\n");
1838 if (err & (1 << 11))
1839 DSSERR("\t\tData type not recognized\n");
1840 if (err & (1 << 12))
1841 DSSERR("\t\tInvalid VC ID\n");
1842 if (err & (1 << 13))
1843 DSSERR("\t\tInvalid Transmission Length\n");
1844 if (err & (1 << 14))
1845 DSSERR("\t\t(reserved14)\n");
1846 if (err & (1 << 15))
1847 DSSERR("\t\tDSI Protocol Violation\n");
1848 }
1849
1850 static u16 dsi_vc_flush_receive_data(int channel)
1851 {
1852 /* RX_FIFO_NOT_EMPTY */
1853 while (REG_GET(DSI_VC_CTRL(channel), 20, 20)) {
1854 u32 val;
1855 u8 dt;
1856 val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
1857 DSSDBG("\trawval %#08x\n", val);
1858 dt = FLD_GET(val, 5, 0);
1859 if (dt == DSI_DT_RX_ACK_WITH_ERR) {
1860 u16 err = FLD_GET(val, 23, 8);
1861 dsi_show_rx_ack_with_err(err);
1862 } else if (dt == DSI_DT_RX_SHORT_READ_1) {
1863 DSSDBG("\tDCS short response, 1 byte: %#x\n",
1864 FLD_GET(val, 23, 8));
1865 } else if (dt == DSI_DT_RX_SHORT_READ_2) {
1866 DSSDBG("\tDCS short response, 2 byte: %#x\n",
1867 FLD_GET(val, 23, 8));
1868 } else if (dt == DSI_DT_RX_DCS_LONG_READ) {
1869 DSSDBG("\tDCS long response, len %d\n",
1870 FLD_GET(val, 23, 8));
1871 dsi_vc_flush_long_data(channel);
1872 } else {
1873 DSSERR("\tunknown datatype 0x%02x\n", dt);
1874 }
1875 }
1876 return 0;
1877 }
1878
1879 static int dsi_vc_send_bta(int channel)
1880 {
1881 if (dsi.debug_write || dsi.debug_read)
1882 DSSDBG("dsi_vc_send_bta %d\n", channel);
1883
1884 WARN_ON(!dsi_bus_is_locked());
1885
1886 if (REG_GET(DSI_VC_CTRL(channel), 20, 20)) { /* RX_FIFO_NOT_EMPTY */
1887 DSSERR("rx fifo not empty when sending BTA, dumping data:\n");
1888 dsi_vc_flush_receive_data(channel);
1889 }
1890
1891 REG_FLD_MOD(DSI_VC_CTRL(channel), 1, 6, 6); /* BTA_EN */
1892
1893 return 0;
1894 }
1895
1896 int dsi_vc_send_bta_sync(int channel)
1897 {
1898 int r = 0;
1899 u32 err;
1900
1901 INIT_COMPLETION(dsi.bta_completion);
1902
1903 dsi_vc_enable_bta_irq(channel);
1904
1905 r = dsi_vc_send_bta(channel);
1906 if (r)
1907 goto err;
1908
1909 if (wait_for_completion_timeout(&dsi.bta_completion,
1910 msecs_to_jiffies(500)) == 0) {
1911 DSSERR("Failed to receive BTA\n");
1912 r = -EIO;
1913 goto err;
1914 }
1915
1916 err = dsi_get_errors();
1917 if (err) {
1918 DSSERR("Error while sending BTA: %x\n", err);
1919 r = -EIO;
1920 goto err;
1921 }
1922 err:
1923 dsi_vc_disable_bta_irq(channel);
1924
1925 return r;
1926 }
1927 EXPORT_SYMBOL(dsi_vc_send_bta_sync);
1928
1929 static inline void dsi_vc_write_long_header(int channel, u8 data_type,
1930 u16 len, u8 ecc)
1931 {
1932 u32 val;
1933 u8 data_id;
1934
1935 WARN_ON(!dsi_bus_is_locked());
1936
1937 data_id = data_type | channel << 6;
1938
1939 val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) |
1940 FLD_VAL(ecc, 31, 24);
1941
1942 dsi_write_reg(DSI_VC_LONG_PACKET_HEADER(channel), val);
1943 }
1944
1945 static inline void dsi_vc_write_long_payload(int channel,
1946 u8 b1, u8 b2, u8 b3, u8 b4)
1947 {
1948 u32 val;
1949
1950 val = b4 << 24 | b3 << 16 | b2 << 8 | b1 << 0;
1951
1952 /* DSSDBG("\twriting %02x, %02x, %02x, %02x (%#010x)\n",
1953 b1, b2, b3, b4, val); */
1954
1955 dsi_write_reg(DSI_VC_LONG_PACKET_PAYLOAD(channel), val);
1956 }
1957
1958 static int dsi_vc_send_long(int channel, u8 data_type, u8 *data, u16 len,
1959 u8 ecc)
1960 {
1961 /*u32 val; */
1962 int i;
1963 u8 *p;
1964 int r = 0;
1965 u8 b1, b2, b3, b4;
1966
1967 if (dsi.debug_write)
1968 DSSDBG("dsi_vc_send_long, %d bytes\n", len);
1969
1970 /* len + header */
1971 if (dsi.vc[channel].fifo_size * 32 * 4 < len + 4) {
1972 DSSERR("unable to send long packet: packet too long.\n");
1973 return -EINVAL;
1974 }
1975
1976 dsi_vc_config_l4(channel);
1977
1978 dsi_vc_write_long_header(channel, data_type, len, ecc);
1979
1980 p = data;
1981 for (i = 0; i < len >> 2; i++) {
1982 if (dsi.debug_write)
1983 DSSDBG("\tsending full packet %d\n", i);
1984
1985 b1 = *p++;
1986 b2 = *p++;
1987 b3 = *p++;
1988 b4 = *p++;
1989
1990 dsi_vc_write_long_payload(channel, b1, b2, b3, b4);
1991 }
1992
1993 i = len % 4;
1994 if (i) {
1995 b1 = 0; b2 = 0; b3 = 0;
1996
1997 if (dsi.debug_write)
1998 DSSDBG("\tsending remainder bytes %d\n", i);
1999
2000 switch (i) {
2001 case 3:
2002 b1 = *p++;
2003 b2 = *p++;
2004 b3 = *p++;
2005 break;
2006 case 2:
2007 b1 = *p++;
2008 b2 = *p++;
2009 break;
2010 case 1:
2011 b1 = *p++;
2012 break;
2013 }
2014
2015 dsi_vc_write_long_payload(channel, b1, b2, b3, 0);
2016 }
2017
2018 return r;
2019 }
2020
2021 static int dsi_vc_send_short(int channel, u8 data_type, u16 data, u8 ecc)
2022 {
2023 u32 r;
2024 u8 data_id;
2025
2026 WARN_ON(!dsi_bus_is_locked());
2027
2028 if (dsi.debug_write)
2029 DSSDBG("dsi_vc_send_short(ch%d, dt %#x, b1 %#x, b2 %#x)\n",
2030 channel,
2031 data_type, data & 0xff, (data >> 8) & 0xff);
2032
2033 dsi_vc_config_l4(channel);
2034
2035 if (FLD_GET(dsi_read_reg(DSI_VC_CTRL(channel)), 16, 16)) {
2036 DSSERR("ERROR FIFO FULL, aborting transfer\n");
2037 return -EINVAL;
2038 }
2039
2040 data_id = data_type | channel << 6;
2041
2042 r = (data_id << 0) | (data << 8) | (ecc << 24);
2043
2044 dsi_write_reg(DSI_VC_SHORT_PACKET_HEADER(channel), r);
2045
2046 return 0;
2047 }
2048
2049 int dsi_vc_send_null(int channel)
2050 {
2051 u8 nullpkg[] = {0, 0, 0, 0};
2052 return dsi_vc_send_long(channel, DSI_DT_NULL_PACKET, nullpkg, 4, 0);
2053 }
2054 EXPORT_SYMBOL(dsi_vc_send_null);
2055
2056 int dsi_vc_dcs_write_nosync(int channel, u8 *data, int len)
2057 {
2058 int r;
2059
2060 BUG_ON(len == 0);
2061
2062 if (len == 1) {
2063 r = dsi_vc_send_short(channel, DSI_DT_DCS_SHORT_WRITE_0,
2064 data[0], 0);
2065 } else if (len == 2) {
2066 r = dsi_vc_send_short(channel, DSI_DT_DCS_SHORT_WRITE_1,
2067 data[0] | (data[1] << 8), 0);
2068 } else {
2069 /* 0x39 = DCS Long Write */
2070 r = dsi_vc_send_long(channel, DSI_DT_DCS_LONG_WRITE,
2071 data, len, 0);
2072 }
2073
2074 return r;
2075 }
2076 EXPORT_SYMBOL(dsi_vc_dcs_write_nosync);
2077
2078 int dsi_vc_dcs_write(int channel, u8 *data, int len)
2079 {
2080 int r;
2081
2082 r = dsi_vc_dcs_write_nosync(channel, data, len);
2083 if (r)
2084 goto err;
2085
2086 r = dsi_vc_send_bta_sync(channel);
2087 if (r)
2088 goto err;
2089
2090 return 0;
2091 err:
2092 DSSERR("dsi_vc_dcs_write(ch %d, cmd 0x%02x, len %d) failed\n",
2093 channel, data[0], len);
2094 return r;
2095 }
2096 EXPORT_SYMBOL(dsi_vc_dcs_write);
2097
2098 int dsi_vc_dcs_write_0(int channel, u8 dcs_cmd)
2099 {
2100 return dsi_vc_dcs_write(channel, &dcs_cmd, 1);
2101 }
2102 EXPORT_SYMBOL(dsi_vc_dcs_write_0);
2103
2104 int dsi_vc_dcs_write_1(int channel, u8 dcs_cmd, u8 param)
2105 {
2106 u8 buf[2];
2107 buf[0] = dcs_cmd;
2108 buf[1] = param;
2109 return dsi_vc_dcs_write(channel, buf, 2);
2110 }
2111 EXPORT_SYMBOL(dsi_vc_dcs_write_1);
2112
2113 int dsi_vc_dcs_read(int channel, u8 dcs_cmd, u8 *buf, int buflen)
2114 {
2115 u32 val;
2116 u8 dt;
2117 int r;
2118
2119 if (dsi.debug_read)
2120 DSSDBG("dsi_vc_dcs_read(ch%d, dcs_cmd %x)\n", channel, dcs_cmd);
2121
2122 r = dsi_vc_send_short(channel, DSI_DT_DCS_READ, dcs_cmd, 0);
2123 if (r)
2124 goto err;
2125
2126 r = dsi_vc_send_bta_sync(channel);
2127 if (r)
2128 goto err;
2129
2130 /* RX_FIFO_NOT_EMPTY */
2131 if (REG_GET(DSI_VC_CTRL(channel), 20, 20) == 0) {
2132 DSSERR("RX fifo empty when trying to read.\n");
2133 r = -EIO;
2134 goto err;
2135 }
2136
2137 val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
2138 if (dsi.debug_read)
2139 DSSDBG("\theader: %08x\n", val);
2140 dt = FLD_GET(val, 5, 0);
2141 if (dt == DSI_DT_RX_ACK_WITH_ERR) {
2142 u16 err = FLD_GET(val, 23, 8);
2143 dsi_show_rx_ack_with_err(err);
2144 r = -EIO;
2145 goto err;
2146
2147 } else if (dt == DSI_DT_RX_SHORT_READ_1) {
2148 u8 data = FLD_GET(val, 15, 8);
2149 if (dsi.debug_read)
2150 DSSDBG("\tDCS short response, 1 byte: %02x\n", data);
2151
2152 if (buflen < 1) {
2153 r = -EIO;
2154 goto err;
2155 }
2156
2157 buf[0] = data;
2158
2159 return 1;
2160 } else if (dt == DSI_DT_RX_SHORT_READ_2) {
2161 u16 data = FLD_GET(val, 23, 8);
2162 if (dsi.debug_read)
2163 DSSDBG("\tDCS short response, 2 byte: %04x\n", data);
2164
2165 if (buflen < 2) {
2166 r = -EIO;
2167 goto err;
2168 }
2169
2170 buf[0] = data & 0xff;
2171 buf[1] = (data >> 8) & 0xff;
2172
2173 return 2;
2174 } else if (dt == DSI_DT_RX_DCS_LONG_READ) {
2175 int w;
2176 int len = FLD_GET(val, 23, 8);
2177 if (dsi.debug_read)
2178 DSSDBG("\tDCS long response, len %d\n", len);
2179
2180 if (len > buflen) {
2181 r = -EIO;
2182 goto err;
2183 }
2184
2185 /* two byte checksum ends the packet, not included in len */
2186 for (w = 0; w < len + 2;) {
2187 int b;
2188 val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
2189 if (dsi.debug_read)
2190 DSSDBG("\t\t%02x %02x %02x %02x\n",
2191 (val >> 0) & 0xff,
2192 (val >> 8) & 0xff,
2193 (val >> 16) & 0xff,
2194 (val >> 24) & 0xff);
2195
2196 for (b = 0; b < 4; ++b) {
2197 if (w < len)
2198 buf[w] = (val >> (b * 8)) & 0xff;
2199 /* we discard the 2 byte checksum */
2200 ++w;
2201 }
2202 }
2203
2204 return len;
2205 } else {
2206 DSSERR("\tunknown datatype 0x%02x\n", dt);
2207 r = -EIO;
2208 goto err;
2209 }
2210
2211 BUG();
2212 err:
2213 DSSERR("dsi_vc_dcs_read(ch %d, cmd 0x%02x) failed\n",
2214 channel, dcs_cmd);
2215 return r;
2216
2217 }
2218 EXPORT_SYMBOL(dsi_vc_dcs_read);
2219
2220 int dsi_vc_dcs_read_1(int channel, u8 dcs_cmd, u8 *data)
2221 {
2222 int r;
2223
2224 r = dsi_vc_dcs_read(channel, dcs_cmd, data, 1);
2225
2226 if (r < 0)
2227 return r;
2228
2229 if (r != 1)
2230 return -EIO;
2231
2232 return 0;
2233 }
2234 EXPORT_SYMBOL(dsi_vc_dcs_read_1);
2235
2236 int dsi_vc_dcs_read_2(int channel, u8 dcs_cmd, u16 *data)
2237 {
2238 int r;
2239
2240 r = dsi_vc_dcs_read(channel, dcs_cmd, (u8 *)data, 2);
2241
2242 if (r < 0)
2243 return r;
2244
2245 if (r != 2)
2246 return -EIO;
2247
2248 return 0;
2249 }
2250 EXPORT_SYMBOL(dsi_vc_dcs_read_2);
2251
2252 int dsi_vc_set_max_rx_packet_size(int channel, u16 len)
2253 {
2254 int r;
2255 r = dsi_vc_send_short(channel, DSI_DT_SET_MAX_RET_PKG_SIZE,
2256 len, 0);
2257
2258 if (r)
2259 return r;
2260
2261 r = dsi_vc_send_bta_sync(channel);
2262
2263 return r;
2264 }
2265 EXPORT_SYMBOL(dsi_vc_set_max_rx_packet_size);
2266
2267 static void dsi_set_lp_rx_timeout(unsigned long ns)
2268 {
2269 u32 r;
2270 unsigned x4, x16;
2271 unsigned long fck;
2272 unsigned long ticks;
2273
2274 /* ticks in DSI_FCK */
2275
2276 fck = dsi_fclk_rate();
2277 ticks = (fck / 1000 / 1000) * ns / 1000;
2278 x4 = 0;
2279 x16 = 0;
2280
2281 if (ticks > 0x1fff) {
2282 ticks = (fck / 1000 / 1000) * ns / 1000 / 4;
2283 x4 = 1;
2284 x16 = 0;
2285 }
2286
2287 if (ticks > 0x1fff) {
2288 ticks = (fck / 1000 / 1000) * ns / 1000 / 16;
2289 x4 = 0;
2290 x16 = 1;
2291 }
2292
2293 if (ticks > 0x1fff) {
2294 ticks = (fck / 1000 / 1000) * ns / 1000 / (4 * 16);
2295 x4 = 1;
2296 x16 = 1;
2297 }
2298
2299 if (ticks > 0x1fff) {
2300 DSSWARN("LP_TX_TO over limit, setting it to max\n");
2301 ticks = 0x1fff;
2302 x4 = 1;
2303 x16 = 1;
2304 }
2305
2306 r = dsi_read_reg(DSI_TIMING2);
2307 r = FLD_MOD(r, 1, 15, 15); /* LP_RX_TO */
2308 r = FLD_MOD(r, x16, 14, 14); /* LP_RX_TO_X16 */
2309 r = FLD_MOD(r, x4, 13, 13); /* LP_RX_TO_X4 */
2310 r = FLD_MOD(r, ticks, 12, 0); /* LP_RX_COUNTER */
2311 dsi_write_reg(DSI_TIMING2, r);
2312
2313 DSSDBG("LP_RX_TO %lu ns (%#lx ticks%s%s)\n",
2314 (ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1) * 1000) /
2315 (fck / 1000 / 1000),
2316 ticks, x4 ? " x4" : "", x16 ? " x16" : "");
2317 }
2318
2319 static void dsi_set_ta_timeout(unsigned long ns)
2320 {
2321 u32 r;
2322 unsigned x8, x16;
2323 unsigned long fck;
2324 unsigned long ticks;
2325
2326 /* ticks in DSI_FCK */
2327 fck = dsi_fclk_rate();
2328 ticks = (fck / 1000 / 1000) * ns / 1000;
2329 x8 = 0;
2330 x16 = 0;
2331
2332 if (ticks > 0x1fff) {
2333 ticks = (fck / 1000 / 1000) * ns / 1000 / 8;
2334 x8 = 1;
2335 x16 = 0;
2336 }
2337
2338 if (ticks > 0x1fff) {
2339 ticks = (fck / 1000 / 1000) * ns / 1000 / 16;
2340 x8 = 0;
2341 x16 = 1;
2342 }
2343
2344 if (ticks > 0x1fff) {
2345 ticks = (fck / 1000 / 1000) * ns / 1000 / (8 * 16);
2346 x8 = 1;
2347 x16 = 1;
2348 }
2349
2350 if (ticks > 0x1fff) {
2351 DSSWARN("TA_TO over limit, setting it to max\n");
2352 ticks = 0x1fff;
2353 x8 = 1;
2354 x16 = 1;
2355 }
2356
2357 r = dsi_read_reg(DSI_TIMING1);
2358 r = FLD_MOD(r, 1, 31, 31); /* TA_TO */
2359 r = FLD_MOD(r, x16, 30, 30); /* TA_TO_X16 */
2360 r = FLD_MOD(r, x8, 29, 29); /* TA_TO_X8 */
2361 r = FLD_MOD(r, ticks, 28, 16); /* TA_TO_COUNTER */
2362 dsi_write_reg(DSI_TIMING1, r);
2363
2364 DSSDBG("TA_TO %lu ns (%#lx ticks%s%s)\n",
2365 (ticks * (x16 ? 16 : 1) * (x8 ? 8 : 1) * 1000) /
2366 (fck / 1000 / 1000),
2367 ticks, x8 ? " x8" : "", x16 ? " x16" : "");
2368 }
2369
2370 static void dsi_set_stop_state_counter(unsigned long ns)
2371 {
2372 u32 r;
2373 unsigned x4, x16;
2374 unsigned long fck;
2375 unsigned long ticks;
2376
2377 /* ticks in DSI_FCK */
2378
2379 fck = dsi_fclk_rate();
2380 ticks = (fck / 1000 / 1000) * ns / 1000;
2381 x4 = 0;
2382 x16 = 0;
2383
2384 if (ticks > 0x1fff) {
2385 ticks = (fck / 1000 / 1000) * ns / 1000 / 4;
2386 x4 = 1;
2387 x16 = 0;
2388 }
2389
2390 if (ticks > 0x1fff) {
2391 ticks = (fck / 1000 / 1000) * ns / 1000 / 16;
2392 x4 = 0;
2393 x16 = 1;
2394 }
2395
2396 if (ticks > 0x1fff) {
2397 ticks = (fck / 1000 / 1000) * ns / 1000 / (4 * 16);
2398 x4 = 1;
2399 x16 = 1;
2400 }
2401
2402 if (ticks > 0x1fff) {
2403 DSSWARN("STOP_STATE_COUNTER_IO over limit, "
2404 "setting it to max\n");
2405 ticks = 0x1fff;
2406 x4 = 1;
2407 x16 = 1;
2408 }
2409
2410 r = dsi_read_reg(DSI_TIMING1);
2411 r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
2412 r = FLD_MOD(r, x16, 14, 14); /* STOP_STATE_X16_IO */
2413 r = FLD_MOD(r, x4, 13, 13); /* STOP_STATE_X4_IO */
2414 r = FLD_MOD(r, ticks, 12, 0); /* STOP_STATE_COUNTER_IO */
2415 dsi_write_reg(DSI_TIMING1, r);
2416
2417 DSSDBG("STOP_STATE_COUNTER %lu ns (%#lx ticks%s%s)\n",
2418 (ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1) * 1000) /
2419 (fck / 1000 / 1000),
2420 ticks, x4 ? " x4" : "", x16 ? " x16" : "");
2421 }
2422
2423 static void dsi_set_hs_tx_timeout(unsigned long ns)
2424 {
2425 u32 r;
2426 unsigned x4, x16;
2427 unsigned long fck;
2428 unsigned long ticks;
2429
2430 /* ticks in TxByteClkHS */
2431
2432 fck = dsi_get_txbyteclkhs();
2433 ticks = (fck / 1000 / 1000) * ns / 1000;
2434 x4 = 0;
2435 x16 = 0;
2436
2437 if (ticks > 0x1fff) {
2438 ticks = (fck / 1000 / 1000) * ns / 1000 / 4;
2439 x4 = 1;
2440 x16 = 0;
2441 }
2442
2443 if (ticks > 0x1fff) {
2444 ticks = (fck / 1000 / 1000) * ns / 1000 / 16;
2445 x4 = 0;
2446 x16 = 1;
2447 }
2448
2449 if (ticks > 0x1fff) {
2450 ticks = (fck / 1000 / 1000) * ns / 1000 / (4 * 16);
2451 x4 = 1;
2452 x16 = 1;
2453 }
2454
2455 if (ticks > 0x1fff) {
2456 DSSWARN("HS_TX_TO over limit, setting it to max\n");
2457 ticks = 0x1fff;
2458 x4 = 1;
2459 x16 = 1;
2460 }
2461
2462 r = dsi_read_reg(DSI_TIMING2);
2463 r = FLD_MOD(r, 1, 31, 31); /* HS_TX_TO */
2464 r = FLD_MOD(r, x16, 30, 30); /* HS_TX_TO_X16 */
2465 r = FLD_MOD(r, x4, 29, 29); /* HS_TX_TO_X8 (4 really) */
2466 r = FLD_MOD(r, ticks, 28, 16); /* HS_TX_TO_COUNTER */
2467 dsi_write_reg(DSI_TIMING2, r);
2468
2469 DSSDBG("HS_TX_TO %lu ns (%#lx ticks%s%s)\n",
2470 (ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1) * 1000) /
2471 (fck / 1000 / 1000),
2472 ticks, x4 ? " x4" : "", x16 ? " x16" : "");
2473 }
2474 static int dsi_proto_config(struct omap_dss_device *dssdev)
2475 {
2476 u32 r;
2477 int buswidth = 0;
2478
2479 dsi_config_tx_fifo(DSI_FIFO_SIZE_32,
2480 DSI_FIFO_SIZE_32,
2481 DSI_FIFO_SIZE_32,
2482 DSI_FIFO_SIZE_32);
2483
2484 dsi_config_rx_fifo(DSI_FIFO_SIZE_32,
2485 DSI_FIFO_SIZE_32,
2486 DSI_FIFO_SIZE_32,
2487 DSI_FIFO_SIZE_32);
2488
2489 /* XXX what values for the timeouts? */
2490 dsi_set_stop_state_counter(1000);
2491 dsi_set_ta_timeout(6400000);
2492 dsi_set_lp_rx_timeout(48000);
2493 dsi_set_hs_tx_timeout(1000000);
2494
2495 switch (dssdev->ctrl.pixel_size) {
2496 case 16:
2497 buswidth = 0;
2498 break;
2499 case 18:
2500 buswidth = 1;
2501 break;
2502 case 24:
2503 buswidth = 2;
2504 break;
2505 default:
2506 BUG();
2507 }
2508
2509 r = dsi_read_reg(DSI_CTRL);
2510 r = FLD_MOD(r, 1, 1, 1); /* CS_RX_EN */
2511 r = FLD_MOD(r, 1, 2, 2); /* ECC_RX_EN */
2512 r = FLD_MOD(r, 1, 3, 3); /* TX_FIFO_ARBITRATION */
2513 r = FLD_MOD(r, 1, 4, 4); /* VP_CLK_RATIO, always 1, see errata*/
2514 r = FLD_MOD(r, buswidth, 7, 6); /* VP_DATA_BUS_WIDTH */
2515 r = FLD_MOD(r, 0, 8, 8); /* VP_CLK_POL */
2516 r = FLD_MOD(r, 2, 13, 12); /* LINE_BUFFER, 2 lines */
2517 r = FLD_MOD(r, 1, 14, 14); /* TRIGGER_RESET_MODE */
2518 r = FLD_MOD(r, 1, 19, 19); /* EOT_ENABLE */
2519 r = FLD_MOD(r, 1, 24, 24); /* DCS_CMD_ENABLE */
2520 r = FLD_MOD(r, 0, 25, 25); /* DCS_CMD_CODE, 1=start, 0=continue */
2521
2522 dsi_write_reg(DSI_CTRL, r);
2523
2524 dsi_vc_initial_config(0);
2525 dsi_vc_initial_config(1);
2526 dsi_vc_initial_config(2);
2527 dsi_vc_initial_config(3);
2528
2529 return 0;
2530 }
2531
2532 static void dsi_proto_timings(struct omap_dss_device *dssdev)
2533 {
2534 unsigned tlpx, tclk_zero, tclk_prepare, tclk_trail;
2535 unsigned tclk_pre, tclk_post;
2536 unsigned ths_prepare, ths_prepare_ths_zero, ths_zero;
2537 unsigned ths_trail, ths_exit;
2538 unsigned ddr_clk_pre, ddr_clk_post;
2539 unsigned enter_hs_mode_lat, exit_hs_mode_lat;
2540 unsigned ths_eot;
2541 u32 r;
2542
2543 r = dsi_read_reg(DSI_DSIPHY_CFG0);
2544 ths_prepare = FLD_GET(r, 31, 24);
2545 ths_prepare_ths_zero = FLD_GET(r, 23, 16);
2546 ths_zero = ths_prepare_ths_zero - ths_prepare;
2547 ths_trail = FLD_GET(r, 15, 8);
2548 ths_exit = FLD_GET(r, 7, 0);
2549
2550 r = dsi_read_reg(DSI_DSIPHY_CFG1);
2551 tlpx = FLD_GET(r, 22, 16) * 2;
2552 tclk_trail = FLD_GET(r, 15, 8);
2553 tclk_zero = FLD_GET(r, 7, 0);
2554
2555 r = dsi_read_reg(DSI_DSIPHY_CFG2);
2556 tclk_prepare = FLD_GET(r, 7, 0);
2557
2558 /* min 8*UI */
2559 tclk_pre = 20;
2560 /* min 60ns + 52*UI */
2561 tclk_post = ns2ddr(60) + 26;
2562
2563 /* ths_eot is 2 for 2 datalanes and 4 for 1 datalane */
2564 if (dssdev->phy.dsi.data1_lane != 0 &&
2565 dssdev->phy.dsi.data2_lane != 0)
2566 ths_eot = 2;
2567 else
2568 ths_eot = 4;
2569
2570 ddr_clk_pre = DIV_ROUND_UP(tclk_pre + tlpx + tclk_zero + tclk_prepare,
2571 4);
2572 ddr_clk_post = DIV_ROUND_UP(tclk_post + ths_trail, 4) + ths_eot;
2573
2574 BUG_ON(ddr_clk_pre == 0 || ddr_clk_pre > 255);
2575 BUG_ON(ddr_clk_post == 0 || ddr_clk_post > 255);
2576
2577 r = dsi_read_reg(DSI_CLK_TIMING);
2578 r = FLD_MOD(r, ddr_clk_pre, 15, 8);
2579 r = FLD_MOD(r, ddr_clk_post, 7, 0);
2580 dsi_write_reg(DSI_CLK_TIMING, r);
2581
2582 DSSDBG("ddr_clk_pre %u, ddr_clk_post %u\n",
2583 ddr_clk_pre,
2584 ddr_clk_post);
2585
2586 enter_hs_mode_lat = 1 + DIV_ROUND_UP(tlpx, 4) +
2587 DIV_ROUND_UP(ths_prepare, 4) +
2588 DIV_ROUND_UP(ths_zero + 3, 4);
2589
2590 exit_hs_mode_lat = DIV_ROUND_UP(ths_trail + ths_exit, 4) + 1 + ths_eot;
2591
2592 r = FLD_VAL(enter_hs_mode_lat, 31, 16) |
2593 FLD_VAL(exit_hs_mode_lat, 15, 0);
2594 dsi_write_reg(DSI_VM_TIMING7, r);
2595
2596 DSSDBG("enter_hs_mode_lat %u, exit_hs_mode_lat %u\n",
2597 enter_hs_mode_lat, exit_hs_mode_lat);
2598 }
2599
2600
2601 #define DSI_DECL_VARS \
2602 int __dsi_cb = 0; u32 __dsi_cv = 0;
2603
2604 #define DSI_FLUSH(ch) \
2605 if (__dsi_cb > 0) { \
2606 /*DSSDBG("sending long packet %#010x\n", __dsi_cv);*/ \
2607 dsi_write_reg(DSI_VC_LONG_PACKET_PAYLOAD(ch), __dsi_cv); \
2608 __dsi_cb = __dsi_cv = 0; \
2609 }
2610
2611 #define DSI_PUSH(ch, data) \
2612 do { \
2613 __dsi_cv |= (data) << (__dsi_cb * 8); \
2614 /*DSSDBG("cv = %#010x, cb = %d\n", __dsi_cv, __dsi_cb);*/ \
2615 if (++__dsi_cb > 3) \
2616 DSI_FLUSH(ch); \
2617 } while (0)
2618
2619 static int dsi_update_screen_l4(struct omap_dss_device *dssdev,
2620 int x, int y, int w, int h)
2621 {
2622 /* Note: supports only 24bit colors in 32bit container */
2623 int first = 1;
2624 int fifo_stalls = 0;
2625 int max_dsi_packet_size;
2626 int max_data_per_packet;
2627 int max_pixels_per_packet;
2628 int pixels_left;
2629 int bytespp = dssdev->ctrl.pixel_size / 8;
2630 int scr_width;
2631 u32 __iomem *data;
2632 int start_offset;
2633 int horiz_inc;
2634 int current_x;
2635 struct omap_overlay *ovl;
2636
2637 debug_irq = 0;
2638
2639 DSSDBG("dsi_update_screen_l4 (%d,%d %dx%d)\n",
2640 x, y, w, h);
2641
2642 ovl = dssdev->manager->overlays[0];
2643
2644 if (ovl->info.color_mode != OMAP_DSS_COLOR_RGB24U)
2645 return -EINVAL;
2646
2647 if (dssdev->ctrl.pixel_size != 24)
2648 return -EINVAL;
2649
2650 scr_width = ovl->info.screen_width;
2651 data = ovl->info.vaddr;
2652
2653 start_offset = scr_width * y + x;
2654 horiz_inc = scr_width - w;
2655 current_x = x;
2656
2657 /* We need header(4) + DCSCMD(1) + pixels(numpix*bytespp) bytes
2658 * in fifo */
2659
2660 /* When using CPU, max long packet size is TX buffer size */
2661 max_dsi_packet_size = dsi.vc[0].fifo_size * 32 * 4;
2662
2663 /* we seem to get better perf if we divide the tx fifo to half,
2664 and while the other half is being sent, we fill the other half
2665 max_dsi_packet_size /= 2; */
2666
2667 max_data_per_packet = max_dsi_packet_size - 4 - 1;
2668
2669 max_pixels_per_packet = max_data_per_packet / bytespp;
2670
2671 DSSDBG("max_pixels_per_packet %d\n", max_pixels_per_packet);
2672
2673 pixels_left = w * h;
2674
2675 DSSDBG("total pixels %d\n", pixels_left);
2676
2677 data += start_offset;
2678
2679 while (pixels_left > 0) {
2680 /* 0x2c = write_memory_start */
2681 /* 0x3c = write_memory_continue */
2682 u8 dcs_cmd = first ? 0x2c : 0x3c;
2683 int pixels;
2684 DSI_DECL_VARS;
2685 first = 0;
2686
2687 #if 1
2688 /* using fifo not empty */
2689 /* TX_FIFO_NOT_EMPTY */
2690 while (FLD_GET(dsi_read_reg(DSI_VC_CTRL(0)), 5, 5)) {
2691 fifo_stalls++;
2692 if (fifo_stalls > 0xfffff) {
2693 DSSERR("fifo stalls overflow, pixels left %d\n",
2694 pixels_left);
2695 dsi_if_enable(0);
2696 return -EIO;
2697 }
2698 udelay(1);
2699 }
2700 #elif 1
2701 /* using fifo emptiness */
2702 while ((REG_GET(DSI_TX_FIFO_VC_EMPTINESS, 7, 0)+1)*4 <
2703 max_dsi_packet_size) {
2704 fifo_stalls++;
2705 if (fifo_stalls > 0xfffff) {
2706 DSSERR("fifo stalls overflow, pixels left %d\n",
2707 pixels_left);
2708 dsi_if_enable(0);
2709 return -EIO;
2710 }
2711 }
2712 #else
2713 while ((REG_GET(DSI_TX_FIFO_VC_EMPTINESS, 7, 0)+1)*4 == 0) {
2714 fifo_stalls++;
2715 if (fifo_stalls > 0xfffff) {
2716 DSSERR("fifo stalls overflow, pixels left %d\n",
2717 pixels_left);
2718 dsi_if_enable(0);
2719 return -EIO;
2720 }
2721 }
2722 #endif
2723 pixels = min(max_pixels_per_packet, pixels_left);
2724
2725 pixels_left -= pixels;
2726
2727 dsi_vc_write_long_header(0, DSI_DT_DCS_LONG_WRITE,
2728 1 + pixels * bytespp, 0);
2729
2730 DSI_PUSH(0, dcs_cmd);
2731
2732 while (pixels-- > 0) {
2733 u32 pix = __raw_readl(data++);
2734
2735 DSI_PUSH(0, (pix >> 16) & 0xff);
2736 DSI_PUSH(0, (pix >> 8) & 0xff);
2737 DSI_PUSH(0, (pix >> 0) & 0xff);
2738
2739 current_x++;
2740 if (current_x == x+w) {
2741 current_x = x;
2742 data += horiz_inc;
2743 }
2744 }
2745
2746 DSI_FLUSH(0);
2747 }
2748
2749 return 0;
2750 }
2751
2752 static void dsi_update_screen_dispc(struct omap_dss_device *dssdev,
2753 u16 x, u16 y, u16 w, u16 h)
2754 {
2755 unsigned bytespp;
2756 unsigned bytespl;
2757 unsigned bytespf;
2758 unsigned total_len;
2759 unsigned packet_payload;
2760 unsigned packet_len;
2761 u32 l;
2762 const unsigned channel = dsi.update_channel;
2763 /* line buffer is 1024 x 24bits */
2764 /* XXX: for some reason using full buffer size causes considerable TX
2765 * slowdown with update sizes that fill the whole buffer */
2766 const unsigned line_buf_size = 1023 * 3;
2767
2768 DSSDBG("dsi_update_screen_dispc(%d,%d %dx%d)\n",
2769 x, y, w, h);
2770
2771 dsi_vc_config_vp(channel);
2772
2773 bytespp = dssdev->ctrl.pixel_size / 8;
2774 bytespl = w * bytespp;
2775 bytespf = bytespl * h;
2776
2777 /* NOTE: packet_payload has to be equal to N * bytespl, where N is
2778 * number of lines in a packet. See errata about VP_CLK_RATIO */
2779
2780 if (bytespf < line_buf_size)
2781 packet_payload = bytespf;
2782 else
2783 packet_payload = (line_buf_size) / bytespl * bytespl;
2784
2785 packet_len = packet_payload + 1; /* 1 byte for DCS cmd */
2786 total_len = (bytespf / packet_payload) * packet_len;
2787
2788 if (bytespf % packet_payload)
2789 total_len += (bytespf % packet_payload) + 1;
2790
2791 l = FLD_VAL(total_len, 23, 0); /* TE_SIZE */
2792 dsi_write_reg(DSI_VC_TE(channel), l);
2793
2794 dsi_vc_write_long_header(channel, DSI_DT_DCS_LONG_WRITE, packet_len, 0);
2795
2796 if (dsi.te_enabled)
2797 l = FLD_MOD(l, 1, 30, 30); /* TE_EN */
2798 else
2799 l = FLD_MOD(l, 1, 31, 31); /* TE_START */
2800 dsi_write_reg(DSI_VC_TE(channel), l);
2801
2802 /* We put SIDLEMODE to no-idle for the duration of the transfer,
2803 * because DSS interrupts are not capable of waking up the CPU and the
2804 * framedone interrupt could be delayed for quite a long time. I think
2805 * the same goes for any DSS interrupts, but for some reason I have not
2806 * seen the problem anywhere else than here.
2807 */
2808 dispc_disable_sidle();
2809
2810 dsi_perf_mark_start();
2811
2812 schedule_delayed_work(&dsi.framedone_timeout_work,
2813 msecs_to_jiffies(250));
2814
2815 dss_start_update(dssdev);
2816
2817 if (dsi.te_enabled) {
2818 /* disable LP_RX_TO, so that we can receive TE. Time to wait
2819 * for TE is longer than the timer allows */
2820 REG_FLD_MOD(DSI_TIMING2, 0, 15, 15); /* LP_RX_TO */
2821
2822 dsi_vc_send_bta(channel);
2823
2824 #ifdef DSI_CATCH_MISSING_TE
2825 mod_timer(&dsi.te_timer, jiffies + msecs_to_jiffies(250));
2826 #endif
2827 }
2828 }
2829
2830 #ifdef DSI_CATCH_MISSING_TE
2831 static void dsi_te_timeout(unsigned long arg)
2832 {
2833 DSSERR("TE not received for 250ms!\n");
2834 }
2835 #endif
2836
2837 static void dsi_framedone_timeout_work_callback(struct work_struct *work)
2838 {
2839 int r;
2840 const int channel = dsi.update_channel;
2841
2842 DSSERR("Framedone not received for 250ms!\n");
2843
2844 /* SIDLEMODE back to smart-idle */
2845 dispc_enable_sidle();
2846
2847 if (dsi.te_enabled) {
2848 /* enable LP_RX_TO again after the TE */
2849 REG_FLD_MOD(DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */
2850 }
2851
2852 /* Send BTA after the frame. We need this for the TE to work, as TE
2853 * trigger is only sent for BTAs without preceding packet. Thus we need
2854 * to BTA after the pixel packets so that next BTA will cause TE
2855 * trigger.
2856 *
2857 * This is not needed when TE is not in use, but we do it anyway to
2858 * make sure that the transfer has been completed. It would be more
2859 * optimal, but more complex, to wait only just before starting next
2860 * transfer. */
2861 r = dsi_vc_send_bta_sync(channel);
2862 if (r)
2863 DSSERR("BTA after framedone failed\n");
2864
2865 /* RX_FIFO_NOT_EMPTY */
2866 if (REG_GET(DSI_VC_CTRL(channel), 20, 20)) {
2867 DSSERR("Received error during frame transfer:\n");
2868 dsi_vc_flush_receive_data(channel);
2869 }
2870
2871 dsi.framedone_callback(-ETIMEDOUT, dsi.framedone_data);
2872 }
2873
2874 static void dsi_framedone_irq_callback(void *data, u32 mask)
2875 {
2876 /* Note: We get FRAMEDONE when DISPC has finished sending pixels and
2877 * turns itself off. However, DSI still has the pixels in its buffers,
2878 * and is sending the data.
2879 */
2880
2881 /* SIDLEMODE back to smart-idle */
2882 dispc_enable_sidle();
2883
2884 schedule_work(&dsi.framedone_work);
2885 }
2886
2887 static void dsi_handle_framedone(void)
2888 {
2889 int r;
2890 const int channel = dsi.update_channel;
2891
2892 DSSDBG("FRAMEDONE\n");
2893
2894 if (dsi.te_enabled) {
2895 /* enable LP_RX_TO again after the TE */
2896 REG_FLD_MOD(DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */
2897 }
2898
2899 /* Send BTA after the frame. We need this for the TE to work, as TE
2900 * trigger is only sent for BTAs without preceding packet. Thus we need
2901 * to BTA after the pixel packets so that next BTA will cause TE
2902 * trigger.
2903 *
2904 * This is not needed when TE is not in use, but we do it anyway to
2905 * make sure that the transfer has been completed. It would be more
2906 * optimal, but more complex, to wait only just before starting next
2907 * transfer. */
2908 r = dsi_vc_send_bta_sync(channel);
2909 if (r)
2910 DSSERR("BTA after framedone failed\n");
2911
2912 /* RX_FIFO_NOT_EMPTY */
2913 if (REG_GET(DSI_VC_CTRL(channel), 20, 20)) {
2914 DSSERR("Received error during frame transfer:\n");
2915 dsi_vc_flush_receive_data(channel);
2916 }
2917
2918 #ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
2919 dispc_fake_vsync_irq();
2920 #endif
2921 }
2922
2923 static void dsi_framedone_work_callback(struct work_struct *work)
2924 {
2925 DSSDBGF();
2926
2927 cancel_delayed_work_sync(&dsi.framedone_timeout_work);
2928
2929 dsi_handle_framedone();
2930
2931 dsi_perf_show("DISPC");
2932
2933 dsi.framedone_callback(0, dsi.framedone_data);
2934 }
2935
2936 int omap_dsi_prepare_update(struct omap_dss_device *dssdev,
2937 u16 *x, u16 *y, u16 *w, u16 *h)
2938 {
2939 u16 dw, dh;
2940
2941 dssdev->driver->get_resolution(dssdev, &dw, &dh);
2942
2943 if (*x > dw || *y > dh)
2944 return -EINVAL;
2945
2946 if (*x + *w > dw)
2947 return -EINVAL;
2948
2949 if (*y + *h > dh)
2950 return -EINVAL;
2951
2952 if (*w == 1)
2953 return -EINVAL;
2954
2955 if (*w == 0 || *h == 0)
2956 return -EINVAL;
2957
2958 dsi_perf_mark_setup();
2959
2960 if (dssdev->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) {
2961 dss_setup_partial_planes(dssdev, x, y, w, h);
2962 dispc_set_lcd_size(*w, *h);
2963 }
2964
2965 return 0;
2966 }
2967 EXPORT_SYMBOL(omap_dsi_prepare_update);
2968
2969 int omap_dsi_update(struct omap_dss_device *dssdev,
2970 int channel,
2971 u16 x, u16 y, u16 w, u16 h,
2972 void (*callback)(int, void *), void *data)
2973 {
2974 dsi.update_channel = channel;
2975
2976 if (dssdev->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) {
2977 dsi.framedone_callback = callback;
2978 dsi.framedone_data = data;
2979
2980 dsi.update_region.x = x;
2981 dsi.update_region.y = y;
2982 dsi.update_region.w = w;
2983 dsi.update_region.h = h;
2984 dsi.update_region.device = dssdev;
2985
2986 dsi_update_screen_dispc(dssdev, x, y, w, h);
2987 } else {
2988 dsi_update_screen_l4(dssdev, x, y, w, h);
2989 dsi_perf_show("L4");
2990 callback(0, data);
2991 }
2992
2993 return 0;
2994 }
2995 EXPORT_SYMBOL(omap_dsi_update);
2996
2997 /* Display funcs */
2998
2999 static int dsi_display_init_dispc(struct omap_dss_device *dssdev)
3000 {
3001 int r;
3002
3003 r = omap_dispc_register_isr(dsi_framedone_irq_callback, NULL,
3004 DISPC_IRQ_FRAMEDONE);
3005 if (r) {
3006 DSSERR("can't get FRAMEDONE irq\n");
3007 return r;
3008 }
3009
3010 dispc_set_lcd_display_type(OMAP_DSS_LCD_DISPLAY_TFT);
3011
3012 dispc_set_parallel_interface_mode(OMAP_DSS_PARALLELMODE_DSI);
3013 dispc_enable_fifohandcheck(1);
3014
3015 dispc_set_tft_data_lines(dssdev->ctrl.pixel_size);
3016
3017 {
3018 struct omap_video_timings timings = {
3019 .hsw = 1,
3020 .hfp = 1,
3021 .hbp = 1,
3022 .vsw = 1,
3023 .vfp = 0,
3024 .vbp = 0,
3025 };
3026
3027 dispc_set_lcd_timings(&timings);
3028 }
3029
3030 return 0;
3031 }
3032
3033 static void dsi_display_uninit_dispc(struct omap_dss_device *dssdev)
3034 {
3035 omap_dispc_unregister_isr(dsi_framedone_irq_callback, NULL,
3036 DISPC_IRQ_FRAMEDONE);
3037 }
3038
3039 static int dsi_configure_dsi_clocks(struct omap_dss_device *dssdev)
3040 {
3041 struct dsi_clock_info cinfo;
3042 int r;
3043
3044 /* we always use DSS2_FCK as input clock */
3045 cinfo.use_dss2_fck = true;
3046 cinfo.regn = dssdev->phy.dsi.div.regn;
3047 cinfo.regm = dssdev->phy.dsi.div.regm;
3048 cinfo.regm3 = dssdev->phy.dsi.div.regm3;
3049 cinfo.regm4 = dssdev->phy.dsi.div.regm4;
3050 r = dsi_calc_clock_rates(&cinfo);
3051 if (r)
3052 return r;
3053
3054 r = dsi_pll_set_clock_div(&cinfo);
3055 if (r) {
3056 DSSERR("Failed to set dsi clocks\n");
3057 return r;
3058 }
3059
3060 return 0;
3061 }
3062
3063 static int dsi_configure_dispc_clocks(struct omap_dss_device *dssdev)
3064 {
3065 struct dispc_clock_info dispc_cinfo;
3066 int r;
3067 unsigned long long fck;
3068
3069 fck = dsi_get_dsi1_pll_rate();
3070
3071 dispc_cinfo.lck_div = dssdev->phy.dsi.div.lck_div;
3072 dispc_cinfo.pck_div = dssdev->phy.dsi.div.pck_div;
3073
3074 r = dispc_calc_clock_rates(fck, &dispc_cinfo);
3075 if (r) {
3076 DSSERR("Failed to calc dispc clocks\n");
3077 return r;
3078 }
3079
3080 r = dispc_set_clock_div(&dispc_cinfo);
3081 if (r) {
3082 DSSERR("Failed to set dispc clocks\n");
3083 return r;
3084 }
3085
3086 return 0;
3087 }
3088
3089 static int dsi_display_init_dsi(struct omap_dss_device *dssdev)
3090 {
3091 int r;
3092
3093 _dsi_print_reset_status();
3094
3095 r = dsi_pll_init(dssdev, true, true);
3096 if (r)
3097 goto err0;
3098
3099 r = dsi_configure_dsi_clocks(dssdev);
3100 if (r)
3101 goto err1;
3102
3103 dss_select_dispc_clk_source(DSS_SRC_DSI1_PLL_FCLK);
3104 dss_select_dsi_clk_source(DSS_SRC_DSI2_PLL_FCLK);
3105
3106 DSSDBG("PLL OK\n");
3107
3108 r = dsi_configure_dispc_clocks(dssdev);
3109 if (r)
3110 goto err2;
3111
3112 r = dsi_complexio_init(dssdev);
3113 if (r)
3114 goto err2;
3115
3116 _dsi_print_reset_status();
3117
3118 dsi_proto_timings(dssdev);
3119 dsi_set_lp_clk_divisor(dssdev);
3120
3121 if (1)
3122 _dsi_print_reset_status();
3123
3124 r = dsi_proto_config(dssdev);
3125 if (r)
3126 goto err3;
3127
3128 /* enable interface */
3129 dsi_vc_enable(0, 1);
3130 dsi_vc_enable(1, 1);
3131 dsi_vc_enable(2, 1);
3132 dsi_vc_enable(3, 1);
3133 dsi_if_enable(1);
3134 dsi_force_tx_stop_mode_io();
3135
3136 return 0;
3137 err3:
3138 dsi_complexio_uninit();
3139 err2:
3140 dss_select_dispc_clk_source(DSS_SRC_DSS1_ALWON_FCLK);
3141 dss_select_dsi_clk_source(DSS_SRC_DSS1_ALWON_FCLK);
3142 err1:
3143 dsi_pll_uninit();
3144 err0:
3145 return r;
3146 }
3147
3148 static void dsi_display_uninit_dsi(struct omap_dss_device *dssdev)
3149 {
3150 dss_select_dispc_clk_source(DSS_SRC_DSS1_ALWON_FCLK);
3151 dss_select_dsi_clk_source(DSS_SRC_DSS1_ALWON_FCLK);
3152 dsi_complexio_uninit();
3153 dsi_pll_uninit();
3154 }
3155
3156 static int dsi_core_init(void)
3157 {
3158 /* Autoidle */
3159 REG_FLD_MOD(DSI_SYSCONFIG, 1, 0, 0);
3160
3161 /* ENWAKEUP */
3162 REG_FLD_MOD(DSI_SYSCONFIG, 1, 2, 2);
3163
3164 /* SIDLEMODE smart-idle */
3165 REG_FLD_MOD(DSI_SYSCONFIG, 2, 4, 3);
3166
3167 _dsi_initialize_irq();
3168
3169 return 0;
3170 }
3171
3172 int omapdss_dsi_display_enable(struct omap_dss_device *dssdev)
3173 {
3174 int r = 0;
3175
3176 DSSDBG("dsi_display_enable\n");
3177
3178 WARN_ON(!dsi_bus_is_locked());
3179
3180 mutex_lock(&dsi.lock);
3181
3182 r = omap_dss_start_device(dssdev);
3183 if (r) {
3184 DSSERR("failed to start device\n");
3185 goto err0;
3186 }
3187
3188 enable_clocks(1);
3189 dsi_enable_pll_clock(1);
3190
3191 r = _dsi_reset();
3192 if (r)
3193 goto err1;
3194
3195 dsi_core_init();
3196
3197 r = dsi_display_init_dispc(dssdev);
3198 if (r)
3199 goto err1;
3200
3201 r = dsi_display_init_dsi(dssdev);
3202 if (r)
3203 goto err2;
3204
3205 mutex_unlock(&dsi.lock);
3206
3207 return 0;
3208
3209 err2:
3210 dsi_display_uninit_dispc(dssdev);
3211 err1:
3212 enable_clocks(0);
3213 dsi_enable_pll_clock(0);
3214 omap_dss_stop_device(dssdev);
3215 err0:
3216 mutex_unlock(&dsi.lock);
3217 DSSDBG("dsi_display_enable FAILED\n");
3218 return r;
3219 }
3220 EXPORT_SYMBOL(omapdss_dsi_display_enable);
3221
3222 void omapdss_dsi_display_disable(struct omap_dss_device *dssdev)
3223 {
3224 DSSDBG("dsi_display_disable\n");
3225
3226 WARN_ON(!dsi_bus_is_locked());
3227
3228 mutex_lock(&dsi.lock);
3229
3230 dsi_display_uninit_dispc(dssdev);
3231
3232 dsi_display_uninit_dsi(dssdev);
3233
3234 enable_clocks(0);
3235 dsi_enable_pll_clock(0);
3236
3237 omap_dss_stop_device(dssdev);
3238
3239 mutex_unlock(&dsi.lock);
3240 }
3241 EXPORT_SYMBOL(omapdss_dsi_display_disable);
3242
3243 int omapdss_dsi_enable_te(struct omap_dss_device *dssdev, bool enable)
3244 {
3245 dsi.te_enabled = enable;
3246 return 0;
3247 }
3248 EXPORT_SYMBOL(omapdss_dsi_enable_te);
3249
3250 void dsi_get_overlay_fifo_thresholds(enum omap_plane plane,
3251 u32 fifo_size, enum omap_burst_size *burst_size,
3252 u32 *fifo_low, u32 *fifo_high)
3253 {
3254 unsigned burst_size_bytes;
3255
3256 *burst_size = OMAP_DSS_BURST_16x32;
3257 burst_size_bytes = 16 * 32 / 8;
3258
3259 *fifo_high = fifo_size - burst_size_bytes;
3260 *fifo_low = fifo_size - burst_size_bytes * 8;
3261 }
3262
3263 int dsi_init_display(struct omap_dss_device *dssdev)
3264 {
3265 DSSDBG("DSI init\n");
3266
3267 /* XXX these should be figured out dynamically */
3268 dssdev->caps = OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE |
3269 OMAP_DSS_DISPLAY_CAP_TEAR_ELIM;
3270
3271 dsi.vc[0].dssdev = dssdev;
3272 dsi.vc[1].dssdev = dssdev;
3273
3274 return 0;
3275 }
3276
3277 int dsi_init(struct platform_device *pdev)
3278 {
3279 u32 rev;
3280 int r;
3281
3282 spin_lock_init(&dsi.errors_lock);
3283 dsi.errors = 0;
3284
3285 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3286 spin_lock_init(&dsi.irq_stats_lock);
3287 dsi.irq_stats.last_reset = jiffies;
3288 #endif
3289
3290 init_completion(&dsi.bta_completion);
3291
3292 mutex_init(&dsi.lock);
3293 sema_init(&dsi.bus_lock, 1);
3294
3295 INIT_WORK(&dsi.framedone_work, dsi_framedone_work_callback);
3296 INIT_DELAYED_WORK_DEFERRABLE(&dsi.framedone_timeout_work,
3297 dsi_framedone_timeout_work_callback);
3298
3299 #ifdef DSI_CATCH_MISSING_TE
3300 init_timer(&dsi.te_timer);
3301 dsi.te_timer.function = dsi_te_timeout;
3302 dsi.te_timer.data = 0;
3303 #endif
3304 dsi.base = ioremap(DSI_BASE, DSI_SZ_REGS);
3305 if (!dsi.base) {
3306 DSSERR("can't ioremap DSI\n");
3307 r = -ENOMEM;
3308 goto err1;
3309 }
3310
3311 dsi.vdds_dsi_reg = dss_get_vdds_dsi();
3312 if (IS_ERR(dsi.vdds_dsi_reg)) {
3313 iounmap(dsi.base);
3314 DSSERR("can't get VDDS_DSI regulator\n");
3315 r = PTR_ERR(dsi.vdds_dsi_reg);
3316 goto err2;
3317 }
3318
3319 enable_clocks(1);
3320
3321 rev = dsi_read_reg(DSI_REVISION);
3322 printk(KERN_INFO "OMAP DSI rev %d.%d\n",
3323 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
3324
3325 enable_clocks(0);
3326
3327 return 0;
3328 err2:
3329 iounmap(dsi.base);
3330 err1:
3331 return r;
3332 }
3333
3334 void dsi_exit(void)
3335 {
3336 iounmap(dsi.base);
3337
3338 DSSDBG("omap_dsi_exit\n");
3339 }
3340