drivers/video/omap2/dss/dss.h

   1 /*
   2  * linux/drivers/video/omap2/dss/dss.h
   3  *
   4  * Copyright (C) 2009 Nokia Corporation
   5  * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
   6  *
   7  * Some code and ideas taken from drivers/video/omap/ driver
   8  * by Imre Deak.
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms of the GNU General Public License version 2 as published by
  12  * the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but WITHOUT
  15  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  17  * more details.
  18  *
  19  * You should have received a copy of the GNU General Public License along with
  20  * this program.  If not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #ifndef __OMAP2_DSS_H
  24 #define __OMAP2_DSS_H
  25
  26 #ifdef CONFIG_OMAP2_DSS_DEBUG_SUPPORT
  27 #define DEBUG
  28 #endif
  29
  30 #ifdef DEBUG
  31 extern unsigned int dss_debug;
  32 #ifdef DSS_SUBSYS_NAME
  33 #define DSSDBG(format, ...) \
  34         if (dss_debug) \
  35                 printk(KERN_DEBUG "omapdss " DSS_SUBSYS_NAME ": " format, \
  36                 ## __VA_ARGS__)
  37 #else
  38 #define DSSDBG(format, ...) \
  39         if (dss_debug) \
  40                 printk(KERN_DEBUG "omapdss: " format, ## __VA_ARGS__)
  41 #endif
  42
  43 #ifdef DSS_SUBSYS_NAME
  44 #define DSSDBGF(format, ...) \
  45         if (dss_debug) \
  46                 printk(KERN_DEBUG "omapdss " DSS_SUBSYS_NAME \
  47                                 ": %s(" format ")\n", \
  48                                 __func__, \
  49                                 ## __VA_ARGS__)
  50 #else
  51 #define DSSDBGF(format, ...) \
  52         if (dss_debug) \
  53                 printk(KERN_DEBUG "omapdss: " \
  54                                 ": %s(" format ")\n", \
  55                                 __func__, \
  56                                 ## __VA_ARGS__)
  57 #endif
  58
  59 #else /* DEBUG */
  60 #define DSSDBG(format, ...)
  61 #define DSSDBGF(format, ...)
  62 #endif
  63
  64
  65 #ifdef DSS_SUBSYS_NAME
  66 #define DSSERR(format, ...) \
  67         printk(KERN_ERR "omapdss " DSS_SUBSYS_NAME " error: " format, \
  68         ## __VA_ARGS__)
  69 #else
  70 #define DSSERR(format, ...) \
  71         printk(KERN_ERR "omapdss error: " format, ## __VA_ARGS__)
  72 #endif
  73
  74 #ifdef DSS_SUBSYS_NAME
  75 #define DSSINFO(format, ...) \
  76         printk(KERN_INFO "omapdss " DSS_SUBSYS_NAME ": " format, \
  77         ## __VA_ARGS__)
  78 #else
  79 #define DSSINFO(format, ...) \
  80         printk(KERN_INFO "omapdss: " format, ## __VA_ARGS__)
  81 #endif
  82
  83 #ifdef DSS_SUBSYS_NAME
  84 #define DSSWARN(format, ...) \
  85         printk(KERN_WARNING "omapdss " DSS_SUBSYS_NAME ": " format, \
  86         ## __VA_ARGS__)
  87 #else
  88 #define DSSWARN(format, ...) \
  89         printk(KERN_WARNING "omapdss: " format, ## __VA_ARGS__)
  90 #endif
  91
  92 /* OMAP TRM gives bitfields as start:end, where start is the higher bit
  93    number. For example 7:0 */
  94 #define FLD_MASK(start, end)    (((1 << ((start) - (end) + 1)) - 1) << (end))
  95 #define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end))
  96 #define FLD_GET(val, start, end) (((val) & FLD_MASK(start, end)) >> (end))
  97 #define FLD_MOD(orig, val, start, end) \
  98         (((orig) & ~FLD_MASK(start, end)) | FLD_VAL(val, start, end))
  99
 100 #define DISPC_MAX_FCK 173000000
 101
 102 enum omap_burst_size {
 103         OMAP_DSS_BURST_4x32 = 0,
 104         OMAP_DSS_BURST_8x32 = 1,
 105         OMAP_DSS_BURST_16x32 = 2,
 106 };
 107
 108 enum omap_parallel_interface_mode {
 109         OMAP_DSS_PARALLELMODE_BYPASS,           /* MIPI DPI */
 110         OMAP_DSS_PARALLELMODE_RFBI,             /* MIPI DBI */
 111         OMAP_DSS_PARALLELMODE_DSI,
 112 };
 113
 114 enum dss_clock {
 115         DSS_CLK_ICK     = 1 << 0,
 116         DSS_CLK_FCK1    = 1 << 1,
 117         DSS_CLK_FCK2    = 1 << 2,
 118         DSS_CLK_54M     = 1 << 3,
 119         DSS_CLK_96M     = 1 << 4,
 120 };
 121
 122 enum dss_clk_source {
 123         DSS_SRC_DSI1_PLL_FCLK,
 124         DSS_SRC_DSI2_PLL_FCLK,
 125         DSS_SRC_DSS1_ALWON_FCLK,
 126 };
 127
 128 struct dss_clock_info {
 129         /* rates that we get with dividers below */
 130         unsigned long fck;
 131
 132         /* dividers */
 133         u16 fck_div;
 134 };
 135
 136 struct dispc_clock_info {
 137         /* rates that we get with dividers below */
 138         unsigned long lck;
 139         unsigned long pck;
 140
 141         /* dividers */
 142         u16 lck_div;
 143         u16 pck_div;
 144 };
 145
 146 struct dsi_clock_info {
 147         /* rates that we get with dividers below */
 148         unsigned long fint;
 149         unsigned long clkin4ddr;
 150         unsigned long clkin;
 151         unsigned long dsi1_pll_fclk;
 152         unsigned long dsi2_pll_fclk;
 153
 154         unsigned long lp_clk;
 155
 156         /* dividers */
 157         u16 regn;
 158         u16 regm;
 159         u16 regm3;
 160         u16 regm4;
 161
 162         u16 lp_clk_div;
 163
 164         u8 highfreq;
 165         bool use_dss2_fck;
 166 };
 167
 168 struct seq_file;
 169 struct platform_device;
 170
 171 /* core */
 172 void dss_clk_enable(enum dss_clock clks);
 173 void dss_clk_disable(enum dss_clock clks);
 174 unsigned long dss_clk_get_rate(enum dss_clock clk);
 175 int dss_need_ctx_restore(void);
 176 void dss_dump_clocks(struct seq_file *s);
 177 struct bus_type *dss_get_bus(void);
 178 struct regulator *dss_get_vdds_dsi(void);
 179 struct regulator *dss_get_vdds_sdi(void);
 180 struct regulator *dss_get_vdda_dac(void);
 181
 182 /* display */
 183 int dss_suspend_all_devices(void);
 184 int dss_resume_all_devices(void);
 185 void dss_disable_all_devices(void);
 186
 187 void dss_init_device(struct platform_device *pdev,
 188                 struct omap_dss_device *dssdev);
 189 void dss_uninit_device(struct platform_device *pdev,
 190                 struct omap_dss_device *dssdev);
 191 bool dss_use_replication(struct omap_dss_device *dssdev,
 192                 enum omap_color_mode mode);
 193 void default_get_overlay_fifo_thresholds(enum omap_plane plane,
 194                 u32 fifo_size, enum omap_burst_size *burst_size,
 195                 u32 *fifo_low, u32 *fifo_high);
 196
 197 /* manager */
 198 int dss_init_overlay_managers(struct platform_device *pdev);
 199 void dss_uninit_overlay_managers(struct platform_device *pdev);
 200 int dss_mgr_wait_for_go_ovl(struct omap_overlay *ovl);
 201 void dss_setup_partial_planes(struct omap_dss_device *dssdev,
 202                                 u16 *x, u16 *y, u16 *w, u16 *h);
 203 void dss_start_update(struct omap_dss_device *dssdev);
 204
 205 /* overlay */
 206 void dss_init_overlays(struct platform_device *pdev);
 207 void dss_uninit_overlays(struct platform_device *pdev);
 208 int dss_check_overlay(struct omap_overlay *ovl, struct omap_dss_device *dssdev);
 209 void dss_overlay_setup_dispc_manager(struct omap_overlay_manager *mgr);
 210 #ifdef L4_EXAMPLE
 211 void dss_overlay_setup_l4_manager(struct omap_overlay_manager *mgr);
 212 #endif
 213 void dss_recheck_connections(struct omap_dss_device *dssdev, bool force);
 214
 215 /* DSS */
 216 int dss_init(bool skip_init);
 217 void dss_exit(void);
 218
 219 void dss_save_context(void);
 220 void dss_restore_context(void);
 221
 222 void dss_dump_regs(struct seq_file *s);
 223
 224 void dss_sdi_init(u8 datapairs);
 225 int dss_sdi_enable(void);
 226 void dss_sdi_disable(void);
 227
 228 void dss_select_dispc_clk_source(enum dss_clk_source clk_src);
 229 void dss_select_dsi_clk_source(enum dss_clk_source clk_src);
 230 enum dss_clk_source dss_get_dispc_clk_source(void);
 231 enum dss_clk_source dss_get_dsi_clk_source(void);
 232
 233 void dss_set_venc_output(enum omap_dss_venc_type type);
 234 void dss_set_dac_pwrdn_bgz(bool enable);
 235
 236 unsigned long dss_get_dpll4_rate(void);
 237 int dss_calc_clock_rates(struct dss_clock_info *cinfo);
 238 int dss_set_clock_div(struct dss_clock_info *cinfo);
 239 int dss_get_clock_div(struct dss_clock_info *cinfo);
 240 int dss_calc_clock_div(bool is_tft, unsigned long req_pck,
 241                 struct dss_clock_info *dss_cinfo,
 242                 struct dispc_clock_info *dispc_cinfo);
 243
 244 /* SDI */
 245 int sdi_init(bool skip_init);
 246 void sdi_exit(void);
 247 int sdi_init_display(struct omap_dss_device *display);
 248
 249 /* DSI */
 250 int dsi_init(struct platform_device *pdev);
 251 void dsi_exit(void);
 252
 253 void dsi_dump_clocks(struct seq_file *s);
 254 void dsi_dump_irqs(struct seq_file *s);
 255 void dsi_dump_regs(struct seq_file *s);
 256
 257 void dsi_save_context(void);
 258 void dsi_restore_context(void);
 259
 260 int dsi_init_display(struct omap_dss_device *display);
 261 void dsi_irq_handler(void);
 262 unsigned long dsi_get_dsi1_pll_rate(void);
 263 int dsi_pll_set_clock_div(struct dsi_clock_info *cinfo);
 264 int dsi_pll_calc_clock_div_pck(bool is_tft, unsigned long req_pck,
 265                 struct dsi_clock_info *cinfo,
 266                 struct dispc_clock_info *dispc_cinfo);
 267 int dsi_pll_init(struct omap_dss_device *dssdev, bool enable_hsclk,
 268                 bool enable_hsdiv);
 269 void dsi_pll_uninit(void);
 270 void dsi_get_overlay_fifo_thresholds(enum omap_plane plane,
 271                 u32 fifo_size, enum omap_burst_size *burst_size,
 272                 u32 *fifo_low, u32 *fifo_high);
 273
 274 /* DPI */
 275 int dpi_init(struct platform_device *pdev);
 276 void dpi_exit(void);
 277 int dpi_init_display(struct omap_dss_device *dssdev);
 278
 279 /* DISPC */
 280 int dispc_init(void);
 281 void dispc_exit(void);
 282 void dispc_dump_clocks(struct seq_file *s);
 283 void dispc_dump_irqs(struct seq_file *s);
 284 void dispc_dump_regs(struct seq_file *s);
 285 void dispc_irq_handler(void);
 286 void dispc_fake_vsync_irq(void);
 287
 288 void dispc_save_context(void);
 289 void dispc_restore_context(void);
 290
 291 void dispc_enable_sidle(void);
 292 void dispc_disable_sidle(void);
 293
 294 void dispc_lcd_enable_signal_polarity(bool act_high);
 295 void dispc_lcd_enable_signal(bool enable);
 296 void dispc_pck_free_enable(bool enable);
 297 void dispc_enable_fifohandcheck(bool enable);
 298
 299 void dispc_set_lcd_size(u16 width, u16 height);
 300 void dispc_set_digit_size(u16 width, u16 height);
 301 u32 dispc_get_plane_fifo_size(enum omap_plane plane);
 302 void dispc_setup_plane_fifo(enum omap_plane plane, u32 low, u32 high);
 303 void dispc_enable_fifomerge(bool enable);
 304 void dispc_set_burst_size(enum omap_plane plane,
 305                 enum omap_burst_size burst_size);
 306
 307 void dispc_set_plane_ba0(enum omap_plane plane, u32 paddr);
 308 void dispc_set_plane_ba1(enum omap_plane plane, u32 paddr);
 309 void dispc_set_plane_pos(enum omap_plane plane, u16 x, u16 y);
 310 void dispc_set_plane_size(enum omap_plane plane, u16 width, u16 height);
 311 void dispc_set_channel_out(enum omap_plane plane,
 312                 enum omap_channel channel_out);
 313
 314 int dispc_setup_plane(enum omap_plane plane,
 315                       u32 paddr, u16 screen_width,
 316                       u16 pos_x, u16 pos_y,
 317                       u16 width, u16 height,
 318                       u16 out_width, u16 out_height,
 319                       enum omap_color_mode color_mode,
 320                       bool ilace,
 321                       enum omap_dss_rotation_type rotation_type,
 322                       u8 rotation, bool mirror,
 323                       u8 global_alpha);
 324
 325 bool dispc_go_busy(enum omap_channel channel);
 326 void dispc_go(enum omap_channel channel);
 327 void dispc_enable_channel(enum omap_channel channel, bool enable);
 328 bool dispc_is_channel_enabled(enum omap_channel channel);
 329 int dispc_enable_plane(enum omap_plane plane, bool enable);
 330 void dispc_enable_replication(enum omap_plane plane, bool enable);
 331
 332 void dispc_set_parallel_interface_mode(enum omap_parallel_interface_mode mode);
 333 void dispc_set_tft_data_lines(u8 data_lines);
 334 void dispc_set_lcd_display_type(enum omap_lcd_display_type type);
 335 void dispc_set_loadmode(enum omap_dss_load_mode mode);
 336
 337 void dispc_set_default_color(enum omap_channel channel, u32 color);
 338 u32 dispc_get_default_color(enum omap_channel channel);
 339 void dispc_set_trans_key(enum omap_channel ch,
 340                 enum omap_dss_trans_key_type type,
 341                 u32 trans_key);
 342 void dispc_get_trans_key(enum omap_channel ch,
 343                 enum omap_dss_trans_key_type *type,
 344                 u32 *trans_key);
 345 void dispc_enable_trans_key(enum omap_channel ch, bool enable);
 346 void dispc_enable_alpha_blending(enum omap_channel ch, bool enable);
 347 bool dispc_trans_key_enabled(enum omap_channel ch);
 348 bool dispc_alpha_blending_enabled(enum omap_channel ch);
 349
 350 bool dispc_lcd_timings_ok(struct omap_video_timings *timings);
 351 void dispc_set_lcd_timings(struct omap_video_timings *timings);
 352 unsigned long dispc_fclk_rate(void);
 353 unsigned long dispc_lclk_rate(void);
 354 unsigned long dispc_pclk_rate(void);
 355 void dispc_set_pol_freq(enum omap_panel_config config, u8 acbi, u8 acb);
 356 void dispc_find_clk_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
 357                 struct dispc_clock_info *cinfo);
 358 int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
 359                 struct dispc_clock_info *cinfo);
 360 int dispc_set_clock_div(struct dispc_clock_info *cinfo);
 361 int dispc_get_clock_div(struct dispc_clock_info *cinfo);
 362
 363
 364 /* VENC */
 365 int venc_init(struct platform_device *pdev);
 366 void venc_exit(void);
 367 void venc_dump_regs(struct seq_file *s);
 368 int venc_init_display(struct omap_dss_device *display);
 369
 370 /* RFBI */
 371 int rfbi_init(void);
 372 void rfbi_exit(void);
 373 void rfbi_dump_regs(struct seq_file *s);
 374
 375 int rfbi_configure(int rfbi_module, int bpp, int lines);
 376 void rfbi_enable_rfbi(bool enable);
 377 void rfbi_transfer_area(u16 width, u16 height,
 378                              void (callback)(void *data), void *data);
 379 void rfbi_set_timings(int rfbi_module, struct rfbi_timings *t);
 380 unsigned long rfbi_get_max_tx_rate(void);
 381 int rfbi_init_display(struct omap_dss_device *display);
 382
 383
 384 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
 385 static inline void dss_collect_irq_stats(u32 irqstatus, unsigned *irq_arr)
 386 {
 387         int b;
 388         for (b = 0; b < 32; ++b) {
 389                 if (irqstatus & (1 << b))
 390                         irq_arr[b]++;
 391         }
 392 }
 393 #endif
 394
 395 #endif