arch/blackfin/mach-bf518/include/mach/defBF518.h

   1 /*
   2  * Copyright 2008-2009 Analog Devices Inc.
   3  *
   4  * Licensed under the ADI BSD license or the GPL-2 (or later)
   5  */
   6
   7 #ifndef _DEF_BF518_H
   8 #define _DEF_BF518_H
   9
  10 /* BF518 is BF516 + IEEE-1588 */
  11 #include "defBF516.h"
  12
  13 /* PTP TSYNC Registers */
  14
  15 #define EMAC_PTP_CTL                   0xFFC030A0 /* PTP Block Control */
  16 #define EMAC_PTP_IE                    0xFFC030A4 /* PTP Block Interrupt Enable */
  17 #define EMAC_PTP_ISTAT                 0xFFC030A8 /* PTP Block Interrupt Status */
  18 #define EMAC_PTP_FOFF                  0xFFC030AC /* PTP Filter offset Register */
  19 #define EMAC_PTP_FV1                   0xFFC030B0 /* PTP Filter Value Register 1 */
  20 #define EMAC_PTP_FV2                   0xFFC030B4 /* PTP Filter Value Register 2 */
  21 #define EMAC_PTP_FV3                   0xFFC030B8 /* PTP Filter Value Register 3 */
  22 #define EMAC_PTP_ADDEND                0xFFC030BC /* PTP Addend for Frequency Compensation */
  23 #define EMAC_PTP_ACCR                  0xFFC030C0 /* PTP Accumulator for Frequency Compensation */
  24 #define EMAC_PTP_OFFSET                0xFFC030C4 /* PTP Time Offset Register */
  25 #define EMAC_PTP_TIMELO                0xFFC030C8 /* PTP Precision Clock Time Low */
  26 #define EMAC_PTP_TIMEHI                0xFFC030CC /* PTP Precision Clock Time High */
  27 #define EMAC_PTP_RXSNAPLO              0xFFC030D0 /* PTP Receive Snapshot Register Low */
  28 #define EMAC_PTP_RXSNAPHI              0xFFC030D4 /* PTP Receive Snapshot Register High */
  29 #define EMAC_PTP_TXSNAPLO              0xFFC030D8 /* PTP Transmit Snapshot Register Low */
  30 #define EMAC_PTP_TXSNAPHI              0xFFC030DC /* PTP Transmit Snapshot Register High */
  31 #define EMAC_PTP_ALARMLO               0xFFC030E0 /* PTP Alarm time Low */
  32 #define EMAC_PTP_ALARMHI               0xFFC030E4 /* PTP Alarm time High */
  33 #define EMAC_PTP_ID_OFF                0xFFC030E8 /* PTP Capture ID offset register */
  34 #define EMAC_PTP_ID_SNAP               0xFFC030EC /* PTP Capture ID register */
  35 #define EMAC_PTP_PPS_STARTLO           0xFFC030F0 /* PPS Start Time Low */
  36 #define EMAC_PTP_PPS_STARTHI           0xFFC030F4 /* PPS Start Time High */
  37 #define EMAC_PTP_PPS_PERIOD            0xFFC030F8 /* PPS Count Register */
  38
  39 /* Bit masks for EMAC_PTP_CTL */
  40
  41 #define                    PTP_EN  0x1        /* Enable the PTP_TSYNC module */
  42 #define                        TL  0x2        /* Timestamp lock control */
  43 #define                      ASEN  0x10       /* Auxiliary snapshot control */
  44 #define                     PPSEN  0x80       /* Pulse-per-second (PPS) control */
  45 #define                     CKOEN  0x2000     /* Clock output control */
  46
  47 /* Bit masks for EMAC_PTP_IE */
  48
  49 #define                      ALIE  0x1        /* Alarm interrupt enable */
  50 #define                     RXEIE  0x2        /* Receive event interrupt enable */
  51 #define                     RXGIE  0x4        /* Receive general interrupt enable */
  52 #define                      TXIE  0x8        /* Transmit interrupt enable */
  53 #define                     RXOVE  0x10       /* Receive overrun error interrupt enable */
  54 #define                     TXOVE  0x20       /* Transmit overrun error interrupt enable */
  55 #define                      ASIE  0x40       /* Auxiliary snapshot interrupt enable */
  56
  57 /* Bit masks for EMAC_PTP_ISTAT */
  58
  59 #define                       ALS  0x1        /* Alarm status */
  60 #define                      RXEL  0x2        /* Receive event interrupt status */
  61 #define                      RXGL  0x4        /* Receive general interrupt status */
  62 #define                      TXTL  0x8        /* Transmit snapshot status */
  63 #define                      RXOV  0x10       /* Receive snapshot overrun status */
  64 #define                      TXOV  0x20       /* Transmit snapshot overrun status */
  65 #define                       ASL  0x40       /* Auxiliary snapshot interrupt status */
  66
  67 #endif /* _DEF_BF518_H */