arch/blackfin/mach-bf561/smp.c

   1 /*
   2  * Copyright 2007-2009 Analog Devices Inc.
   3  *               Philippe Gerum <rpm@xenomai.org>
   4  *
   5  * Licensed under the GPL-2 or later.
   6  */
   7
   8 #include <linux/init.h>
   9 #include <linux/kernel.h>
  10 #include <linux/sched.h>
  11 #include <linux/delay.h>
  12 #include <asm/smp.h>
  13 #include <asm/dma.h>
  14 #include <asm/time.h>
  15
  16 static DEFINE_SPINLOCK(boot_lock);
  17
  18 /*
  19  * platform_init_cpus() - Tell the world about how many cores we
  20  * have. This is called while setting up the architecture support
  21  * (setup_arch()), so don't be too demanding here with respect to
  22  * available kernel services.
  23  */
  24
  25 void __init platform_init_cpus(void)
  26 {
  27         cpu_set(0, cpu_possible_map); /* CoreA */
  28         cpu_set(1, cpu_possible_map); /* CoreB */
  29 }
  30
  31 void __init platform_prepare_cpus(unsigned int max_cpus)
  32 {
  33         bfin_relocate_coreb_l1_mem();
  34
  35         /* Both cores ought to be present on a bf561! */
  36         cpu_set(0, cpu_present_map); /* CoreA */
  37         cpu_set(1, cpu_present_map); /* CoreB */
  38 }
  39
  40 int __init setup_profiling_timer(unsigned int multiplier) /* not supported */
  41 {
  42         return -EINVAL;
  43 }
  44
  45 void __cpuinit platform_secondary_init(unsigned int cpu)
  46 {
  47         /* Clone setup for peripheral interrupt sources from CoreA. */
  48         bfin_write_SICB_IMASK0(bfin_read_SIC_IMASK0());
  49         bfin_write_SICB_IMASK1(bfin_read_SIC_IMASK1());
  50         SSYNC();
  51
  52         /* Clone setup for IARs from CoreA. */
  53         bfin_write_SICB_IAR0(bfin_read_SIC_IAR0());
  54         bfin_write_SICB_IAR1(bfin_read_SIC_IAR1());
  55         bfin_write_SICB_IAR2(bfin_read_SIC_IAR2());
  56         bfin_write_SICB_IAR3(bfin_read_SIC_IAR3());
  57         bfin_write_SICB_IAR4(bfin_read_SIC_IAR4());
  58         bfin_write_SICB_IAR5(bfin_read_SIC_IAR5());
  59         bfin_write_SICB_IAR6(bfin_read_SIC_IAR6());
  60         bfin_write_SICB_IAR7(bfin_read_SIC_IAR7());
  61         bfin_write_SICB_IWR0(IWR_DISABLE_ALL);
  62         bfin_write_SICB_IWR1(IWR_DISABLE_ALL);
  63         SSYNC();
  64
  65         /* Store CPU-private information to the cpu_data array. */
  66         bfin_setup_cpudata(cpu);
  67
  68         /* We are done with local CPU inits, unblock the boot CPU. */
  69         set_cpu_online(cpu, true);
  70         spin_lock(&boot_lock);
  71         spin_unlock(&boot_lock);
  72 }
  73
  74 int __cpuinit platform_boot_secondary(unsigned int cpu, struct task_struct *idle)
  75 {
  76         unsigned long timeout;
  77
  78         printk(KERN_INFO "Booting Core B.\n");
  79
  80         spin_lock(&boot_lock);
  81
  82         if ((bfin_read_SYSCR() & COREB_SRAM_INIT) == 0) {
  83                 /* CoreB already running, sending ipi to wakeup it */
  84                 platform_send_ipi_cpu(cpu, IRQ_SUPPLE_0);
  85         } else {
  86                 /* Kick CoreB, which should start execution from CORE_SRAM_BASE. */
  87                 bfin_write_SYSCR(bfin_read_SYSCR() & ~COREB_SRAM_INIT);
  88                 SSYNC();
  89         }
  90
  91         timeout = jiffies + 1 * HZ;
  92         while (time_before(jiffies, timeout)) {
  93                 if (cpu_online(cpu))
  94                         break;
  95                 udelay(100);
  96                 barrier();
  97         }
  98
  99         if (cpu_online(cpu)) {
 100                 /* release the lock and let coreb run */
 101                 spin_unlock(&boot_lock);
 102                 return 0;
 103         } else
 104                 panic("CPU%u: processor failed to boot\n", cpu);
 105 }
 106
 107 static const char supple0[] = "IRQ_SUPPLE_0";
 108 static const char supple1[] = "IRQ_SUPPLE_1";
 109 void __init platform_request_ipi(int irq, void *handler)
 110 {
 111         int ret;
 112         const char *name = (irq == IRQ_SUPPLE_0) ? supple0 : supple1;
 113
 114         ret = request_irq(irq, handler, IRQF_DISABLED | IRQF_PERCPU, name, handler);
 115         if (ret)
 116                 panic("Cannot request %s for IPI service", name);
 117 }
 118
 119 void platform_send_ipi(cpumask_t callmap, int irq)
 120 {
 121         unsigned int cpu;
 122         int offset = (irq == IRQ_SUPPLE_0) ? 6 : 8;
 123
 124         for_each_cpu_mask(cpu, callmap) {
 125                 BUG_ON(cpu >= 2);
 126                 SSYNC();
 127                 bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (offset + cpu)));
 128                 SSYNC();
 129         }
 130 }
 131
 132 void platform_send_ipi_cpu(unsigned int cpu, int irq)
 133 {
 134         int offset = (irq == IRQ_SUPPLE_0) ? 6 : 8;
 135         BUG_ON(cpu >= 2);
 136         SSYNC();
 137         bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (offset + cpu)));
 138         SSYNC();
 139 }
 140
 141 void platform_clear_ipi(unsigned int cpu, int irq)
 142 {
 143         int offset = (irq == IRQ_SUPPLE_0) ? 10 : 12;
 144         BUG_ON(cpu >= 2);
 145         SSYNC();
 146         bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (offset + cpu)));
 147         SSYNC();
 148 }
 149
 150 /*
 151  * Setup core B's local core timer.
 152  * In SMP, core timer is used for clock event device.
 153  */
 154 void __cpuinit bfin_local_timer_setup(void)
 155 {
 156 #if defined(CONFIG_TICKSOURCE_CORETMR)
 157         struct irq_data *data = irq_get_irq_data(IRQ_CORETMR);
 158         struct irq_chip *chip = irq_data_get_irq_chip(data);
 159
 160         bfin_coretmr_init();
 161         bfin_coretmr_clockevent_init();
 162
 163         chip->irq_unmask(data);
 164 #else
 165         /* Power down the core timer, just to play safe. */
 166         bfin_write_TCNTL(0);
 167 #endif
 168
 169 }