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Linux 2.6.33-rc2
[pohmelfs.git] / include / linux / i2c / twl.h
blobbf1c5be1f5b66879e238ff6605c17b4787f13ffc
1 /*
2 * twl4030.h - header for TWL4030 PM and audio CODEC device
3 *
4 * Copyright (C) 2005-2006 Texas Instruments, Inc.
5 *
6 * Based on tlv320aic23.c:
7 * Copyright (c) by Kai Svahn <kai.svahn@nokia.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 *
23 */
24
25 #ifndef __TWL_H_
26 #define __TWL_H_
27
28 #include <linux/types.h>
29 #include <linux/input/matrix_keypad.h>
30
31 /*
32 * Using the twl4030 core we address registers using a pair
33 * { module id, relative register offset }
34 * which that core then maps to the relevant
35 * { i2c slave, absolute register address }
36 *
37 * The module IDs are meaningful only to the twl4030 core code,
38 * which uses them as array indices to look up the first register
39 * address each module uses within a given i2c slave.
40 */
41
42 /* Slave 0 (i2c address 0x48) */
43 #define TWL4030_MODULE_USB 0x00
44
45 /* Slave 1 (i2c address 0x49) */
46 #define TWL4030_MODULE_AUDIO_VOICE 0x01
47 #define TWL4030_MODULE_GPIO 0x02
48 #define TWL4030_MODULE_INTBR 0x03
49 #define TWL4030_MODULE_PIH 0x04
50 #define TWL4030_MODULE_TEST 0x05
51
52 /* Slave 2 (i2c address 0x4a) */
53 #define TWL4030_MODULE_KEYPAD 0x06
54 #define TWL4030_MODULE_MADC 0x07
55 #define TWL4030_MODULE_INTERRUPTS 0x08
56 #define TWL4030_MODULE_LED 0x09
57 #define TWL4030_MODULE_MAIN_CHARGE 0x0A
58 #define TWL4030_MODULE_PRECHARGE 0x0B
59 #define TWL4030_MODULE_PWM0 0x0C
60 #define TWL4030_MODULE_PWM1 0x0D
61 #define TWL4030_MODULE_PWMA 0x0E
62 #define TWL4030_MODULE_PWMB 0x0F
63
64 #define TWL5031_MODULE_ACCESSORY 0x10
65 #define TWL5031_MODULE_INTERRUPTS 0x11
66
67 /* Slave 3 (i2c address 0x4b) */
68 #define TWL4030_MODULE_BACKUP 0x12
69 #define TWL4030_MODULE_INT 0x13
70 #define TWL4030_MODULE_PM_MASTER 0x14
71 #define TWL4030_MODULE_PM_RECEIVER 0x15
72 #define TWL4030_MODULE_RTC 0x16
73 #define TWL4030_MODULE_SECURED_REG 0x17
74
75 #define TWL_MODULE_USB TWL4030_MODULE_USB
76 #define TWL_MODULE_AUDIO_VOICE TWL4030_MODULE_AUDIO_VOICE
77 #define TWL_MODULE_PIH TWL4030_MODULE_PIH
78 #define TWL_MODULE_MADC TWL4030_MODULE_MADC
79 #define TWL_MODULE_MAIN_CHARGE TWL4030_MODULE_MAIN_CHARGE
80 #define TWL_MODULE_PM_MASTER TWL4030_MODULE_PM_MASTER
81 #define TWL_MODULE_PM_RECEIVER TWL4030_MODULE_PM_RECEIVER
82 #define TWL_MODULE_RTC TWL4030_MODULE_RTC
83
84 #define GPIO_INTR_OFFSET 0
85 #define KEYPAD_INTR_OFFSET 1
86 #define BCI_INTR_OFFSET 2
87 #define MADC_INTR_OFFSET 3
88 #define USB_INTR_OFFSET 4
89 #define BCI_PRES_INTR_OFFSET 9
90 #define USB_PRES_INTR_OFFSET 10
91 #define RTC_INTR_OFFSET 11
92
93 /*
94 * Offset from TWL6030_IRQ_BASE / pdata->irq_base
95 */
96 #define PWR_INTR_OFFSET 0
97 #define HOTDIE_INTR_OFFSET 12
98 #define SMPSLDO_INTR_OFFSET 13
99 #define BATDETECT_INTR_OFFSET 14
100 #define SIMDETECT_INTR_OFFSET 15
101 #define MMCDETECT_INTR_OFFSET 16
102 #define GASGAUGE_INTR_OFFSET 17
103 #define USBOTG_INTR_OFFSET 4
104 #define CHARGER_INTR_OFFSET 2
105 #define RSV_INTR_OFFSET 0
106
107 /* INT register offsets */
108 #define REG_INT_STS_A 0x00
109 #define REG_INT_STS_B 0x01
110 #define REG_INT_STS_C 0x02
111
112 #define REG_INT_MSK_LINE_A 0x03
113 #define REG_INT_MSK_LINE_B 0x04
114 #define REG_INT_MSK_LINE_C 0x05
115
116 #define REG_INT_MSK_STS_A 0x06
117 #define REG_INT_MSK_STS_B 0x07
118 #define REG_INT_MSK_STS_C 0x08
119
120 /* MASK INT REG GROUP A */
121 #define TWL6030_PWR_INT_MASK 0x07
122 #define TWL6030_RTC_INT_MASK 0x18
123 #define TWL6030_HOTDIE_INT_MASK 0x20
124 #define TWL6030_SMPSLDOA_INT_MASK 0xC0
125
126 /* MASK INT REG GROUP B */
127 #define TWL6030_SMPSLDOB_INT_MASK 0x01
128 #define TWL6030_BATDETECT_INT_MASK 0x02
129 #define TWL6030_SIMDETECT_INT_MASK 0x04
130 #define TWL6030_MMCDETECT_INT_MASK 0x08
131 #define TWL6030_GPADC_INT_MASK 0x60
132 #define TWL6030_GASGAUGE_INT_MASK 0x80
133
134 /* MASK INT REG GROUP C */
135 #define TWL6030_USBOTG_INT_MASK 0x0F
136 #define TWL6030_CHARGER_CTRL_INT_MASK 0x10
137 #define TWL6030_CHARGER_FAULT_INT_MASK 0x60
138
139
140 #define TWL4030_CLASS_ID 0x4030
141 #define TWL6030_CLASS_ID 0x6030
142 unsigned int twl_rev(void);
143 #define GET_TWL_REV (twl_rev())
144 #define TWL_CLASS_IS(class, id) \
145 static inline int twl_class_is_ ##class(void) \
146 { \
147 return ((id) == (GET_TWL_REV)) ? 1 : 0; \
148 }
149
150 TWL_CLASS_IS(4030, TWL4030_CLASS_ID)
151 TWL_CLASS_IS(6030, TWL6030_CLASS_ID)
152
153 /*
154 * Read and write single 8-bit registers
155 */
156 int twl_i2c_write_u8(u8 mod_no, u8 val, u8 reg);
157 int twl_i2c_read_u8(u8 mod_no, u8 *val, u8 reg);
158
159 /*
160 * Read and write several 8-bit registers at once.
161 *
162 * IMPORTANT: For twl_i2c_write(), allocate num_bytes + 1
163 * for the value, and populate your data starting at offset 1.
164 */
165 int twl_i2c_write(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes);
166 int twl_i2c_read(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes);
167
168 int twl6030_interrupt_unmask(u8 bit_mask, u8 offset);
169 int twl6030_interrupt_mask(u8 bit_mask, u8 offset);
170
171 /*----------------------------------------------------------------------*/
172
173 /*
174 * NOTE: at up to 1024 registers, this is a big chip.
175 *
176 * Avoid putting register declarations in this file, instead of into
177 * a driver-private file, unless some of the registers in a block
178 * need to be shared with other drivers. One example is blocks that
179 * have Secondary IRQ Handler (SIH) registers.
180 */
181
182 #define TWL4030_SIH_CTRL_EXCLEN_MASK BIT(0)
183 #define TWL4030_SIH_CTRL_PENDDIS_MASK BIT(1)
184 #define TWL4030_SIH_CTRL_COR_MASK BIT(2)
185
186 /*----------------------------------------------------------------------*/
187
188 /*
189 * GPIO Block Register offsets (use TWL4030_MODULE_GPIO)
190 */
191
192 #define REG_GPIODATAIN1 0x0
193 #define REG_GPIODATAIN2 0x1
194 #define REG_GPIODATAIN3 0x2
195 #define REG_GPIODATADIR1 0x3
196 #define REG_GPIODATADIR2 0x4
197 #define REG_GPIODATADIR3 0x5
198 #define REG_GPIODATAOUT1 0x6
199 #define REG_GPIODATAOUT2 0x7
200 #define REG_GPIODATAOUT3 0x8
201 #define REG_CLEARGPIODATAOUT1 0x9
202 #define REG_CLEARGPIODATAOUT2 0xA
203 #define REG_CLEARGPIODATAOUT3 0xB
204 #define REG_SETGPIODATAOUT1 0xC
205 #define REG_SETGPIODATAOUT2 0xD
206 #define REG_SETGPIODATAOUT3 0xE
207 #define REG_GPIO_DEBEN1 0xF
208 #define REG_GPIO_DEBEN2 0x10
209 #define REG_GPIO_DEBEN3 0x11
210 #define REG_GPIO_CTRL 0x12
211 #define REG_GPIOPUPDCTR1 0x13
212 #define REG_GPIOPUPDCTR2 0x14
213 #define REG_GPIOPUPDCTR3 0x15
214 #define REG_GPIOPUPDCTR4 0x16
215 #define REG_GPIOPUPDCTR5 0x17
216 #define REG_GPIO_ISR1A 0x19
217 #define REG_GPIO_ISR2A 0x1A
218 #define REG_GPIO_ISR3A 0x1B
219 #define REG_GPIO_IMR1A 0x1C
220 #define REG_GPIO_IMR2A 0x1D
221 #define REG_GPIO_IMR3A 0x1E
222 #define REG_GPIO_ISR1B 0x1F
223 #define REG_GPIO_ISR2B 0x20
224 #define REG_GPIO_ISR3B 0x21
225 #define REG_GPIO_IMR1B 0x22
226 #define REG_GPIO_IMR2B 0x23
227 #define REG_GPIO_IMR3B 0x24
228 #define REG_GPIO_EDR1 0x28
229 #define REG_GPIO_EDR2 0x29
230 #define REG_GPIO_EDR3 0x2A
231 #define REG_GPIO_EDR4 0x2B
232 #define REG_GPIO_EDR5 0x2C
233 #define REG_GPIO_SIH_CTRL 0x2D
234
235 /* Up to 18 signals are available as GPIOs, when their
236 * pins are not assigned to another use (such as ULPI/USB).
237 */
238 #define TWL4030_GPIO_MAX 18
239
240 /*----------------------------------------------------------------------*/
241
242 /*
243 * Keypad register offsets (use TWL4030_MODULE_KEYPAD)
244 * ... SIH/interrupt only
245 */
246
247 #define TWL4030_KEYPAD_KEYP_ISR1 0x11
248 #define TWL4030_KEYPAD_KEYP_IMR1 0x12
249 #define TWL4030_KEYPAD_KEYP_ISR2 0x13
250 #define TWL4030_KEYPAD_KEYP_IMR2 0x14
251 #define TWL4030_KEYPAD_KEYP_SIR 0x15 /* test register */
252 #define TWL4030_KEYPAD_KEYP_EDR 0x16
253 #define TWL4030_KEYPAD_KEYP_SIH_CTRL 0x17
254
255 /*----------------------------------------------------------------------*/
256
257 /*
258 * Multichannel ADC register offsets (use TWL4030_MODULE_MADC)
259 * ... SIH/interrupt only
260 */
261
262 #define TWL4030_MADC_ISR1 0x61
263 #define TWL4030_MADC_IMR1 0x62
264 #define TWL4030_MADC_ISR2 0x63
265 #define TWL4030_MADC_IMR2 0x64
266 #define TWL4030_MADC_SIR 0x65 /* test register */
267 #define TWL4030_MADC_EDR 0x66
268 #define TWL4030_MADC_SIH_CTRL 0x67
269
270 /*----------------------------------------------------------------------*/
271
272 /*
273 * Battery charger register offsets (use TWL4030_MODULE_INTERRUPTS)
274 */
275
276 #define TWL4030_INTERRUPTS_BCIISR1A 0x0
277 #define TWL4030_INTERRUPTS_BCIISR2A 0x1
278 #define TWL4030_INTERRUPTS_BCIIMR1A 0x2
279 #define TWL4030_INTERRUPTS_BCIIMR2A 0x3
280 #define TWL4030_INTERRUPTS_BCIISR1B 0x4
281 #define TWL4030_INTERRUPTS_BCIISR2B 0x5
282 #define TWL4030_INTERRUPTS_BCIIMR1B 0x6
283 #define TWL4030_INTERRUPTS_BCIIMR2B 0x7
284 #define TWL4030_INTERRUPTS_BCISIR1 0x8 /* test register */
285 #define TWL4030_INTERRUPTS_BCISIR2 0x9 /* test register */
286 #define TWL4030_INTERRUPTS_BCIEDR1 0xa
287 #define TWL4030_INTERRUPTS_BCIEDR2 0xb
288 #define TWL4030_INTERRUPTS_BCIEDR3 0xc
289 #define TWL4030_INTERRUPTS_BCISIHCTRL 0xd
290
291 /*----------------------------------------------------------------------*/
292
293 /*
294 * Power Interrupt block register offsets (use TWL4030_MODULE_INT)
295 */
296
297 #define TWL4030_INT_PWR_ISR1 0x0
298 #define TWL4030_INT_PWR_IMR1 0x1
299 #define TWL4030_INT_PWR_ISR2 0x2
300 #define TWL4030_INT_PWR_IMR2 0x3
301 #define TWL4030_INT_PWR_SIR 0x4 /* test register */
302 #define TWL4030_INT_PWR_EDR1 0x5
303 #define TWL4030_INT_PWR_EDR2 0x6
304 #define TWL4030_INT_PWR_SIH_CTRL 0x7
305
306 /*----------------------------------------------------------------------*/
307
308 /*
309 * Accessory Interrupts
310 */
311 #define TWL5031_ACIIMR_LSB 0x05
312 #define TWL5031_ACIIMR_MSB 0x06
313 #define TWL5031_ACIIDR_LSB 0x07
314 #define TWL5031_ACIIDR_MSB 0x08
315 #define TWL5031_ACCISR1 0x0F
316 #define TWL5031_ACCIMR1 0x10
317 #define TWL5031_ACCISR2 0x11
318 #define TWL5031_ACCIMR2 0x12
319 #define TWL5031_ACCSIR 0x13
320 #define TWL5031_ACCEDR1 0x14
321 #define TWL5031_ACCSIHCTRL 0x15
322
323 /*----------------------------------------------------------------------*/
324
325 /*
326 * Battery Charger Controller
327 */
328
329 #define TWL5031_INTERRUPTS_BCIISR1 0x0
330 #define TWL5031_INTERRUPTS_BCIIMR1 0x1
331 #define TWL5031_INTERRUPTS_BCIISR2 0x2
332 #define TWL5031_INTERRUPTS_BCIIMR2 0x3
333 #define TWL5031_INTERRUPTS_BCISIR 0x4
334 #define TWL5031_INTERRUPTS_BCIEDR1 0x5
335 #define TWL5031_INTERRUPTS_BCIEDR2 0x6
336 #define TWL5031_INTERRUPTS_BCISIHCTRL 0x7
337
338 /*----------------------------------------------------------------------*/
339
340 /* Power bus message definitions */
341
342 /* The TWL4030/5030 splits its power-management resources (the various
343 * regulators, clock and reset lines) into 3 processor groups - P1, P2 and
344 * P3. These groups can then be configured to transition between sleep, wait-on
345 * and active states by sending messages to the power bus. See Section 5.4.2
346 * Power Resources of TWL4030 TRM
347 */
348
349 /* Processor groups */
350 #define DEV_GRP_NULL 0x0
351 #define DEV_GRP_P1 0x1 /* P1: all OMAP devices */
352 #define DEV_GRP_P2 0x2 /* P2: all Modem devices */
353 #define DEV_GRP_P3 0x4 /* P3: all peripheral devices */
354
355 /* Resource groups */
356 #define RES_GRP_RES 0x0 /* Reserved */
357 #define RES_GRP_PP 0x1 /* Power providers */
358 #define RES_GRP_RC 0x2 /* Reset and control */
359 #define RES_GRP_PP_RC 0x3
360 #define RES_GRP_PR 0x4 /* Power references */
361 #define RES_GRP_PP_PR 0x5
362 #define RES_GRP_RC_PR 0x6
363 #define RES_GRP_ALL 0x7 /* All resource groups */
364
365 #define RES_TYPE2_R0 0x0
366
367 #define RES_TYPE_ALL 0x7
368
369 /* Resource states */
370 #define RES_STATE_WRST 0xF
371 #define RES_STATE_ACTIVE 0xE
372 #define RES_STATE_SLEEP 0x8
373 #define RES_STATE_OFF 0x0
374
375 /* Power resources */
376
377 /* Power providers */
378 #define RES_VAUX1 1
379 #define RES_VAUX2 2
380 #define RES_VAUX3 3
381 #define RES_VAUX4 4
382 #define RES_VMMC1 5
383 #define RES_VMMC2 6
384 #define RES_VPLL1 7
385 #define RES_VPLL2 8
386 #define RES_VSIM 9
387 #define RES_VDAC 10
388 #define RES_VINTANA1 11
389 #define RES_VINTANA2 12
390 #define RES_VINTDIG 13
391 #define RES_VIO 14
392 #define RES_VDD1 15
393 #define RES_VDD2 16
394 #define RES_VUSB_1V5 17
395 #define RES_VUSB_1V8 18
396 #define RES_VUSB_3V1 19
397 #define RES_VUSBCP 20
398 #define RES_REGEN 21
399 /* Reset and control */
400 #define RES_NRES_PWRON 22
401 #define RES_CLKEN 23
402 #define RES_SYSEN 24
403 #define RES_HFCLKOUT 25
404 #define RES_32KCLKOUT 26
405 #define RES_RESET 27
406 /* Power Reference */
407 #define RES_Main_Ref 28
408
409 #define TOTAL_RESOURCES 28
410 /*
411 * Power Bus Message Format ... these can be sent individually by Linux,
412 * but are usually part of downloaded scripts that are run when various
413 * power events are triggered.
414 *
415 * Broadcast Message (16 Bits):
416 * DEV_GRP[15:13] MT[12] RES_GRP[11:9] RES_TYPE2[8:7] RES_TYPE[6:4]
417 * RES_STATE[3:0]
418 *
419 * Singular Message (16 Bits):
420 * DEV_GRP[15:13] MT[12] RES_ID[11:4] RES_STATE[3:0]
421 */
422
423 #define MSG_BROADCAST(devgrp, grp, type, type2, state) \
424 ( (devgrp) << 13 | 1 << 12 | (grp) << 9 | (type2) << 7 \
425 | (type) << 4 | (state))
426
427 #define MSG_SINGULAR(devgrp, id, state) \
428 ((devgrp) << 13 | 0 << 12 | (id) << 4 | (state))
429
430 #define MSG_BROADCAST_ALL(devgrp, state) \
431 ((devgrp) << 5 | (state))
432
433 #define MSG_BROADCAST_REF MSG_BROADCAST_ALL
434 #define MSG_BROADCAST_PROV MSG_BROADCAST_ALL
435 #define MSG_BROADCAST__CLK_RST MSG_BROADCAST_ALL
436 /*----------------------------------------------------------------------*/
437
438 struct twl4030_clock_init_data {
439 bool ck32k_lowpwr_enable;
440 };
441
442 struct twl4030_bci_platform_data {
443 int *battery_tmp_tbl;
444 unsigned int tblsize;
445 };
446
447 /* TWL4030_GPIO_MAX (18) GPIOs, with interrupts */
448 struct twl4030_gpio_platform_data {
449 int gpio_base;
450 unsigned irq_base, irq_end;
451
452 /* package the two LED signals as output-only GPIOs? */
453 bool use_leds;
454
455 /* gpio-n should control VMMC(n+1) if BIT(n) in mmc_cd is set */
456 u8 mmc_cd;
457
458 /* if BIT(N) is set, or VMMC(n+1) is linked, debounce GPIO-N */
459 u32 debounce;
460
461 /* For gpio-N, bit (1 << N) in "pullups" is set if that pullup
462 * should be enabled. Else, if that bit is set in "pulldowns",
463 * that pulldown is enabled. Don't waste power by letting any
464 * digital inputs float...
465 */
466 u32 pullups;
467 u32 pulldowns;
468
469 int (*setup)(struct device *dev,
470 unsigned gpio, unsigned ngpio);
471 int (*teardown)(struct device *dev,
472 unsigned gpio, unsigned ngpio);
473 };
474
475 struct twl4030_madc_platform_data {
476 int irq_line;
477 };
478
479 /* Boards have uniqe mappings of {row, col} --> keycode.
480 * Column and row are 8 bits each, but range only from 0..7.
481 * a PERSISTENT_KEY is "always on" and never reported.
482 */
483 #define PERSISTENT_KEY(r, c) KEY((r), (c), KEY_RESERVED)
484
485 struct twl4030_keypad_data {
486 const struct matrix_keymap_data *keymap_data;
487 unsigned rows;
488 unsigned cols;
489 bool rep;
490 };
491
492 enum twl4030_usb_mode {
493 T2_USB_MODE_ULPI = 1,
494 T2_USB_MODE_CEA2011_3PIN = 2,
495 };
496
497 struct twl4030_usb_data {
498 enum twl4030_usb_mode usb_mode;
499 };
500
501 struct twl4030_ins {
502 u16 pmb_message;
503 u8 delay;
504 };
505
506 struct twl4030_script {
507 struct twl4030_ins *script;
508 unsigned size;
509 u8 flags;
510 #define TWL4030_WRST_SCRIPT (1<<0)
511 #define TWL4030_WAKEUP12_SCRIPT (1<<1)
512 #define TWL4030_WAKEUP3_SCRIPT (1<<2)
513 #define TWL4030_SLEEP_SCRIPT (1<<3)
514 };
515
516 struct twl4030_resconfig {
517 u8 resource;
518 u8 devgroup; /* Processor group that Power resource belongs to */
519 u8 type; /* Power resource addressed, 6 / broadcast message */
520 u8 type2; /* Power resource addressed, 3 / broadcast message */
521 u8 remap_off; /* off state remapping */
522 u8 remap_sleep; /* sleep state remapping */
523 };
524
525 struct twl4030_power_data {
526 struct twl4030_script **scripts;
527 unsigned num;
528 struct twl4030_resconfig *resource_config;
529 #define TWL4030_RESCONFIG_UNDEF ((u8)-1)
530 };
531
532 extern void twl4030_power_init(struct twl4030_power_data *triton2_scripts);
533
534 struct twl4030_codec_audio_data {
535 unsigned int audio_mclk;
536 unsigned int ramp_delay_value;
537 unsigned int hs_extmute:1;
538 void (*set_hs_extmute)(int mute);
539 };
540
541 struct twl4030_codec_vibra_data {
542 unsigned int audio_mclk;
543 unsigned int coexist;
544 };
545
546 struct twl4030_codec_data {
547 unsigned int audio_mclk;
548 struct twl4030_codec_audio_data *audio;
549 struct twl4030_codec_vibra_data *vibra;
550 };
551
552 struct twl4030_platform_data {
553 unsigned irq_base, irq_end;
554 struct twl4030_clock_init_data *clock;
555 struct twl4030_bci_platform_data *bci;
556 struct twl4030_gpio_platform_data *gpio;
557 struct twl4030_madc_platform_data *madc;
558 struct twl4030_keypad_data *keypad;
559 struct twl4030_usb_data *usb;
560 struct twl4030_power_data *power;
561 struct twl4030_codec_data *codec;
562
563 /* Common LDO regulators for TWL4030/TWL6030 */
564 struct regulator_init_data *vdac;
565 struct regulator_init_data *vaux1;
566 struct regulator_init_data *vaux2;
567 struct regulator_init_data *vaux3;
568 /* TWL4030 LDO regulators */
569 struct regulator_init_data *vpll1;
570 struct regulator_init_data *vpll2;
571 struct regulator_init_data *vmmc1;
572 struct regulator_init_data *vmmc2;
573 struct regulator_init_data *vsim;
574 struct regulator_init_data *vaux4;
575 struct regulator_init_data *vio;
576 struct regulator_init_data *vdd1;
577 struct regulator_init_data *vdd2;
578 struct regulator_init_data *vintana1;
579 struct regulator_init_data *vintana2;
580 struct regulator_init_data *vintdig;
581 /* TWL6030 LDO regulators */
582 struct regulator_init_data *vmmc;
583 struct regulator_init_data *vpp;
584 struct regulator_init_data *vusim;
585 struct regulator_init_data *vana;
586 struct regulator_init_data *vcxio;
587 struct regulator_init_data *vusb;
588 };
589
590 /*----------------------------------------------------------------------*/
591
592 int twl4030_sih_setup(int module);
593
594 /* Offsets to Power Registers */
595 #define TWL4030_VDAC_DEV_GRP 0x3B
596 #define TWL4030_VDAC_DEDICATED 0x3E
597 #define TWL4030_VAUX1_DEV_GRP 0x17
598 #define TWL4030_VAUX1_DEDICATED 0x1A
599 #define TWL4030_VAUX2_DEV_GRP 0x1B
600 #define TWL4030_VAUX2_DEDICATED 0x1E
601 #define TWL4030_VAUX3_DEV_GRP 0x1F
602 #define TWL4030_VAUX3_DEDICATED 0x22
603
604 #if defined(CONFIG_TWL4030_BCI_BATTERY) || \
605 defined(CONFIG_TWL4030_BCI_BATTERY_MODULE)
606 extern int twl4030charger_usb_en(int enable);
607 #else
608 static inline int twl4030charger_usb_en(int enable) { return 0; }
609 #endif
610
611 /*----------------------------------------------------------------------*/
612
613 /* Linux-specific regulator identifiers ... for now, we only support
614 * the LDOs, and leave the three buck converters alone. VDD1 and VDD2
615 * need to tie into hardware based voltage scaling (cpufreq etc), while
616 * VIO is generally fixed.
617 */
618
619 /* TWL4030 SMPS/LDO's */
620 /* EXTERNAL dc-to-dc buck converters */
621 #define TWL4030_REG_VDD1 0
622 #define TWL4030_REG_VDD2 1
623 #define TWL4030_REG_VIO 2
624
625 /* EXTERNAL LDOs */
626 #define TWL4030_REG_VDAC 3
627 #define TWL4030_REG_VPLL1 4
628 #define TWL4030_REG_VPLL2 5 /* not on all chips */
629 #define TWL4030_REG_VMMC1 6
630 #define TWL4030_REG_VMMC2 7 /* not on all chips */
631 #define TWL4030_REG_VSIM 8 /* not on all chips */
632 #define TWL4030_REG_VAUX1 9 /* not on all chips */
633 #define TWL4030_REG_VAUX2_4030 10 /* (twl4030-specific) */
634 #define TWL4030_REG_VAUX2 11 /* (twl5030 and newer) */
635 #define TWL4030_REG_VAUX3 12 /* not on all chips */
636 #define TWL4030_REG_VAUX4 13 /* not on all chips */
637
638 /* INTERNAL LDOs */
639 #define TWL4030_REG_VINTANA1 14
640 #define TWL4030_REG_VINTANA2 15
641 #define TWL4030_REG_VINTDIG 16
642 #define TWL4030_REG_VUSB1V5 17
643 #define TWL4030_REG_VUSB1V8 18
644 #define TWL4030_REG_VUSB3V1 19
645
646 /* TWL6030 SMPS/LDO's */
647 /* EXTERNAL dc-to-dc buck convertor contollable via SR */
648 #define TWL6030_REG_VDD1 30
649 #define TWL6030_REG_VDD2 31
650 #define TWL6030_REG_VDD3 32
651
652 /* Non SR compliant dc-to-dc buck convertors */
653 #define TWL6030_REG_VMEM 33
654 #define TWL6030_REG_V2V1 34
655 #define TWL6030_REG_V1V29 35
656 #define TWL6030_REG_V1V8 36
657
658 /* EXTERNAL LDOs */
659 #define TWL6030_REG_VAUX1_6030 37
660 #define TWL6030_REG_VAUX2_6030 38
661 #define TWL6030_REG_VAUX3_6030 39
662 #define TWL6030_REG_VMMC 40
663 #define TWL6030_REG_VPP 41
664 #define TWL6030_REG_VUSIM 42
665 #define TWL6030_REG_VANA 43
666 #define TWL6030_REG_VCXIO 44
667 #define TWL6030_REG_VDAC 45
668 #define TWL6030_REG_VUSB 46
669
670 /* INTERNAL LDOs */
671 #define TWL6030_REG_VRTC 47
672
673 #endif /* End of __TWL4030_H */