| blob | c244b06caac9630679f11403a1f60bc0617799a8 |
1 /*
2 * linux/arch/arm/mm/proc-arm1020e.S: MMU functions for ARM1020
3 *
4 * Copyright (C) 2000 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd.
6 * hacked for non-paged-MM by Hyok S. Choi, 2003.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 *
23 * These are the low level assembler for performing cache and TLB
24 * functions on the arm1020e.
25 *
26 * CONFIG_CPU_ARM1020_CPU_IDLE -> nohlt
27 */
28 #include <linux/linkage.h>
29 #include <linux/init.h>
30 #include <asm/assembler.h>
31 #include <asm/asm-offsets.h>
32 #include <asm/hwcap.h>
33 #include <asm/pgtable-hwdef.h>
34 #include <asm/pgtable.h>
35 #include <asm/ptrace.h>
37 #include "proc-macros.S"
39 /*
40 * This is the maximum size of an area which will be invalidated
41 * using the single invalidate entry instructions. Anything larger
42 * than this, and we go for the whole cache.
43 *
44 * This value should be chosen such that we choose the cheapest
45 * alternative.
46 */
47 #define MAX_AREA_SIZE 32768
49 /*
50 * The size of one data cache line.
51 */
52 #define CACHE_DLINESIZE 32
54 /*
55 * The number of data cache segments.
56 */
57 #define CACHE_DSEGMENTS 16
59 /*
60 * The number of lines in a cache segment.
61 */
62 #define CACHE_DENTRIES 64
64 /*
65 * This is the size at which it becomes more efficient to
66 * clean the whole cache, rather than using the individual
67 * cache line maintenance instructions.
68 */
69 #define CACHE_DLIMIT 32768
71 .text
72 /*
73 * cpu_arm1020e_proc_init()
74 */
75 ENTRY(cpu_arm1020e_proc_init)
76 mov pc, lr
78 /*
79 * cpu_arm1020e_proc_fin()
80 */
81 ENTRY(cpu_arm1020e_proc_fin)
82 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
83 bic r0, r0, #0x1000 @ ...i............
84 bic r0, r0, #0x000e @ ............wca.
85 mcr p15, 0, r0, c1, c0, 0 @ disable caches
86 mov pc, lr
88 /*
89 * cpu_arm1020e_reset(loc)
90 *
91 * Perform a soft reset of the system. Put the CPU into the
92 * same state as it would be if it had been reset, and branch
93 * to what would be the reset vector.
94 *
95 * loc: location to jump to for soft reset
96 */
97 .align 5
98 .pushsection .idmap.text, "ax"
99 ENTRY(cpu_arm1020e_reset)
100 mov ip, #0
101 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
102 mcr p15, 0, ip, c7, c10, 4 @ drain WB
103 #ifdef CONFIG_MMU
104 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
105 #endif
106 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
107 bic ip, ip, #0x000f @ ............wcam
108 bic ip, ip, #0x1100 @ ...i...s........
109 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
110 mov pc, r0
111 ENDPROC(cpu_arm1020e_reset)
112 .popsection
114 /*
115 * cpu_arm1020e_do_idle()
116 */
117 .align 5
118 ENTRY(cpu_arm1020e_do_idle)
119 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
120 mov pc, lr
122 /* ================================= CACHE ================================ */
124 .align 5
126 /*
127 * flush_icache_all()
128 *
129 * Unconditionally clean and invalidate the entire icache.
130 */
131 ENTRY(arm1020e_flush_icache_all)
132 #ifndef CONFIG_CPU_ICACHE_DISABLE
133 mov r0, #0
134 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
135 #endif
136 mov pc, lr
137 ENDPROC(arm1020e_flush_icache_all)
139 /*
140 * flush_user_cache_all()
141 *
142 * Invalidate all cache entries in a particular address
143 * space.
144 */
145 ENTRY(arm1020e_flush_user_cache_all)
146 /* FALLTHROUGH */
147 /*
148 * flush_kern_cache_all()
149 *
150 * Clean and invalidate the entire cache.
151 */
152 ENTRY(arm1020e_flush_kern_cache_all)
153 mov r2, #VM_EXEC
154 mov ip, #0
155 __flush_whole_cache:
156 #ifndef CONFIG_CPU_DCACHE_DISABLE
157 mcr p15, 0, ip, c7, c10, 4 @ drain WB
158 mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 16 segments
159 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
160 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
161 subs r3, r3, #1 << 26
162 bcs 2b @ entries 63 to 0
163 subs r1, r1, #1 << 5
164 bcs 1b @ segments 15 to 0
165 #endif
166 tst r2, #VM_EXEC
167 #ifndef CONFIG_CPU_ICACHE_DISABLE
168 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
169 #endif
170 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
171 mov pc, lr
173 /*
174 * flush_user_cache_range(start, end, flags)
175 *
176 * Invalidate a range of cache entries in the specified
177 * address space.
178 *
179 * - start - start address (inclusive)
180 * - end - end address (exclusive)
181 * - flags - vm_flags for this space
182 */
183 ENTRY(arm1020e_flush_user_cache_range)
184 mov ip, #0
185 sub r3, r1, r0 @ calculate total size
186 cmp r3, #CACHE_DLIMIT
187 bhs __flush_whole_cache
189 #ifndef CONFIG_CPU_DCACHE_DISABLE
190 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
191 add r0, r0, #CACHE_DLINESIZE
192 cmp r0, r1
193 blo 1b
194 #endif
195 tst r2, #VM_EXEC
196 #ifndef CONFIG_CPU_ICACHE_DISABLE
197 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
198 #endif
199 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
200 mov pc, lr
202 /*
203 * coherent_kern_range(start, end)
204 *
205 * Ensure coherency between the Icache and the Dcache in the
206 * region described by start. If you have non-snooping
207 * Harvard caches, you need to implement this function.
208 *
209 * - start - virtual start address
210 * - end - virtual end address
211 */
212 ENTRY(arm1020e_coherent_kern_range)
213 /* FALLTHROUGH */
214 /*
215 * coherent_user_range(start, end)
216 *
217 * Ensure coherency between the Icache and the Dcache in the
218 * region described by start. If you have non-snooping
219 * Harvard caches, you need to implement this function.
220 *
221 * - start - virtual start address
222 * - end - virtual end address
223 */
224 ENTRY(arm1020e_coherent_user_range)
225 mov ip, #0
226 bic r0, r0, #CACHE_DLINESIZE - 1
227 1:
228 #ifndef CONFIG_CPU_DCACHE_DISABLE
229 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
230 #endif
231 #ifndef CONFIG_CPU_ICACHE_DISABLE
232 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
233 #endif
234 add r0, r0, #CACHE_DLINESIZE
235 cmp r0, r1
236 blo 1b
237 mcr p15, 0, ip, c7, c10, 4 @ drain WB
238 mov pc, lr
240 /*
241 * flush_kern_dcache_area(void *addr, size_t size)
242 *
243 * Ensure no D cache aliasing occurs, either with itself or
244 * the I cache
245 *
246 * - addr - kernel address
247 * - size - region size
248 */
249 ENTRY(arm1020e_flush_kern_dcache_area)
250 mov ip, #0
251 #ifndef CONFIG_CPU_DCACHE_DISABLE
252 add r1, r0, r1
253 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
254 add r0, r0, #CACHE_DLINESIZE
255 cmp r0, r1
256 blo 1b
257 #endif
258 mcr p15, 0, ip, c7, c10, 4 @ drain WB
259 mov pc, lr
261 /*
262 * dma_inv_range(start, end)
263 *
264 * Invalidate (discard) the specified virtual address range.
265 * May not write back any entries. If 'start' or 'end'
266 * are not cache line aligned, those lines must be written
267 * back.
268 *
269 * - start - virtual start address
270 * - end - virtual end address
271 *
272 * (same as v4wb)
273 */
274 arm1020e_dma_inv_range:
275 mov ip, #0
276 #ifndef CONFIG_CPU_DCACHE_DISABLE
277 tst r0, #CACHE_DLINESIZE - 1
278 bic r0, r0, #CACHE_DLINESIZE - 1
279 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
280 tst r1, #CACHE_DLINESIZE - 1
281 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
282 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
283 add r0, r0, #CACHE_DLINESIZE
284 cmp r0, r1
285 blo 1b
286 #endif
287 mcr p15, 0, ip, c7, c10, 4 @ drain WB
288 mov pc, lr
290 /*
291 * dma_clean_range(start, end)
292 *
293 * Clean the specified virtual address range.
294 *
295 * - start - virtual start address
296 * - end - virtual end address
297 *
298 * (same as v4wb)
299 */
300 arm1020e_dma_clean_range:
301 mov ip, #0
302 #ifndef CONFIG_CPU_DCACHE_DISABLE
303 bic r0, r0, #CACHE_DLINESIZE - 1
304 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
305 add r0, r0, #CACHE_DLINESIZE
306 cmp r0, r1
307 blo 1b
308 #endif
309 mcr p15, 0, ip, c7, c10, 4 @ drain WB
310 mov pc, lr
312 /*
313 * dma_flush_range(start, end)
314 *
315 * Clean and invalidate the specified virtual address range.
316 *
317 * - start - virtual start address
318 * - end - virtual end address
319 */
320 ENTRY(arm1020e_dma_flush_range)
321 mov ip, #0
322 #ifndef CONFIG_CPU_DCACHE_DISABLE
323 bic r0, r0, #CACHE_DLINESIZE - 1
324 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
325 add r0, r0, #CACHE_DLINESIZE
326 cmp r0, r1
327 blo 1b
328 #endif
329 mcr p15, 0, ip, c7, c10, 4 @ drain WB
330 mov pc, lr
332 /*
333 * dma_map_area(start, size, dir)
334 * - start - kernel virtual start address
335 * - size - size of region
336 * - dir - DMA direction
337 */
338 ENTRY(arm1020e_dma_map_area)
339 add r1, r1, r0
340 cmp r2, #DMA_TO_DEVICE
341 beq arm1020e_dma_clean_range
342 bcs arm1020e_dma_inv_range
343 b arm1020e_dma_flush_range
344 ENDPROC(arm1020e_dma_map_area)
346 /*
347 * dma_unmap_area(start, size, dir)
348 * - start - kernel virtual start address
349 * - size - size of region
350 * - dir - DMA direction
351 */
352 ENTRY(arm1020e_dma_unmap_area)
353 mov pc, lr
354 ENDPROC(arm1020e_dma_unmap_area)
356 @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
357 define_cache_functions arm1020e
359 .align 5
360 ENTRY(cpu_arm1020e_dcache_clean_area)
361 #ifndef CONFIG_CPU_DCACHE_DISABLE
362 mov ip, #0
363 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
364 add r0, r0, #CACHE_DLINESIZE
365 subs r1, r1, #CACHE_DLINESIZE
366 bhi 1b
367 #endif
368 mov pc, lr
370 /* =============================== PageTable ============================== */
372 /*
373 * cpu_arm1020e_switch_mm(pgd)
374 *
375 * Set the translation base pointer to be as described by pgd.
376 *
377 * pgd: new page tables
378 */
379 .align 5
380 ENTRY(cpu_arm1020e_switch_mm)
381 #ifdef CONFIG_MMU
382 #ifndef CONFIG_CPU_DCACHE_DISABLE
383 mcr p15, 0, r3, c7, c10, 4
384 mov r1, #0xF @ 16 segments
385 1: mov r3, #0x3F @ 64 entries
386 2: mov ip, r3, LSL #26 @ shift up entry
387 orr ip, ip, r1, LSL #5 @ shift in/up index
388 mcr p15, 0, ip, c7, c14, 2 @ Clean & Inval DCache entry
389 mov ip, #0
390 subs r3, r3, #1
391 cmp r3, #0
392 bge 2b @ entries 3F to 0
393 subs r1, r1, #1
394 cmp r1, #0
395 bge 1b @ segments 15 to 0
397 #endif
398 mov r1, #0
399 #ifndef CONFIG_CPU_ICACHE_DISABLE
400 mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache
401 #endif
402 mcr p15, 0, r1, c7, c10, 4 @ drain WB
403 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
404 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
405 #endif
406 mov pc, lr
408 /*
409 * cpu_arm1020e_set_pte(ptep, pte)
410 *
411 * Set a PTE and flush it out
412 */
413 .align 5
414 ENTRY(cpu_arm1020e_set_pte_ext)
415 #ifdef CONFIG_MMU
416 armv3_set_pte_ext
417 mov r0, r0
418 #ifndef CONFIG_CPU_DCACHE_DISABLE
419 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
420 #endif
421 #endif /* CONFIG_MMU */
422 mov pc, lr
424 __CPUINIT
426 .type __arm1020e_setup, #function
427 __arm1020e_setup:
428 mov r0, #0
429 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
430 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
431 #ifdef CONFIG_MMU
432 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
433 #endif
434 adr r5, arm1020e_crval
435 ldmia r5, {r5, r6}
436 mrc p15, 0, r0, c1, c0 @ get control register v4
437 bic r0, r0, r5
438 orr r0, r0, r6
439 #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
440 orr r0, r0, #0x4000 @ .R.. .... .... ....
441 #endif
442 mov pc, lr
443 .size __arm1020e_setup, . - __arm1020e_setup
445 /*
446 * R
447 * .RVI ZFRS BLDP WCAM
448 * .011 1001 ..11 0101
449 */
450 .type arm1020e_crval, #object
451 arm1020e_crval:
452 crval clear=0x00007f3f, mmuset=0x00003935, ucset=0x00001930
454 __INITDATA
455 @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
456 define_processor_functions arm1020e, dabort=v4t_early_abort, pabort=legacy_pabort
458 .section ".rodata"
460 string cpu_arch_name, "armv5te"
461 string cpu_elf_name, "v5"
462 string cpu_arm1020e_name, "ARM1020E"
464 .align
466 .section ".proc.info.init", #alloc, #execinstr
468 .type __arm1020e_proc_info,#object
469 __arm1020e_proc_info:
470 .long 0x4105a200 @ ARM 1020TE (Architecture v5TE)
471 .long 0xff0ffff0
472 .long PMD_TYPE_SECT | \
473 PMD_BIT4 | \
474 PMD_SECT_AP_WRITE | \
475 PMD_SECT_AP_READ
476 .long PMD_TYPE_SECT | \
477 PMD_BIT4 | \
478 PMD_SECT_AP_WRITE | \
479 PMD_SECT_AP_READ
480 b __arm1020e_setup
481 .long cpu_arch_name
482 .long cpu_elf_name
483 .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_EDSP
484 .long cpu_arm1020e_name
485 .long arm1020e_processor_functions
486 .long v4wbi_tlb_fns
487 .long v4wb_user_fns
488 .long arm1020e_cache_fns
489 .size __arm1020e_proc_info, . - __arm1020e_proc_info