| blob | 9dccd9a365b38c2c7c1261a280d55f4f4e7d5af4 |
1 /*
2 * linux/arch/arm/mm/arm925.S: MMU functions for ARM925
3 *
4 * Copyright (C) 1999,2000 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd.
6 * Copyright (C) 2002 RidgeRun, Inc.
7 * Copyright (C) 2002-2003 MontaVista Software, Inc.
8 *
9 * Update for Linux-2.6 and cache flush improvements
10 * Copyright (C) 2004 Nokia Corporation by Tony Lindgren <tony@atomide.com>
11 *
12 * hacked for non-paged-MM by Hyok S. Choi, 2004.
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
27 *
28 *
29 * These are the low level assembler for performing cache and TLB
30 * functions on the arm925.
31 *
32 * CONFIG_CPU_ARM925_CPU_IDLE -> nohlt
33 *
34 * Some additional notes based on deciphering the TI TRM on OMAP-5910:
35 *
36 * NOTE1: The TI925T Configuration Register bit "D-cache clean and flush
37 * entry mode" must be 0 to flush the entries in both segments
38 * at once. This is the default value. See TRM 2-20 and 2-24 for
39 * more information.
40 *
41 * NOTE2: Default is the "D-cache clean and flush entry mode". It looks
42 * like the "Transparent mode" must be on for partial cache flushes
43 * to work in this mode. This mode only works with 16-bit external
44 * memory. See TRM 2-24 for more information.
45 *
46 * NOTE3: Write-back cache flushing seems to be flakey with devices using
47 * direct memory access, such as USB OHCI. The workaround is to use
48 * write-through cache with CONFIG_CPU_DCACHE_WRITETHROUGH (this is
49 * the default for OMAP-1510).
50 */
52 #include <linux/linkage.h>
53 #include <linux/init.h>
54 #include <asm/assembler.h>
55 #include <asm/hwcap.h>
56 #include <asm/pgtable-hwdef.h>
57 #include <asm/pgtable.h>
58 #include <asm/page.h>
59 #include <asm/ptrace.h>
60 #include "proc-macros.S"
62 /*
63 * The size of one data cache line.
64 */
65 #define CACHE_DLINESIZE 16
67 /*
68 * The number of data cache segments.
69 */
70 #define CACHE_DSEGMENTS 2
72 /*
73 * The number of lines in a cache segment.
74 */
75 #define CACHE_DENTRIES 256
77 /*
78 * This is the size at which it becomes more efficient to
79 * clean the whole cache, rather than using the individual
80 * cache line maintenance instructions.
81 */
82 #define CACHE_DLIMIT 8192
84 .text
85 /*
86 * cpu_arm925_proc_init()
87 */
88 ENTRY(cpu_arm925_proc_init)
89 mov pc, lr
91 /*
92 * cpu_arm925_proc_fin()
93 */
94 ENTRY(cpu_arm925_proc_fin)
95 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
96 bic r0, r0, #0x1000 @ ...i............
97 bic r0, r0, #0x000e @ ............wca.
98 mcr p15, 0, r0, c1, c0, 0 @ disable caches
99 mov pc, lr
101 /*
102 * cpu_arm925_reset(loc)
103 *
104 * Perform a soft reset of the system. Put the CPU into the
105 * same state as it would be if it had been reset, and branch
106 * to what would be the reset vector.
107 *
108 * loc: location to jump to for soft reset
109 */
110 .align 5
111 .pushsection .idmap.text, "ax"
112 ENTRY(cpu_arm925_reset)
113 /* Send software reset to MPU and DSP */
114 mov ip, #0xff000000
115 orr ip, ip, #0x00fe0000
116 orr ip, ip, #0x0000ce00
117 mov r4, #1
118 strh r4, [ip, #0x10]
119 ENDPROC(cpu_arm925_reset)
120 .popsection
122 mov ip, #0
123 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
124 mcr p15, 0, ip, c7, c10, 4 @ drain WB
125 #ifdef CONFIG_MMU
126 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
127 #endif
128 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
129 bic ip, ip, #0x000f @ ............wcam
130 bic ip, ip, #0x1100 @ ...i...s........
131 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
132 mov pc, r0
134 /*
135 * cpu_arm925_do_idle()
136 *
137 * Called with IRQs disabled
138 */
139 .align 10
140 ENTRY(cpu_arm925_do_idle)
141 mov r0, #0
142 mrc p15, 0, r1, c1, c0, 0 @ Read control register
143 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
144 bic r2, r1, #1 << 12
145 mcr p15, 0, r2, c1, c0, 0 @ Disable I cache
146 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
147 mcr p15, 0, r1, c1, c0, 0 @ Restore ICache enable
148 mov pc, lr
150 /*
151 * flush_icache_all()
152 *
153 * Unconditionally clean and invalidate the entire icache.
154 */
155 ENTRY(arm925_flush_icache_all)
156 mov r0, #0
157 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
158 mov pc, lr
159 ENDPROC(arm925_flush_icache_all)
161 /*
162 * flush_user_cache_all()
163 *
164 * Clean and invalidate all cache entries in a particular
165 * address space.
166 */
167 ENTRY(arm925_flush_user_cache_all)
168 /* FALLTHROUGH */
170 /*
171 * flush_kern_cache_all()
172 *
173 * Clean and invalidate the entire cache.
174 */
175 ENTRY(arm925_flush_kern_cache_all)
176 mov r2, #VM_EXEC
177 mov ip, #0
178 __flush_whole_cache:
179 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
180 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
181 #else
182 /* Flush entries in both segments at once, see NOTE1 above */
183 mov r3, #(CACHE_DENTRIES - 1) << 4 @ 256 entries in segment
184 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
185 subs r3, r3, #1 << 4
186 bcs 2b @ entries 255 to 0
187 #endif
188 tst r2, #VM_EXEC
189 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
190 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
191 mov pc, lr
193 /*
194 * flush_user_cache_range(start, end, flags)
195 *
196 * Clean and invalidate a range of cache entries in the
197 * specified address range.
198 *
199 * - start - start address (inclusive)
200 * - end - end address (exclusive)
201 * - flags - vm_flags describing address space
202 */
203 ENTRY(arm925_flush_user_cache_range)
204 mov ip, #0
205 sub r3, r1, r0 @ calculate total size
206 cmp r3, #CACHE_DLIMIT
207 bgt __flush_whole_cache
208 1: tst r2, #VM_EXEC
209 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
210 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
211 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
212 add r0, r0, #CACHE_DLINESIZE
213 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
214 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
215 add r0, r0, #CACHE_DLINESIZE
216 #else
217 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
218 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
219 add r0, r0, #CACHE_DLINESIZE
220 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
221 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
222 add r0, r0, #CACHE_DLINESIZE
223 #endif
224 cmp r0, r1
225 blo 1b
226 tst r2, #VM_EXEC
227 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
228 mov pc, lr
230 /*
231 * coherent_kern_range(start, end)
232 *
233 * Ensure coherency between the Icache and the Dcache in the
234 * region described by start, end. If you have non-snooping
235 * Harvard caches, you need to implement this function.
236 *
237 * - start - virtual start address
238 * - end - virtual end address
239 */
240 ENTRY(arm925_coherent_kern_range)
241 /* FALLTHROUGH */
243 /*
244 * coherent_user_range(start, end)
245 *
246 * Ensure coherency between the Icache and the Dcache in the
247 * region described by start, end. If you have non-snooping
248 * Harvard caches, you need to implement this function.
249 *
250 * - start - virtual start address
251 * - end - virtual end address
252 */
253 ENTRY(arm925_coherent_user_range)
254 bic r0, r0, #CACHE_DLINESIZE - 1
255 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
256 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
257 add r0, r0, #CACHE_DLINESIZE
258 cmp r0, r1
259 blo 1b
260 mcr p15, 0, r0, c7, c10, 4 @ drain WB
261 mov pc, lr
263 /*
264 * flush_kern_dcache_area(void *addr, size_t size)
265 *
266 * Ensure no D cache aliasing occurs, either with itself or
267 * the I cache
268 *
269 * - addr - kernel address
270 * - size - region size
271 */
272 ENTRY(arm925_flush_kern_dcache_area)
273 add r1, r0, r1
274 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
275 add r0, r0, #CACHE_DLINESIZE
276 cmp r0, r1
277 blo 1b
278 mov r0, #0
279 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
280 mcr p15, 0, r0, c7, c10, 4 @ drain WB
281 mov pc, lr
283 /*
284 * dma_inv_range(start, end)
285 *
286 * Invalidate (discard) the specified virtual address range.
287 * May not write back any entries. If 'start' or 'end'
288 * are not cache line aligned, those lines must be written
289 * back.
290 *
291 * - start - virtual start address
292 * - end - virtual end address
293 *
294 * (same as v4wb)
295 */
296 arm925_dma_inv_range:
297 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
298 tst r0, #CACHE_DLINESIZE - 1
299 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
300 tst r1, #CACHE_DLINESIZE - 1
301 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
302 #endif
303 bic r0, r0, #CACHE_DLINESIZE - 1
304 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
305 add r0, r0, #CACHE_DLINESIZE
306 cmp r0, r1
307 blo 1b
308 mcr p15, 0, r0, c7, c10, 4 @ drain WB
309 mov pc, lr
311 /*
312 * dma_clean_range(start, end)
313 *
314 * Clean the specified virtual address range.
315 *
316 * - start - virtual start address
317 * - end - virtual end address
318 *
319 * (same as v4wb)
320 */
321 arm925_dma_clean_range:
322 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
323 bic r0, r0, #CACHE_DLINESIZE - 1
324 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
325 add r0, r0, #CACHE_DLINESIZE
326 cmp r0, r1
327 blo 1b
328 #endif
329 mcr p15, 0, r0, c7, c10, 4 @ drain WB
330 mov pc, lr
332 /*
333 * dma_flush_range(start, end)
334 *
335 * Clean and invalidate the specified virtual address range.
336 *
337 * - start - virtual start address
338 * - end - virtual end address
339 */
340 ENTRY(arm925_dma_flush_range)
341 bic r0, r0, #CACHE_DLINESIZE - 1
342 1:
343 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
344 mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
345 #else
346 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
347 #endif
348 add r0, r0, #CACHE_DLINESIZE
349 cmp r0, r1
350 blo 1b
351 mcr p15, 0, r0, c7, c10, 4 @ drain WB
352 mov pc, lr
354 /*
355 * dma_map_area(start, size, dir)
356 * - start - kernel virtual start address
357 * - size - size of region
358 * - dir - DMA direction
359 */
360 ENTRY(arm925_dma_map_area)
361 add r1, r1, r0
362 cmp r2, #DMA_TO_DEVICE
363 beq arm925_dma_clean_range
364 bcs arm925_dma_inv_range
365 b arm925_dma_flush_range
366 ENDPROC(arm925_dma_map_area)
368 /*
369 * dma_unmap_area(start, size, dir)
370 * - start - kernel virtual start address
371 * - size - size of region
372 * - dir - DMA direction
373 */
374 ENTRY(arm925_dma_unmap_area)
375 mov pc, lr
376 ENDPROC(arm925_dma_unmap_area)
378 @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
379 define_cache_functions arm925
381 ENTRY(cpu_arm925_dcache_clean_area)
382 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
383 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
384 add r0, r0, #CACHE_DLINESIZE
385 subs r1, r1, #CACHE_DLINESIZE
386 bhi 1b
387 #endif
388 mcr p15, 0, r0, c7, c10, 4 @ drain WB
389 mov pc, lr
391 /* =============================== PageTable ============================== */
393 /*
394 * cpu_arm925_switch_mm(pgd)
395 *
396 * Set the translation base pointer to be as described by pgd.
397 *
398 * pgd: new page tables
399 */
400 .align 5
401 ENTRY(cpu_arm925_switch_mm)
402 #ifdef CONFIG_MMU
403 mov ip, #0
404 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
405 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
406 #else
407 /* Flush entries in bothe segments at once, see NOTE1 above */
408 mov r3, #(CACHE_DENTRIES - 1) << 4 @ 256 entries in segment
409 2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index
410 subs r3, r3, #1 << 4
411 bcs 2b @ entries 255 to 0
412 #endif
413 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
414 mcr p15, 0, ip, c7, c10, 4 @ drain WB
415 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
416 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
417 #endif
418 mov pc, lr
420 /*
421 * cpu_arm925_set_pte_ext(ptep, pte, ext)
422 *
423 * Set a PTE and flush it out
424 */
425 .align 5
426 ENTRY(cpu_arm925_set_pte_ext)
427 #ifdef CONFIG_MMU
428 armv3_set_pte_ext
429 mov r0, r0
430 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
431 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
432 #endif
433 mcr p15, 0, r0, c7, c10, 4 @ drain WB
434 #endif /* CONFIG_MMU */
435 mov pc, lr
437 __CPUINIT
439 .type __arm925_setup, #function
440 __arm925_setup:
441 mov r0, #0
442 #if defined(CONFIG_CPU_ICACHE_STREAMING_DISABLE)
443 orr r0,r0,#1 << 7
444 #endif
446 /* Transparent on, D-cache clean & flush mode. See NOTE2 above */
447 orr r0,r0,#1 << 1 @ transparent mode on
448 mcr p15, 0, r0, c15, c1, 0 @ write TI config register
450 mov r0, #0
451 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
452 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
453 #ifdef CONFIG_MMU
454 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
455 #endif
457 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
458 mov r0, #4 @ disable write-back on caches explicitly
459 mcr p15, 7, r0, c15, c0, 0
460 #endif
462 adr r5, arm925_crval
463 ldmia r5, {r5, r6}
464 mrc p15, 0, r0, c1, c0 @ get control register v4
465 bic r0, r0, r5
466 orr r0, r0, r6
467 #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
468 orr r0, r0, #0x4000 @ .1.. .... .... ....
469 #endif
470 mov pc, lr
471 .size __arm925_setup, . - __arm925_setup
473 /*
474 * R
475 * .RVI ZFRS BLDP WCAM
476 * .011 0001 ..11 1101
477 *
478 */
479 .type arm925_crval, #object
480 arm925_crval:
481 crval clear=0x00007f3f, mmuset=0x0000313d, ucset=0x00001130
483 __INITDATA
484 @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
485 define_processor_functions arm925, dabort=v4t_early_abort, pabort=legacy_pabort
487 .section ".rodata"
489 string cpu_arch_name, "armv4t"
490 string cpu_elf_name, "v4"
491 string cpu_arm925_name, "ARM925T"
493 .align
495 .section ".proc.info.init", #alloc, #execinstr
497 .macro arm925_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req, cache
498 .type __\name\()_proc_info,#object
499 __\name\()_proc_info:
500 .long \cpu_val
501 .long \cpu_mask
502 .long PMD_TYPE_SECT | \
503 PMD_BIT4 | \
504 PMD_SECT_AP_WRITE | \
505 PMD_SECT_AP_READ
506 .long PMD_TYPE_SECT | \
507 PMD_BIT4 | \
508 PMD_SECT_AP_WRITE | \
509 PMD_SECT_AP_READ
510 b __arm925_setup
511 .long cpu_arch_name
512 .long cpu_elf_name
513 .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB
514 .long cpu_arm925_name
515 .long arm925_processor_functions
516 .long v4wbi_tlb_fns
517 .long v4wb_user_fns
518 .long arm925_cache_fns
519 .size __\name\()_proc_info, . - __\name\()_proc_info
520 .endm
522 arm925_proc_info arm925, 0x54029250, 0xfffffff0, cpu_arm925_name
523 arm925_proc_info arm915, 0x54029150, 0xfffffff0, cpu_arm925_name