| blob | 7cd07b42ca1a505c9a9bfbb3802277336537a514 |
1 /*
2 * This file contains miscellaneous low-level functions.
3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 *
5 * Largely rewritten by Cort Dougan (cort@cs.nmt.edu)
6 * and Paul Mackerras.
7 *
8 * kexec bits:
9 * Copyright (C) 2002-2003 Eric Biederman <ebiederm@xmission.com>
10 * GameCube/ppc32 port Copyright (C) 2004 Albert Herranz
11 * PPC44x port. Copyright (C) 2011, IBM Corporation
12 * Author: Suzuki Poulose <suzuki@in.ibm.com>
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License
16 * as published by the Free Software Foundation; either version
17 * 2 of the License, or (at your option) any later version.
18 *
19 */
21 #include <linux/sys.h>
22 #include <asm/unistd.h>
23 #include <asm/errno.h>
24 #include <asm/reg.h>
25 #include <asm/page.h>
26 #include <asm/cache.h>
27 #include <asm/cputable.h>
28 #include <asm/mmu.h>
29 #include <asm/ppc_asm.h>
30 #include <asm/thread_info.h>
31 #include <asm/asm-offsets.h>
32 #include <asm/processor.h>
33 #include <asm/kexec.h>
34 #include <asm/bug.h>
35 #include <asm/ptrace.h>
37 .text
39 _GLOBAL(call_do_softirq)
40 mflr r0
41 stw r0,4(r1)
42 stwu r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r3)
43 mr r1,r3
44 bl __do_softirq
45 lwz r1,0(r1)
46 lwz r0,4(r1)
47 mtlr r0
48 blr
50 _GLOBAL(call_handle_irq)
51 mflr r0
52 stw r0,4(r1)
53 mtctr r6
54 stwu r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r5)
55 mr r1,r5
56 bctrl
57 lwz r1,0(r1)
58 lwz r0,4(r1)
59 mtlr r0
60 blr
62 /*
63 * This returns the high 64 bits of the product of two 64-bit numbers.
64 */
65 _GLOBAL(mulhdu)
66 cmpwi r6,0
67 cmpwi cr1,r3,0
68 mr r10,r4
69 mulhwu r4,r4,r5
70 beq 1f
71 mulhwu r0,r10,r6
72 mullw r7,r10,r5
73 addc r7,r0,r7
74 addze r4,r4
75 1: beqlr cr1 /* all done if high part of A is 0 */
76 mr r10,r3
77 mullw r9,r3,r5
78 mulhwu r3,r3,r5
79 beq 2f
80 mullw r0,r10,r6
81 mulhwu r8,r10,r6
82 addc r7,r0,r7
83 adde r4,r4,r8
84 addze r3,r3
85 2: addc r4,r4,r9
86 addze r3,r3
87 blr
89 /*
90 * sub_reloc_offset(x) returns x - reloc_offset().
91 */
92 _GLOBAL(sub_reloc_offset)
93 mflr r0
94 bl 1f
95 1: mflr r5
96 lis r4,1b@ha
97 addi r4,r4,1b@l
98 subf r5,r4,r5
99 subf r3,r5,r3
100 mtlr r0
101 blr
103 /*
104 * reloc_got2 runs through the .got2 section adding an offset
105 * to each entry.
106 */
107 _GLOBAL(reloc_got2)
108 mflr r11
109 lis r7,__got2_start@ha
110 addi r7,r7,__got2_start@l
111 lis r8,__got2_end@ha
112 addi r8,r8,__got2_end@l
113 subf r8,r7,r8
114 srwi. r8,r8,2
115 beqlr
116 mtctr r8
117 bl 1f
118 1: mflr r0
119 lis r4,1b@ha
120 addi r4,r4,1b@l
121 subf r0,r4,r0
122 add r7,r0,r7
123 2: lwz r0,0(r7)
124 add r0,r0,r3
125 stw r0,0(r7)
126 addi r7,r7,4
127 bdnz 2b
128 mtlr r11
129 blr
131 /*
132 * call_setup_cpu - call the setup_cpu function for this cpu
133 * r3 = data offset, r24 = cpu number
134 *
135 * Setup function is called with:
136 * r3 = data offset
137 * r4 = ptr to CPU spec (relocated)
138 */
139 _GLOBAL(call_setup_cpu)
140 addis r4,r3,cur_cpu_spec@ha
141 addi r4,r4,cur_cpu_spec@l
142 lwz r4,0(r4)
143 add r4,r4,r3
144 lwz r5,CPU_SPEC_SETUP(r4)
145 cmpwi 0,r5,0
146 add r5,r5,r3
147 beqlr
148 mtctr r5
149 bctr
151 #if defined(CONFIG_CPU_FREQ_PMAC) && defined(CONFIG_6xx)
153 /* This gets called by via-pmu.c to switch the PLL selection
154 * on 750fx CPU. This function should really be moved to some
155 * other place (as most of the cpufreq code in via-pmu
156 */
157 _GLOBAL(low_choose_750fx_pll)
158 /* Clear MSR:EE */
159 mfmsr r7
160 rlwinm r0,r7,0,17,15
161 mtmsr r0
163 /* If switching to PLL1, disable HID0:BTIC */
164 cmplwi cr0,r3,0
165 beq 1f
166 mfspr r5,SPRN_HID0
167 rlwinm r5,r5,0,27,25
168 sync
169 mtspr SPRN_HID0,r5
170 isync
171 sync
173 1:
174 /* Calc new HID1 value */
175 mfspr r4,SPRN_HID1 /* Build a HID1:PS bit from parameter */
176 rlwinm r5,r3,16,15,15 /* Clear out HID1:PS from value read */
177 rlwinm r4,r4,0,16,14 /* Could have I used rlwimi here ? */
178 or r4,r4,r5
179 mtspr SPRN_HID1,r4
181 /* Store new HID1 image */
182 rlwinm r6,r1,0,0,(31-THREAD_SHIFT)
183 lwz r6,TI_CPU(r6)
184 slwi r6,r6,2
185 addis r6,r6,nap_save_hid1@ha
186 stw r4,nap_save_hid1@l(r6)
188 /* If switching to PLL0, enable HID0:BTIC */
189 cmplwi cr0,r3,0
190 bne 1f
191 mfspr r5,SPRN_HID0
192 ori r5,r5,HID0_BTIC
193 sync
194 mtspr SPRN_HID0,r5
195 isync
196 sync
198 1:
199 /* Return */
200 mtmsr r7
201 blr
203 _GLOBAL(low_choose_7447a_dfs)
204 /* Clear MSR:EE */
205 mfmsr r7
206 rlwinm r0,r7,0,17,15
207 mtmsr r0
209 /* Calc new HID1 value */
210 mfspr r4,SPRN_HID1
211 insrwi r4,r3,1,9 /* insert parameter into bit 9 */
212 sync
213 mtspr SPRN_HID1,r4
214 sync
215 isync
217 /* Return */
218 mtmsr r7
219 blr
221 #endif /* CONFIG_CPU_FREQ_PMAC && CONFIG_6xx */
223 /*
224 * complement mask on the msr then "or" some values on.
225 * _nmask_and_or_msr(nmask, value_to_or)
226 */
227 _GLOBAL(_nmask_and_or_msr)
228 mfmsr r0 /* Get current msr */
229 andc r0,r0,r3 /* And off the bits set in r3 (first parm) */
230 or r0,r0,r4 /* Or on the bits in r4 (second parm) */
231 SYNC /* Some chip revs have problems here... */
232 mtmsr r0 /* Update machine state */
233 isync
234 blr /* Done */
236 #ifdef CONFIG_40x
238 /*
239 * Do an IO access in real mode
240 */
241 _GLOBAL(real_readb)
242 mfmsr r7
243 ori r0,r7,MSR_DR
244 xori r0,r0,MSR_DR
245 sync
246 mtmsr r0
247 sync
248 isync
249 lbz r3,0(r3)
250 sync
251 mtmsr r7
252 sync
253 isync
254 blr
256 /*
257 * Do an IO access in real mode
258 */
259 _GLOBAL(real_writeb)
260 mfmsr r7
261 ori r0,r7,MSR_DR
262 xori r0,r0,MSR_DR
263 sync
264 mtmsr r0
265 sync
266 isync
267 stb r3,0(r4)
268 sync
269 mtmsr r7
270 sync
271 isync
272 blr
274 #endif /* CONFIG_40x */
277 /*
278 * Flush instruction cache.
279 * This is a no-op on the 601.
280 */
281 _GLOBAL(flush_instruction_cache)
282 #if defined(CONFIG_8xx)
283 isync
284 lis r5, IDC_INVALL@h
285 mtspr SPRN_IC_CST, r5
286 #elif defined(CONFIG_4xx)
287 #ifdef CONFIG_403GCX
288 li r3, 512
289 mtctr r3
290 lis r4, KERNELBASE@h
291 1: iccci 0, r4
292 addi r4, r4, 16
293 bdnz 1b
294 #else
295 lis r3, KERNELBASE@h
296 iccci 0,r3
297 #endif
298 #elif CONFIG_FSL_BOOKE
299 BEGIN_FTR_SECTION
300 mfspr r3,SPRN_L1CSR0
301 ori r3,r3,L1CSR0_CFI|L1CSR0_CLFC
302 /* msync; isync recommended here */
303 mtspr SPRN_L1CSR0,r3
304 isync
305 blr
306 END_FTR_SECTION_IFSET(CPU_FTR_UNIFIED_ID_CACHE)
307 mfspr r3,SPRN_L1CSR1
308 ori r3,r3,L1CSR1_ICFI|L1CSR1_ICLFR
309 mtspr SPRN_L1CSR1,r3
310 #else
311 mfspr r3,SPRN_PVR
312 rlwinm r3,r3,16,16,31
313 cmpwi 0,r3,1
314 beqlr /* for 601, do nothing */
315 /* 603/604 processor - use invalidate-all bit in HID0 */
316 mfspr r3,SPRN_HID0
317 ori r3,r3,HID0_ICFI
318 mtspr SPRN_HID0,r3
319 #endif /* CONFIG_8xx/4xx */
320 isync
321 blr
323 /*
324 * Write any modified data cache blocks out to memory
325 * and invalidate the corresponding instruction cache blocks.
326 * This is a no-op on the 601.
327 *
328 * flush_icache_range(unsigned long start, unsigned long stop)
329 */
330 _KPROBE(__flush_icache_range)
331 BEGIN_FTR_SECTION
332 blr /* for 601, do nothing */
333 END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
334 li r5,L1_CACHE_BYTES-1
335 andc r3,r3,r5
336 subf r4,r3,r4
337 add r4,r4,r5
338 srwi. r4,r4,L1_CACHE_SHIFT
339 beqlr
340 mtctr r4
341 mr r6,r3
342 1: dcbst 0,r3
343 addi r3,r3,L1_CACHE_BYTES
344 bdnz 1b
345 sync /* wait for dcbst's to get to ram */
346 #ifndef CONFIG_44x
347 mtctr r4
348 2: icbi 0,r6
349 addi r6,r6,L1_CACHE_BYTES
350 bdnz 2b
351 #else
352 /* Flash invalidate on 44x because we are passed kmapped addresses and
353 this doesn't work for userspace pages due to the virtually tagged
354 icache. Sigh. */
355 iccci 0, r0
356 #endif
357 sync /* additional sync needed on g4 */
358 isync
359 blr
360 /*
361 * Write any modified data cache blocks out to memory.
362 * Does not invalidate the corresponding cache lines (especially for
363 * any corresponding instruction cache).
364 *
365 * clean_dcache_range(unsigned long start, unsigned long stop)
366 */
367 _GLOBAL(clean_dcache_range)
368 li r5,L1_CACHE_BYTES-1
369 andc r3,r3,r5
370 subf r4,r3,r4
371 add r4,r4,r5
372 srwi. r4,r4,L1_CACHE_SHIFT
373 beqlr
374 mtctr r4
376 1: dcbst 0,r3
377 addi r3,r3,L1_CACHE_BYTES
378 bdnz 1b
379 sync /* wait for dcbst's to get to ram */
380 blr
382 /*
383 * Write any modified data cache blocks out to memory and invalidate them.
384 * Does not invalidate the corresponding instruction cache blocks.
385 *
386 * flush_dcache_range(unsigned long start, unsigned long stop)
387 */
388 _GLOBAL(flush_dcache_range)
389 li r5,L1_CACHE_BYTES-1
390 andc r3,r3,r5
391 subf r4,r3,r4
392 add r4,r4,r5
393 srwi. r4,r4,L1_CACHE_SHIFT
394 beqlr
395 mtctr r4
397 1: dcbf 0,r3
398 addi r3,r3,L1_CACHE_BYTES
399 bdnz 1b
400 sync /* wait for dcbst's to get to ram */
401 blr
403 /*
404 * Like above, but invalidate the D-cache. This is used by the 8xx
405 * to invalidate the cache so the PPC core doesn't get stale data
406 * from the CPM (no cache snooping here :-).
407 *
408 * invalidate_dcache_range(unsigned long start, unsigned long stop)
409 */
410 _GLOBAL(invalidate_dcache_range)
411 li r5,L1_CACHE_BYTES-1
412 andc r3,r3,r5
413 subf r4,r3,r4
414 add r4,r4,r5
415 srwi. r4,r4,L1_CACHE_SHIFT
416 beqlr
417 mtctr r4
419 1: dcbi 0,r3
420 addi r3,r3,L1_CACHE_BYTES
421 bdnz 1b
422 sync /* wait for dcbi's to get to ram */
423 blr
425 /*
426 * Flush a particular page from the data cache to RAM.
427 * Note: this is necessary because the instruction cache does *not*
428 * snoop from the data cache.
429 * This is a no-op on the 601 which has a unified cache.
430 *
431 * void __flush_dcache_icache(void *page)
432 */
433 _GLOBAL(__flush_dcache_icache)
434 BEGIN_FTR_SECTION
435 blr
436 END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
437 rlwinm r3,r3,0,0,31-PAGE_SHIFT /* Get page base address */
438 li r4,PAGE_SIZE/L1_CACHE_BYTES /* Number of lines in a page */
439 mtctr r4
440 mr r6,r3
441 0: dcbst 0,r3 /* Write line to ram */
442 addi r3,r3,L1_CACHE_BYTES
443 bdnz 0b
444 sync
445 #ifdef CONFIG_44x
446 /* We don't flush the icache on 44x. Those have a virtual icache
447 * and we don't have access to the virtual address here (it's
448 * not the page vaddr but where it's mapped in user space). The
449 * flushing of the icache on these is handled elsewhere, when
450 * a change in the address space occurs, before returning to
451 * user space
452 */
453 BEGIN_MMU_FTR_SECTION
454 blr
455 END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_44x)
456 #endif /* CONFIG_44x */
457 mtctr r4
458 1: icbi 0,r6
459 addi r6,r6,L1_CACHE_BYTES
460 bdnz 1b
461 sync
462 isync
463 blr
465 #ifndef CONFIG_BOOKE
466 /*
467 * Flush a particular page from the data cache to RAM, identified
468 * by its physical address. We turn off the MMU so we can just use
469 * the physical address (this may be a highmem page without a kernel
470 * mapping).
471 *
472 * void __flush_dcache_icache_phys(unsigned long physaddr)
473 */
474 _GLOBAL(__flush_dcache_icache_phys)
475 BEGIN_FTR_SECTION
476 blr /* for 601, do nothing */
477 END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
478 mfmsr r10
479 rlwinm r0,r10,0,28,26 /* clear DR */
480 mtmsr r0
481 isync
482 rlwinm r3,r3,0,0,31-PAGE_SHIFT /* Get page base address */
483 li r4,PAGE_SIZE/L1_CACHE_BYTES /* Number of lines in a page */
484 mtctr r4
485 mr r6,r3
486 0: dcbst 0,r3 /* Write line to ram */
487 addi r3,r3,L1_CACHE_BYTES
488 bdnz 0b
489 sync
490 mtctr r4
491 1: icbi 0,r6
492 addi r6,r6,L1_CACHE_BYTES
493 bdnz 1b
494 sync
495 mtmsr r10 /* restore DR */
496 isync
497 blr
498 #endif /* CONFIG_BOOKE */
500 /*
501 * Clear pages using the dcbz instruction, which doesn't cause any
502 * memory traffic (except to write out any cache lines which get
503 * displaced). This only works on cacheable memory.
504 *
505 * void clear_pages(void *page, int order) ;
506 */
507 _GLOBAL(clear_pages)
508 li r0,PAGE_SIZE/L1_CACHE_BYTES
509 slw r0,r0,r4
510 mtctr r0
511 1: dcbz 0,r3
512 addi r3,r3,L1_CACHE_BYTES
513 bdnz 1b
514 blr
516 /*
517 * Copy a whole page. We use the dcbz instruction on the destination
518 * to reduce memory traffic (it eliminates the unnecessary reads of
519 * the destination into cache). This requires that the destination
520 * is cacheable.
521 */
522 #define COPY_16_BYTES \
523 lwz r6,4(r4); \
524 lwz r7,8(r4); \
525 lwz r8,12(r4); \
526 lwzu r9,16(r4); \
527 stw r6,4(r3); \
528 stw r7,8(r3); \
529 stw r8,12(r3); \
530 stwu r9,16(r3)
532 _GLOBAL(copy_page)
533 addi r3,r3,-4
534 addi r4,r4,-4
536 li r5,4
538 #if MAX_COPY_PREFETCH > 1
539 li r0,MAX_COPY_PREFETCH
540 li r11,4
541 mtctr r0
542 11: dcbt r11,r4
543 addi r11,r11,L1_CACHE_BYTES
544 bdnz 11b
545 #else /* MAX_COPY_PREFETCH == 1 */
546 dcbt r5,r4
547 li r11,L1_CACHE_BYTES+4
548 #endif /* MAX_COPY_PREFETCH */
549 li r0,PAGE_SIZE/L1_CACHE_BYTES - MAX_COPY_PREFETCH
550 crclr 4*cr0+eq
551 2:
552 mtctr r0
553 1:
554 dcbt r11,r4
555 dcbz r5,r3
556 COPY_16_BYTES
557 #if L1_CACHE_BYTES >= 32
558 COPY_16_BYTES
559 #if L1_CACHE_BYTES >= 64
560 COPY_16_BYTES
561 COPY_16_BYTES
562 #if L1_CACHE_BYTES >= 128
563 COPY_16_BYTES
564 COPY_16_BYTES
565 COPY_16_BYTES
566 COPY_16_BYTES
567 #endif
568 #endif
569 #endif
570 bdnz 1b
571 beqlr
572 crnot 4*cr0+eq,4*cr0+eq
573 li r0,MAX_COPY_PREFETCH
574 li r11,4
575 b 2b
577 /*
578 * void atomic_clear_mask(atomic_t mask, atomic_t *addr)
579 * void atomic_set_mask(atomic_t mask, atomic_t *addr);
580 */
581 _GLOBAL(atomic_clear_mask)
582 10: lwarx r5,0,r4
583 andc r5,r5,r3
584 PPC405_ERR77(0,r4)
585 stwcx. r5,0,r4
586 bne- 10b
587 blr
588 _GLOBAL(atomic_set_mask)
589 10: lwarx r5,0,r4
590 or r5,r5,r3
591 PPC405_ERR77(0,r4)
592 stwcx. r5,0,r4
593 bne- 10b
594 blr
596 /*
597 * Extended precision shifts.
598 *
599 * Updated to be valid for shift counts from 0 to 63 inclusive.
600 * -- Gabriel
601 *
602 * R3/R4 has 64 bit value
603 * R5 has shift count
604 * result in R3/R4
605 *
606 * ashrdi3: arithmetic right shift (sign propagation)
607 * lshrdi3: logical right shift
608 * ashldi3: left shift
609 */
610 _GLOBAL(__ashrdi3)
611 subfic r6,r5,32
612 srw r4,r4,r5 # LSW = count > 31 ? 0 : LSW >> count
613 addi r7,r5,32 # could be xori, or addi with -32
614 slw r6,r3,r6 # t1 = count > 31 ? 0 : MSW << (32-count)
615 rlwinm r8,r7,0,32 # t3 = (count < 32) ? 32 : 0
616 sraw r7,r3,r7 # t2 = MSW >> (count-32)
617 or r4,r4,r6 # LSW |= t1
618 slw r7,r7,r8 # t2 = (count < 32) ? 0 : t2
619 sraw r3,r3,r5 # MSW = MSW >> count
620 or r4,r4,r7 # LSW |= t2
621 blr
623 _GLOBAL(__ashldi3)
624 subfic r6,r5,32
625 slw r3,r3,r5 # MSW = count > 31 ? 0 : MSW << count
626 addi r7,r5,32 # could be xori, or addi with -32
627 srw r6,r4,r6 # t1 = count > 31 ? 0 : LSW >> (32-count)
628 slw r7,r4,r7 # t2 = count < 32 ? 0 : LSW << (count-32)
629 or r3,r3,r6 # MSW |= t1
630 slw r4,r4,r5 # LSW = LSW << count
631 or r3,r3,r7 # MSW |= t2
632 blr
634 _GLOBAL(__lshrdi3)
635 subfic r6,r5,32
636 srw r4,r4,r5 # LSW = count > 31 ? 0 : LSW >> count
637 addi r7,r5,32 # could be xori, or addi with -32
638 slw r6,r3,r6 # t1 = count > 31 ? 0 : MSW << (32-count)
639 srw r7,r3,r7 # t2 = count < 32 ? 0 : MSW >> (count-32)
640 or r4,r4,r6 # LSW |= t1
641 srw r3,r3,r5 # MSW = MSW >> count
642 or r4,r4,r7 # LSW |= t2
643 blr
645 /*
646 * 64-bit comparison: __ucmpdi2(u64 a, u64 b)
647 * Returns 0 if a < b, 1 if a == b, 2 if a > b.
648 */
649 _GLOBAL(__ucmpdi2)
650 cmplw r3,r5
651 li r3,1
652 bne 1f
653 cmplw r4,r6
654 beqlr
655 1: li r3,0
656 bltlr
657 li r3,2
658 blr
660 _GLOBAL(abs)
661 srawi r4,r3,31
662 xor r3,r3,r4
663 sub r3,r3,r4
664 blr
666 /*
667 * Create a kernel thread
668 * kernel_thread(fn, arg, flags)
669 */
670 _GLOBAL(kernel_thread)
671 stwu r1,-16(r1)
672 stw r30,8(r1)
673 stw r31,12(r1)
674 mr r30,r3 /* function */
675 mr r31,r4 /* argument */
676 ori r3,r5,CLONE_VM /* flags */
677 oris r3,r3,CLONE_UNTRACED>>16
678 li r4,0 /* new sp (unused) */
679 li r0,__NR_clone
680 sc
681 bns+ 1f /* did system call indicate error? */
682 neg r3,r3 /* if so, make return code negative */
683 1: cmpwi 0,r3,0 /* parent or child? */
684 bne 2f /* return if parent */
685 li r0,0 /* make top-level stack frame */
686 stwu r0,-16(r1)
687 mtlr r30 /* fn addr in lr */
688 mr r3,r31 /* load arg and call fn */
689 PPC440EP_ERR42
690 blrl
691 li r0,__NR_exit /* exit if function returns */
692 li r3,0
693 sc
694 2: lwz r30,8(r1)
695 lwz r31,12(r1)
696 addi r1,r1,16
697 blr
699 #ifdef CONFIG_SMP
700 _GLOBAL(start_secondary_resume)
701 /* Reset stack */
702 rlwinm r1,r1,0,0,(31-THREAD_SHIFT) /* current_thread_info() */
703 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
704 li r3,0
705 stw r3,0(r1) /* Zero the stack frame pointer */
706 bl start_secondary
707 b .
708 #endif /* CONFIG_SMP */
710 /*
711 * This routine is just here to keep GCC happy - sigh...
712 */
713 _GLOBAL(__main)
714 blr
716 #ifdef CONFIG_KEXEC
717 /*
718 * Must be relocatable PIC code callable as a C function.
719 */
720 .globl relocate_new_kernel
721 relocate_new_kernel:
722 /* r3 = page_list */
723 /* r4 = reboot_code_buffer */
724 /* r5 = start_address */
726 #ifdef CONFIG_FSL_BOOKE
728 mr r29, r3
729 mr r30, r4
730 mr r31, r5
732 #define ENTRY_MAPPING_KEXEC_SETUP
733 #include "fsl_booke_entry_mapping.S"
734 #undef ENTRY_MAPPING_KEXEC_SETUP
736 mr r3, r29
737 mr r4, r30
738 mr r5, r31
740 li r0, 0
741 #elif defined(CONFIG_44x) && !defined(CONFIG_PPC_47x)
743 /*
744 * Code for setting up 1:1 mapping for PPC440x for KEXEC
745 *
746 * We cannot switch off the MMU on PPC44x.
747 * So we:
748 * 1) Invalidate all the mappings except the one we are running from.
749 * 2) Create a tmp mapping for our code in the other address space(TS) and
750 * jump to it. Invalidate the entry we started in.
751 * 3) Create a 1:1 mapping for 0-2GiB in chunks of 256M in original TS.
752 * 4) Jump to the 1:1 mapping in original TS.
753 * 5) Invalidate the tmp mapping.
754 *
755 * - Based on the kexec support code for FSL BookE
756 * - Doesn't support 47x yet.
757 *
758 */
759 /* Save our parameters */
760 mr r29, r3
761 mr r30, r4
762 mr r31, r5
764 /* Load our MSR_IS and TID to MMUCR for TLB search */
765 mfspr r3,SPRN_PID
766 mfmsr r4
767 andi. r4,r4,MSR_IS@l
768 beq wmmucr
769 oris r3,r3,PPC44x_MMUCR_STS@h
770 wmmucr:
771 mtspr SPRN_MMUCR,r3
772 sync
774 /*
775 * Invalidate all the TLB entries except the current entry
776 * where we are running from
777 */
778 bl 0f /* Find our address */
779 0: mflr r5 /* Make it accessible */
780 tlbsx r23,0,r5 /* Find entry we are in */
781 li r4,0 /* Start at TLB entry 0 */
782 li r3,0 /* Set PAGEID inval value */
783 1: cmpw r23,r4 /* Is this our entry? */
784 beq skip /* If so, skip the inval */
785 tlbwe r3,r4,PPC44x_TLB_PAGEID /* If not, inval the entry */
786 skip:
787 addi r4,r4,1 /* Increment */
788 cmpwi r4,64 /* Are we done? */
789 bne 1b /* If not, repeat */
790 isync
792 /* Create a temp mapping and jump to it */
793 andi. r6, r23, 1 /* Find the index to use */
794 addi r24, r6, 1 /* r24 will contain 1 or 2 */
796 mfmsr r9 /* get the MSR */
797 rlwinm r5, r9, 27, 31, 31 /* Extract the MSR[IS] */
798 xori r7, r5, 1 /* Use the other address space */
800 /* Read the current mapping entries */
801 tlbre r3, r23, PPC44x_TLB_PAGEID
802 tlbre r4, r23, PPC44x_TLB_XLAT
803 tlbre r5, r23, PPC44x_TLB_ATTRIB
805 /* Save our current XLAT entry */
806 mr r25, r4
808 /* Extract the TLB PageSize */
809 li r10, 1 /* r10 will hold PageSize */
810 rlwinm r11, r3, 0, 24, 27 /* bits 24-27 */
812 /* XXX: As of now we use 256M, 4K pages */
813 cmpwi r11, PPC44x_TLB_256M
814 bne tlb_4k
815 rotlwi r10, r10, 28 /* r10 = 256M */
816 b write_out
817 tlb_4k:
818 cmpwi r11, PPC44x_TLB_4K
819 bne default
820 rotlwi r10, r10, 12 /* r10 = 4K */
821 b write_out
822 default:
823 rotlwi r10, r10, 10 /* r10 = 1K */
825 write_out:
826 /*
827 * Write out the tmp 1:1 mapping for this code in other address space
828 * Fixup EPN = RPN , TS=other address space
829 */
830 insrwi r3, r7, 1, 23 /* Bit 23 is TS for PAGEID field */
832 /* Write out the tmp mapping entries */
833 tlbwe r3, r24, PPC44x_TLB_PAGEID
834 tlbwe r4, r24, PPC44x_TLB_XLAT
835 tlbwe r5, r24, PPC44x_TLB_ATTRIB
837 subi r11, r10, 1 /* PageOffset Mask = PageSize - 1 */
838 not r10, r11 /* Mask for PageNum */
840 /* Switch to other address space in MSR */
841 insrwi r9, r7, 1, 26 /* Set MSR[IS] = r7 */
843 bl 1f
844 1: mflr r8
845 addi r8, r8, (2f-1b) /* Find the target offset */
847 /* Jump to the tmp mapping */
848 mtspr SPRN_SRR0, r8
849 mtspr SPRN_SRR1, r9
850 rfi
852 2:
853 /* Invalidate the entry we were executing from */
854 li r3, 0
855 tlbwe r3, r23, PPC44x_TLB_PAGEID
857 /* attribute fields. rwx for SUPERVISOR mode */
858 li r5, 0
859 ori r5, r5, (PPC44x_TLB_SW | PPC44x_TLB_SR | PPC44x_TLB_SX | PPC44x_TLB_G)
861 /* Create 1:1 mapping in 256M pages */
862 xori r7, r7, 1 /* Revert back to Original TS */
864 li r8, 0 /* PageNumber */
865 li r6, 3 /* TLB Index, start at 3 */
867 next_tlb:
868 rotlwi r3, r8, 28 /* Create EPN (bits 0-3) */
869 mr r4, r3 /* RPN = EPN */
870 ori r3, r3, (PPC44x_TLB_VALID | PPC44x_TLB_256M) /* SIZE = 256M, Valid */
871 insrwi r3, r7, 1, 23 /* Set TS from r7 */
873 tlbwe r3, r6, PPC44x_TLB_PAGEID /* PageID field : EPN, V, SIZE */
874 tlbwe r4, r6, PPC44x_TLB_XLAT /* Address translation : RPN */
875 tlbwe r5, r6, PPC44x_TLB_ATTRIB /* Attributes */
877 addi r8, r8, 1 /* Increment PN */
878 addi r6, r6, 1 /* Increment TLB Index */
879 cmpwi r8, 8 /* Are we done ? */
880 bne next_tlb
881 isync
883 /* Jump to the new mapping 1:1 */
884 li r9,0
885 insrwi r9, r7, 1, 26 /* Set MSR[IS] = r7 */
887 bl 1f
888 1: mflr r8
889 and r8, r8, r11 /* Get our offset within page */
890 addi r8, r8, (2f-1b)
892 and r5, r25, r10 /* Get our target PageNum */
893 or r8, r8, r5 /* Target jump address */
895 mtspr SPRN_SRR0, r8
896 mtspr SPRN_SRR1, r9
897 rfi
898 2:
899 /* Invalidate the tmp entry we used */
900 li r3, 0
901 tlbwe r3, r24, PPC44x_TLB_PAGEID
902 sync
904 /* Restore the parameters */
905 mr r3, r29
906 mr r4, r30
907 mr r5, r31
909 li r0, 0
910 #else
911 li r0, 0
913 /*
914 * Set Machine Status Register to a known status,
915 * switch the MMU off and jump to 1: in a single step.
916 */
918 mr r8, r0
919 ori r8, r8, MSR_RI|MSR_ME
920 mtspr SPRN_SRR1, r8
921 addi r8, r4, 1f - relocate_new_kernel
922 mtspr SPRN_SRR0, r8
923 sync
924 rfi
926 1:
927 #endif
928 /* from this point address translation is turned off */
929 /* and interrupts are disabled */
931 /* set a new stack at the bottom of our page... */
932 /* (not really needed now) */
933 addi r1, r4, KEXEC_CONTROL_PAGE_SIZE - 8 /* for LR Save+Back Chain */
934 stw r0, 0(r1)
936 /* Do the copies */
937 li r6, 0 /* checksum */
938 mr r0, r3
939 b 1f
941 0: /* top, read another word for the indirection page */
942 lwzu r0, 4(r3)
944 1:
945 /* is it a destination page? (r8) */
946 rlwinm. r7, r0, 0, 31, 31 /* IND_DESTINATION (1<<0) */
947 beq 2f
949 rlwinm r8, r0, 0, 0, 19 /* clear kexec flags, page align */
950 b 0b
952 2: /* is it an indirection page? (r3) */
953 rlwinm. r7, r0, 0, 30, 30 /* IND_INDIRECTION (1<<1) */
954 beq 2f
956 rlwinm r3, r0, 0, 0, 19 /* clear kexec flags, page align */
957 subi r3, r3, 4
958 b 0b
960 2: /* are we done? */
961 rlwinm. r7, r0, 0, 29, 29 /* IND_DONE (1<<2) */
962 beq 2f
963 b 3f
965 2: /* is it a source page? (r9) */
966 rlwinm. r7, r0, 0, 28, 28 /* IND_SOURCE (1<<3) */
967 beq 0b
969 rlwinm r9, r0, 0, 0, 19 /* clear kexec flags, page align */
971 li r7, PAGE_SIZE / 4
972 mtctr r7
973 subi r9, r9, 4
974 subi r8, r8, 4
975 9:
976 lwzu r0, 4(r9) /* do the copy */
977 xor r6, r6, r0
978 stwu r0, 4(r8)
979 dcbst 0, r8
980 sync
981 icbi 0, r8
982 bdnz 9b
984 addi r9, r9, 4
985 addi r8, r8, 4
986 b 0b
988 3:
990 /* To be certain of avoiding problems with self-modifying code
991 * execute a serializing instruction here.
992 */
993 isync
994 sync
996 mfspr r3, SPRN_PIR /* current core we are running on */
997 mr r4, r5 /* load physical address of chunk called */
999 /* jump to the entry point, usually the setup routine */
1000 mtlr r5
1001 blrl
1003 1: b 1b
1005 relocate_new_kernel_end:
1007 .globl relocate_new_kernel_size
1008 relocate_new_kernel_size:
1009 .long relocate_new_kernel_end - relocate_new_kernel
1010 #endif