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Linux v2.6.13-rc3
[pohmelfs.git] / arch / x86_64 / kernel / mpparse.c
blob9c5aa2a790c71f3abd26a92dd1b0021969104dd9
1 /*
2 * Intel Multiprocessor Specification 1.1 and 1.4
3 * compliant MP-table parsing routines.
4 *
5 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
6 * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 *
8 * Fixes
9 * Erich Boleyn : MP v1.4 and additional changes.
10 * Alan Cox : Added EBDA scanning
11 * Ingo Molnar : various cleanups and rewrites
12 * Maciej W. Rozycki: Bits for default MP configurations
13 * Paul Diefenbaugh: Added full ACPI support
14 */
15
16 #include <linux/mm.h>
17 #include <linux/irq.h>
18 #include <linux/init.h>
19 #include <linux/delay.h>
20 #include <linux/config.h>
21 #include <linux/bootmem.h>
22 #include <linux/smp_lock.h>
23 #include <linux/kernel_stat.h>
24 #include <linux/mc146818rtc.h>
25 #include <linux/acpi.h>
26 #include <linux/module.h>
27
28 #include <asm/smp.h>
29 #include <asm/mtrr.h>
30 #include <asm/mpspec.h>
31 #include <asm/pgalloc.h>
32 #include <asm/io_apic.h>
33 #include <asm/proto.h>
34 #include <asm/acpi.h>
35
36 /* Have we found an MP table */
37 int smp_found_config;
38 unsigned int __initdata maxcpus = NR_CPUS;
39
40 int acpi_found_madt;
41
42 /*
43 * Various Linux-internal data structures created from the
44 * MP-table.
45 */
46 int apic_version [MAX_APICS];
47 unsigned char mp_bus_id_to_type [MAX_MP_BUSSES] = { [0 ... MAX_MP_BUSSES-1] = -1 };
48 int mp_bus_id_to_pci_bus [MAX_MP_BUSSES] = { [0 ... MAX_MP_BUSSES-1] = -1 };
49 unsigned char pci_bus_to_node [256];
50 EXPORT_SYMBOL(pci_bus_to_node);
51
52 static int mp_current_pci_id = 0;
53 /* I/O APIC entries */
54 struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS];
55
56 /* # of MP IRQ source entries */
57 struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
58
59 /* MP IRQ source entries */
60 int mp_irq_entries;
61
62 int nr_ioapics;
63 int pic_mode;
64 unsigned long mp_lapic_addr = 0;
65
66
67
68 /* Processor that is doing the boot up */
69 unsigned int boot_cpu_id = -1U;
70 /* Internal processor count */
71 static unsigned int num_processors = 0;
72
73 /* Bitmask of physically existing CPUs */
74 physid_mask_t phys_cpu_present_map = PHYSID_MASK_NONE;
75
76 /* ACPI MADT entry parsing functions */
77 #ifdef CONFIG_ACPI_BOOT
78 extern struct acpi_boot_flags acpi_boot;
79 #ifdef CONFIG_X86_LOCAL_APIC
80 extern int acpi_parse_lapic (acpi_table_entry_header *header);
81 extern int acpi_parse_lapic_addr_ovr (acpi_table_entry_header *header);
82 extern int acpi_parse_lapic_nmi (acpi_table_entry_header *header);
83 #endif /*CONFIG_X86_LOCAL_APIC*/
84 #ifdef CONFIG_X86_IO_APIC
85 extern int acpi_parse_ioapic (acpi_table_entry_header *header);
86 #endif /*CONFIG_X86_IO_APIC*/
87 #endif /*CONFIG_ACPI_BOOT*/
88
89 u8 bios_cpu_apicid[NR_CPUS] = { [0 ... NR_CPUS-1] = BAD_APICID };
90
91
92 /*
93 * Intel MP BIOS table parsing routines:
94 */
95
96 /*
97 * Checksum an MP configuration block.
98 */
99
100 static int __init mpf_checksum(unsigned char *mp, int len)
101 {
102 int sum = 0;
103
104 while (len--)
105 sum += *mp++;
106
107 return sum & 0xFF;
108 }
109
110 static void __init MP_processor_info (struct mpc_config_processor *m)
111 {
112 int ver;
113 static int found_bsp=0;
114
115 if (!(m->mpc_cpuflag & CPU_ENABLED))
116 return;
117
118 printk(KERN_INFO "Processor #%d %d:%d APIC version %d\n",
119 m->mpc_apicid,
120 (m->mpc_cpufeature & CPU_FAMILY_MASK)>>8,
121 (m->mpc_cpufeature & CPU_MODEL_MASK)>>4,
122 m->mpc_apicver);
123
124 if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) {
125 Dprintk(" Bootup CPU\n");
126 boot_cpu_id = m->mpc_apicid;
127 }
128 if (num_processors >= NR_CPUS) {
129 printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached."
130 " Processor ignored.\n", NR_CPUS);
131 return;
132 }
133
134 num_processors++;
135
136 if (m->mpc_apicid > MAX_APICS) {
137 printk(KERN_ERR "Processor #%d INVALID. (Max ID: %d).\n",
138 m->mpc_apicid, MAX_APICS);
139 return;
140 }
141 ver = m->mpc_apicver;
142
143 physid_set(m->mpc_apicid, phys_cpu_present_map);
144 /*
145 * Validate version
146 */
147 if (ver == 0x0) {
148 printk(KERN_ERR "BIOS bug, APIC version is 0 for CPU#%d! fixing up to 0x10. (tell your hw vendor)\n", m->mpc_apicid);
149 ver = 0x10;
150 }
151 apic_version[m->mpc_apicid] = ver;
152 if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) {
153 /*
154 * bios_cpu_apicid is required to have processors listed
155 * in same order as logical cpu numbers. Hence the first
156 * entry is BSP, and so on.
157 */
158 bios_cpu_apicid[0] = m->mpc_apicid;
159 x86_cpu_to_apicid[0] = m->mpc_apicid;
160 found_bsp = 1;
161 } else {
162 bios_cpu_apicid[num_processors - found_bsp] = m->mpc_apicid;
163 x86_cpu_to_apicid[num_processors - found_bsp] = m->mpc_apicid;
164 }
165 }
166
167 static void __init MP_bus_info (struct mpc_config_bus *m)
168 {
169 char str[7];
170
171 memcpy(str, m->mpc_bustype, 6);
172 str[6] = 0;
173 Dprintk("Bus #%d is %s\n", m->mpc_busid, str);
174
175 if (strncmp(str, "ISA", 3) == 0) {
176 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_ISA;
177 } else if (strncmp(str, "EISA", 4) == 0) {
178 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_EISA;
179 } else if (strncmp(str, "PCI", 3) == 0) {
180 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_PCI;
181 mp_bus_id_to_pci_bus[m->mpc_busid] = mp_current_pci_id;
182 mp_current_pci_id++;
183 } else if (strncmp(str, "MCA", 3) == 0) {
184 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_MCA;
185 } else {
186 printk(KERN_ERR "Unknown bustype %s\n", str);
187 }
188 }
189
190 static void __init MP_ioapic_info (struct mpc_config_ioapic *m)
191 {
192 if (!(m->mpc_flags & MPC_APIC_USABLE))
193 return;
194
195 printk("I/O APIC #%d Version %d at 0x%X.\n",
196 m->mpc_apicid, m->mpc_apicver, m->mpc_apicaddr);
197 if (nr_ioapics >= MAX_IO_APICS) {
198 printk(KERN_ERR "Max # of I/O APICs (%d) exceeded (found %d).\n",
199 MAX_IO_APICS, nr_ioapics);
200 panic("Recompile kernel with bigger MAX_IO_APICS!.\n");
201 }
202 if (!m->mpc_apicaddr) {
203 printk(KERN_ERR "WARNING: bogus zero I/O APIC address"
204 " found in MP table, skipping!\n");
205 return;
206 }
207 mp_ioapics[nr_ioapics] = *m;
208 nr_ioapics++;
209 }
210
211 static void __init MP_intsrc_info (struct mpc_config_intsrc *m)
212 {
213 mp_irqs [mp_irq_entries] = *m;
214 Dprintk("Int: type %d, pol %d, trig %d, bus %d,"
215 " IRQ %02x, APIC ID %x, APIC INT %02x\n",
216 m->mpc_irqtype, m->mpc_irqflag & 3,
217 (m->mpc_irqflag >> 2) & 3, m->mpc_srcbus,
218 m->mpc_srcbusirq, m->mpc_dstapic, m->mpc_dstirq);
219 if (++mp_irq_entries == MAX_IRQ_SOURCES)
220 panic("Max # of irq sources exceeded!!\n");
221 }
222
223 static void __init MP_lintsrc_info (struct mpc_config_lintsrc *m)
224 {
225 Dprintk("Lint: type %d, pol %d, trig %d, bus %d,"
226 " IRQ %02x, APIC ID %x, APIC LINT %02x\n",
227 m->mpc_irqtype, m->mpc_irqflag & 3,
228 (m->mpc_irqflag >> 2) &3, m->mpc_srcbusid,
229 m->mpc_srcbusirq, m->mpc_destapic, m->mpc_destapiclint);
230 /*
231 * Well it seems all SMP boards in existence
232 * use ExtINT/LVT1 == LINT0 and
233 * NMI/LVT2 == LINT1 - the following check
234 * will show us if this assumptions is false.
235 * Until then we do not have to add baggage.
236 */
237 if ((m->mpc_irqtype == mp_ExtINT) &&
238 (m->mpc_destapiclint != 0))
239 BUG();
240 if ((m->mpc_irqtype == mp_NMI) &&
241 (m->mpc_destapiclint != 1))
242 BUG();
243 }
244
245 /*
246 * Read/parse the MPC
247 */
248
249 static int __init smp_read_mpc(struct mp_config_table *mpc)
250 {
251 char str[16];
252 int count=sizeof(*mpc);
253 unsigned char *mpt=((unsigned char *)mpc)+count;
254
255 if (memcmp(mpc->mpc_signature,MPC_SIGNATURE,4)) {
256 printk("SMP mptable: bad signature [%c%c%c%c]!\n",
257 mpc->mpc_signature[0],
258 mpc->mpc_signature[1],
259 mpc->mpc_signature[2],
260 mpc->mpc_signature[3]);
261 return 0;
262 }
263 if (mpf_checksum((unsigned char *)mpc,mpc->mpc_length)) {
264 printk("SMP mptable: checksum error!\n");
265 return 0;
266 }
267 if (mpc->mpc_spec!=0x01 && mpc->mpc_spec!=0x04) {
268 printk(KERN_ERR "SMP mptable: bad table version (%d)!!\n",
269 mpc->mpc_spec);
270 return 0;
271 }
272 if (!mpc->mpc_lapic) {
273 printk(KERN_ERR "SMP mptable: null local APIC address!\n");
274 return 0;
275 }
276 memcpy(str,mpc->mpc_oem,8);
277 str[8]=0;
278 printk(KERN_INFO "OEM ID: %s ",str);
279
280 memcpy(str,mpc->mpc_productid,12);
281 str[12]=0;
282 printk(KERN_INFO "Product ID: %s ",str);
283
284 printk(KERN_INFO "APIC at: 0x%X\n",mpc->mpc_lapic);
285
286 /* save the local APIC address, it might be non-default */
287 if (!acpi_lapic)
288 mp_lapic_addr = mpc->mpc_lapic;
289
290 /*
291 * Now process the configuration blocks.
292 */
293 while (count < mpc->mpc_length) {
294 switch(*mpt) {
295 case MP_PROCESSOR:
296 {
297 struct mpc_config_processor *m=
298 (struct mpc_config_processor *)mpt;
299 if (!acpi_lapic)
300 MP_processor_info(m);
301 mpt += sizeof(*m);
302 count += sizeof(*m);
303 break;
304 }
305 case MP_BUS:
306 {
307 struct mpc_config_bus *m=
308 (struct mpc_config_bus *)mpt;
309 MP_bus_info(m);
310 mpt += sizeof(*m);
311 count += sizeof(*m);
312 break;
313 }
314 case MP_IOAPIC:
315 {
316 struct mpc_config_ioapic *m=
317 (struct mpc_config_ioapic *)mpt;
318 MP_ioapic_info(m);
319 mpt+=sizeof(*m);
320 count+=sizeof(*m);
321 break;
322 }
323 case MP_INTSRC:
324 {
325 struct mpc_config_intsrc *m=
326 (struct mpc_config_intsrc *)mpt;
327
328 MP_intsrc_info(m);
329 mpt+=sizeof(*m);
330 count+=sizeof(*m);
331 break;
332 }
333 case MP_LINTSRC:
334 {
335 struct mpc_config_lintsrc *m=
336 (struct mpc_config_lintsrc *)mpt;
337 MP_lintsrc_info(m);
338 mpt+=sizeof(*m);
339 count+=sizeof(*m);
340 break;
341 }
342 }
343 }
344 clustered_apic_check();
345 if (!num_processors)
346 printk(KERN_ERR "SMP mptable: no processors registered!\n");
347 return num_processors;
348 }
349
350 static int __init ELCR_trigger(unsigned int irq)
351 {
352 unsigned int port;
353
354 port = 0x4d0 + (irq >> 3);
355 return (inb(port) >> (irq & 7)) & 1;
356 }
357
358 static void __init construct_default_ioirq_mptable(int mpc_default_type)
359 {
360 struct mpc_config_intsrc intsrc;
361 int i;
362 int ELCR_fallback = 0;
363
364 intsrc.mpc_type = MP_INTSRC;
365 intsrc.mpc_irqflag = 0; /* conforming */
366 intsrc.mpc_srcbus = 0;
367 intsrc.mpc_dstapic = mp_ioapics[0].mpc_apicid;
368
369 intsrc.mpc_irqtype = mp_INT;
370
371 /*
372 * If true, we have an ISA/PCI system with no IRQ entries
373 * in the MP table. To prevent the PCI interrupts from being set up
374 * incorrectly, we try to use the ELCR. The sanity check to see if
375 * there is good ELCR data is very simple - IRQ0, 1, 2 and 13 can
376 * never be level sensitive, so we simply see if the ELCR agrees.
377 * If it does, we assume it's valid.
378 */
379 if (mpc_default_type == 5) {
380 printk(KERN_INFO "ISA/PCI bus type with no IRQ information... falling back to ELCR\n");
381
382 if (ELCR_trigger(0) || ELCR_trigger(1) || ELCR_trigger(2) || ELCR_trigger(13))
383 printk(KERN_ERR "ELCR contains invalid data... not using ELCR\n");
384 else {
385 printk(KERN_INFO "Using ELCR to identify PCI interrupts\n");
386 ELCR_fallback = 1;
387 }
388 }
389
390 for (i = 0; i < 16; i++) {
391 switch (mpc_default_type) {
392 case 2:
393 if (i == 0 || i == 13)
394 continue; /* IRQ0 & IRQ13 not connected */
395 /* fall through */
396 default:
397 if (i == 2)
398 continue; /* IRQ2 is never connected */
399 }
400
401 if (ELCR_fallback) {
402 /*
403 * If the ELCR indicates a level-sensitive interrupt, we
404 * copy that information over to the MP table in the
405 * irqflag field (level sensitive, active high polarity).
406 */
407 if (ELCR_trigger(i))
408 intsrc.mpc_irqflag = 13;
409 else
410 intsrc.mpc_irqflag = 0;
411 }
412
413 intsrc.mpc_srcbusirq = i;
414 intsrc.mpc_dstirq = i ? i : 2; /* IRQ0 to INTIN2 */
415 MP_intsrc_info(&intsrc);
416 }
417
418 intsrc.mpc_irqtype = mp_ExtINT;
419 intsrc.mpc_srcbusirq = 0;
420 intsrc.mpc_dstirq = 0; /* 8259A to INTIN0 */
421 MP_intsrc_info(&intsrc);
422 }
423
424 static inline void __init construct_default_ISA_mptable(int mpc_default_type)
425 {
426 struct mpc_config_processor processor;
427 struct mpc_config_bus bus;
428 struct mpc_config_ioapic ioapic;
429 struct mpc_config_lintsrc lintsrc;
430 int linttypes[2] = { mp_ExtINT, mp_NMI };
431 int i;
432
433 /*
434 * local APIC has default address
435 */
436 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
437
438 /*
439 * 2 CPUs, numbered 0 & 1.
440 */
441 processor.mpc_type = MP_PROCESSOR;
442 /* Either an integrated APIC or a discrete 82489DX. */
443 processor.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
444 processor.mpc_cpuflag = CPU_ENABLED;
445 processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) |
446 (boot_cpu_data.x86_model << 4) |
447 boot_cpu_data.x86_mask;
448 processor.mpc_featureflag = boot_cpu_data.x86_capability[0];
449 processor.mpc_reserved[0] = 0;
450 processor.mpc_reserved[1] = 0;
451 for (i = 0; i < 2; i++) {
452 processor.mpc_apicid = i;
453 MP_processor_info(&processor);
454 }
455
456 bus.mpc_type = MP_BUS;
457 bus.mpc_busid = 0;
458 switch (mpc_default_type) {
459 default:
460 printk(KERN_ERR "???\nUnknown standard configuration %d\n",
461 mpc_default_type);
462 /* fall through */
463 case 1:
464 case 5:
465 memcpy(bus.mpc_bustype, "ISA ", 6);
466 break;
467 case 2:
468 case 6:
469 case 3:
470 memcpy(bus.mpc_bustype, "EISA ", 6);
471 break;
472 case 4:
473 case 7:
474 memcpy(bus.mpc_bustype, "MCA ", 6);
475 }
476 MP_bus_info(&bus);
477 if (mpc_default_type > 4) {
478 bus.mpc_busid = 1;
479 memcpy(bus.mpc_bustype, "PCI ", 6);
480 MP_bus_info(&bus);
481 }
482
483 ioapic.mpc_type = MP_IOAPIC;
484 ioapic.mpc_apicid = 2;
485 ioapic.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
486 ioapic.mpc_flags = MPC_APIC_USABLE;
487 ioapic.mpc_apicaddr = 0xFEC00000;
488 MP_ioapic_info(&ioapic);
489
490 /*
491 * We set up most of the low 16 IO-APIC pins according to MPS rules.
492 */
493 construct_default_ioirq_mptable(mpc_default_type);
494
495 lintsrc.mpc_type = MP_LINTSRC;
496 lintsrc.mpc_irqflag = 0; /* conforming */
497 lintsrc.mpc_srcbusid = 0;
498 lintsrc.mpc_srcbusirq = 0;
499 lintsrc.mpc_destapic = MP_APIC_ALL;
500 for (i = 0; i < 2; i++) {
501 lintsrc.mpc_irqtype = linttypes[i];
502 lintsrc.mpc_destapiclint = i;
503 MP_lintsrc_info(&lintsrc);
504 }
505 }
506
507 static struct intel_mp_floating *mpf_found;
508
509 /*
510 * Scan the memory blocks for an SMP configuration block.
511 */
512 void __init get_smp_config (void)
513 {
514 struct intel_mp_floating *mpf = mpf_found;
515
516 /*
517 * ACPI may be used to obtain the entire SMP configuration or just to
518 * enumerate/configure processors (CONFIG_ACPI_BOOT). Note that
519 * ACPI supports both logical (e.g. Hyper-Threading) and physical
520 * processors, where MPS only supports physical.
521 */
522 if (acpi_lapic && acpi_ioapic) {
523 printk(KERN_INFO "Using ACPI (MADT) for SMP configuration information\n");
524 return;
525 }
526 else if (acpi_lapic)
527 printk(KERN_INFO "Using ACPI for processor (LAPIC) configuration information\n");
528
529 printk("Intel MultiProcessor Specification v1.%d\n", mpf->mpf_specification);
530 if (mpf->mpf_feature2 & (1<<7)) {
531 printk(KERN_INFO " IMCR and PIC compatibility mode.\n");
532 pic_mode = 1;
533 } else {
534 printk(KERN_INFO " Virtual Wire compatibility mode.\n");
535 pic_mode = 0;
536 }
537
538 /*
539 * Now see if we need to read further.
540 */
541 if (mpf->mpf_feature1 != 0) {
542
543 printk(KERN_INFO "Default MP configuration #%d\n", mpf->mpf_feature1);
544 construct_default_ISA_mptable(mpf->mpf_feature1);
545
546 } else if (mpf->mpf_physptr) {
547
548 /*
549 * Read the physical hardware table. Anything here will
550 * override the defaults.
551 */
552 if (!smp_read_mpc((void *)(unsigned long)mpf->mpf_physptr)) {
553 smp_found_config = 0;
554 printk(KERN_ERR "BIOS bug, MP table errors detected!...\n");
555 printk(KERN_ERR "... disabling SMP support. (tell your hw vendor)\n");
556 return;
557 }
558 /*
559 * If there are no explicit MP IRQ entries, then we are
560 * broken. We set up most of the low 16 IO-APIC pins to
561 * ISA defaults and hope it will work.
562 */
563 if (!mp_irq_entries) {
564 struct mpc_config_bus bus;
565
566 printk(KERN_ERR "BIOS bug, no explicit IRQ entries, using default mptable. (tell your hw vendor)\n");
567
568 bus.mpc_type = MP_BUS;
569 bus.mpc_busid = 0;
570 memcpy(bus.mpc_bustype, "ISA ", 6);
571 MP_bus_info(&bus);
572
573 construct_default_ioirq_mptable(0);
574 }
575
576 } else
577 BUG();
578
579 printk(KERN_INFO "Processors: %d\n", num_processors);
580 /*
581 * Only use the first configuration found.
582 */
583 }
584
585 static int __init smp_scan_config (unsigned long base, unsigned long length)
586 {
587 extern void __bad_mpf_size(void);
588 unsigned int *bp = phys_to_virt(base);
589 struct intel_mp_floating *mpf;
590
591 Dprintk("Scan SMP from %p for %ld bytes.\n", bp,length);
592 if (sizeof(*mpf) != 16)
593 __bad_mpf_size();
594
595 while (length > 0) {
596 mpf = (struct intel_mp_floating *)bp;
597 if ((*bp == SMP_MAGIC_IDENT) &&
598 (mpf->mpf_length == 1) &&
599 !mpf_checksum((unsigned char *)bp, 16) &&
600 ((mpf->mpf_specification == 1)
601 || (mpf->mpf_specification == 4)) ) {
602
603 smp_found_config = 1;
604 reserve_bootmem_generic(virt_to_phys(mpf), PAGE_SIZE);
605 if (mpf->mpf_physptr)
606 reserve_bootmem_generic(mpf->mpf_physptr, PAGE_SIZE);
607 mpf_found = mpf;
608 return 1;
609 }
610 bp += 4;
611 length -= 16;
612 }
613 return 0;
614 }
615
616 void __init find_intel_smp (void)
617 {
618 unsigned int address;
619
620 /*
621 * FIXME: Linux assumes you have 640K of base ram..
622 * this continues the error...
623 *
624 * 1) Scan the bottom 1K for a signature
625 * 2) Scan the top 1K of base RAM
626 * 3) Scan the 64K of bios
627 */
628 if (smp_scan_config(0x0,0x400) ||
629 smp_scan_config(639*0x400,0x400) ||
630 smp_scan_config(0xF0000,0x10000))
631 return;
632 /*
633 * If it is an SMP machine we should know now, unless the
634 * configuration is in an EISA/MCA bus machine with an
635 * extended bios data area.
636 *
637 * there is a real-mode segmented pointer pointing to the
638 * 4K EBDA area at 0x40E, calculate and scan it here.
639 *
640 * NOTE! There are Linux loaders that will corrupt the EBDA
641 * area, and as such this kind of SMP config may be less
642 * trustworthy, simply because the SMP table may have been
643 * stomped on during early boot. These loaders are buggy and
644 * should be fixed.
645 */
646
647 address = *(unsigned short *)phys_to_virt(0x40E);
648 address <<= 4;
649 if (smp_scan_config(address, 0x1000))
650 return;
651
652 /* If we have come this far, we did not find an MP table */
653 printk(KERN_INFO "No mptable found.\n");
654 }
655
656 /*
657 * - Intel MP Configuration Table
658 */
659 void __init find_smp_config (void)
660 {
661 #ifdef CONFIG_X86_LOCAL_APIC
662 find_intel_smp();
663 #endif
664 }
665
666
667 /* --------------------------------------------------------------------------
668 ACPI-based MP Configuration
669 -------------------------------------------------------------------------- */
670
671 #ifdef CONFIG_ACPI_BOOT
672
673 void __init mp_register_lapic_address (
674 u64 address)
675 {
676 mp_lapic_addr = (unsigned long) address;
677
678 set_fixmap_nocache(FIX_APIC_BASE, mp_lapic_addr);
679
680 if (boot_cpu_id == -1U)
681 boot_cpu_id = GET_APIC_ID(apic_read(APIC_ID));
682
683 Dprintk("Boot CPU = %d\n", boot_cpu_physical_apicid);
684 }
685
686
687 void __init mp_register_lapic (
688 u8 id,
689 u8 enabled)
690 {
691 struct mpc_config_processor processor;
692 int boot_cpu = 0;
693
694 if (id >= MAX_APICS) {
695 printk(KERN_WARNING "Processor #%d invalid (max %d)\n",
696 id, MAX_APICS);
697 return;
698 }
699
700 if (id == boot_cpu_physical_apicid)
701 boot_cpu = 1;
702
703 processor.mpc_type = MP_PROCESSOR;
704 processor.mpc_apicid = id;
705 processor.mpc_apicver = 0x10; /* TBD: lapic version */
706 processor.mpc_cpuflag = (enabled ? CPU_ENABLED : 0);
707 processor.mpc_cpuflag |= (boot_cpu ? CPU_BOOTPROCESSOR : 0);
708 processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) |
709 (boot_cpu_data.x86_model << 4) | boot_cpu_data.x86_mask;
710 processor.mpc_featureflag = boot_cpu_data.x86_capability[0];
711 processor.mpc_reserved[0] = 0;
712 processor.mpc_reserved[1] = 0;
713
714 MP_processor_info(&processor);
715 }
716
717 #ifdef CONFIG_X86_IO_APIC
718
719 #define MP_ISA_BUS 0
720 #define MP_MAX_IOAPIC_PIN 127
721
722 static struct mp_ioapic_routing {
723 int apic_id;
724 int gsi_start;
725 int gsi_end;
726 u32 pin_programmed[4];
727 } mp_ioapic_routing[MAX_IO_APICS];
728
729
730 static int mp_find_ioapic (
731 int gsi)
732 {
733 int i = 0;
734
735 /* Find the IOAPIC that manages this GSI. */
736 for (i = 0; i < nr_ioapics; i++) {
737 if ((gsi >= mp_ioapic_routing[i].gsi_start)
738 && (gsi <= mp_ioapic_routing[i].gsi_end))
739 return i;
740 }
741
742 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
743
744 return -1;
745 }
746
747
748 void __init mp_register_ioapic (
749 u8 id,
750 u32 address,
751 u32 gsi_base)
752 {
753 int idx = 0;
754
755 if (nr_ioapics >= MAX_IO_APICS) {
756 printk(KERN_ERR "ERROR: Max # of I/O APICs (%d) exceeded "
757 "(found %d)\n", MAX_IO_APICS, nr_ioapics);
758 panic("Recompile kernel with bigger MAX_IO_APICS!\n");
759 }
760 if (!address) {
761 printk(KERN_ERR "WARNING: Bogus (zero) I/O APIC address"
762 " found in MADT table, skipping!\n");
763 return;
764 }
765
766 idx = nr_ioapics++;
767
768 mp_ioapics[idx].mpc_type = MP_IOAPIC;
769 mp_ioapics[idx].mpc_flags = MPC_APIC_USABLE;
770 mp_ioapics[idx].mpc_apicaddr = address;
771
772 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
773 mp_ioapics[idx].mpc_apicid = id;
774 mp_ioapics[idx].mpc_apicver = io_apic_get_version(idx);
775
776 /*
777 * Build basic IRQ lookup table to facilitate gsi->io_apic lookups
778 * and to prevent reprogramming of IOAPIC pins (PCI IRQs).
779 */
780 mp_ioapic_routing[idx].apic_id = mp_ioapics[idx].mpc_apicid;
781 mp_ioapic_routing[idx].gsi_start = gsi_base;
782 mp_ioapic_routing[idx].gsi_end = gsi_base +
783 io_apic_get_redir_entries(idx);
784
785 printk(KERN_INFO "IOAPIC[%d]: apic_id %d, version %d, address 0x%x, "
786 "GSI %d-%d\n", idx, mp_ioapics[idx].mpc_apicid,
787 mp_ioapics[idx].mpc_apicver, mp_ioapics[idx].mpc_apicaddr,
788 mp_ioapic_routing[idx].gsi_start,
789 mp_ioapic_routing[idx].gsi_end);
790
791 return;
792 }
793
794
795 void __init mp_override_legacy_irq (
796 u8 bus_irq,
797 u8 polarity,
798 u8 trigger,
799 u32 gsi)
800 {
801 struct mpc_config_intsrc intsrc;
802 int ioapic = -1;
803 int pin = -1;
804
805 /*
806 * Convert 'gsi' to 'ioapic.pin'.
807 */
808 ioapic = mp_find_ioapic(gsi);
809 if (ioapic < 0)
810 return;
811 pin = gsi - mp_ioapic_routing[ioapic].gsi_start;
812
813 /*
814 * TBD: This check is for faulty timer entries, where the override
815 * erroneously sets the trigger to level, resulting in a HUGE
816 * increase of timer interrupts!
817 */
818 if ((bus_irq == 0) && (trigger == 3))
819 trigger = 1;
820
821 intsrc.mpc_type = MP_INTSRC;
822 intsrc.mpc_irqtype = mp_INT;
823 intsrc.mpc_irqflag = (trigger << 2) | polarity;
824 intsrc.mpc_srcbus = MP_ISA_BUS;
825 intsrc.mpc_srcbusirq = bus_irq; /* IRQ */
826 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid; /* APIC ID */
827 intsrc.mpc_dstirq = pin; /* INTIN# */
828
829 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, %d-%d\n",
830 intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
831 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
832 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic, intsrc.mpc_dstirq);
833
834 mp_irqs[mp_irq_entries] = intsrc;
835 if (++mp_irq_entries == MAX_IRQ_SOURCES)
836 panic("Max # of irq sources exceeded!\n");
837
838 return;
839 }
840
841
842 void __init mp_config_acpi_legacy_irqs (void)
843 {
844 struct mpc_config_intsrc intsrc;
845 int i = 0;
846 int ioapic = -1;
847
848 /*
849 * Fabricate the legacy ISA bus (bus #31).
850 */
851 mp_bus_id_to_type[MP_ISA_BUS] = MP_BUS_ISA;
852 Dprintk("Bus #%d is ISA\n", MP_ISA_BUS);
853
854 /*
855 * Locate the IOAPIC that manages the ISA IRQs (0-15).
856 */
857 ioapic = mp_find_ioapic(0);
858 if (ioapic < 0)
859 return;
860
861 intsrc.mpc_type = MP_INTSRC;
862 intsrc.mpc_irqflag = 0; /* Conforming */
863 intsrc.mpc_srcbus = MP_ISA_BUS;
864 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid;
865
866 /*
867 * Use the default configuration for the IRQs 0-15. Unless
868 * overridden by (MADT) interrupt source override entries.
869 */
870 for (i = 0; i < 16; i++) {
871 int idx;
872
873 for (idx = 0; idx < mp_irq_entries; idx++) {
874 struct mpc_config_intsrc *irq = mp_irqs + idx;
875
876 /* Do we already have a mapping for this ISA IRQ? */
877 if (irq->mpc_srcbus == MP_ISA_BUS && irq->mpc_srcbusirq == i)
878 break;
879
880 /* Do we already have a mapping for this IOAPIC pin */
881 if ((irq->mpc_dstapic == intsrc.mpc_dstapic) &&
882 (irq->mpc_dstirq == i))
883 break;
884 }
885
886 if (idx != mp_irq_entries) {
887 printk(KERN_DEBUG "ACPI: IRQ%d used by override.\n", i);
888 continue; /* IRQ already used */
889 }
890
891 intsrc.mpc_irqtype = mp_INT;
892 intsrc.mpc_srcbusirq = i; /* Identity mapped */
893 intsrc.mpc_dstirq = i;
894
895 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, "
896 "%d-%d\n", intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
897 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
898 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic,
899 intsrc.mpc_dstirq);
900
901 mp_irqs[mp_irq_entries] = intsrc;
902 if (++mp_irq_entries == MAX_IRQ_SOURCES)
903 panic("Max # of irq sources exceeded!\n");
904 }
905
906 return;
907 }
908
909 #define MAX_GSI_NUM 4096
910
911 int mp_register_gsi(u32 gsi, int edge_level, int active_high_low)
912 {
913 int ioapic = -1;
914 int ioapic_pin = 0;
915 int idx, bit = 0;
916 static int pci_irq = 16;
917 /*
918 * Mapping between Global System Interrupts, which
919 * represent all possible interrupts, to the IRQs
920 * assigned to actual devices.
921 */
922 static int gsi_to_irq[MAX_GSI_NUM];
923
924 if (acpi_irq_model != ACPI_IRQ_MODEL_IOAPIC)
925 return gsi;
926
927 #ifdef CONFIG_ACPI_BUS
928 /* Don't set up the ACPI SCI because it's already set up */
929 if (acpi_fadt.sci_int == gsi)
930 return gsi;
931 #endif
932
933 ioapic = mp_find_ioapic(gsi);
934 if (ioapic < 0) {
935 printk(KERN_WARNING "No IOAPIC for GSI %u\n", gsi);
936 return gsi;
937 }
938
939 ioapic_pin = gsi - mp_ioapic_routing[ioapic].gsi_start;
940
941 /*
942 * Avoid pin reprogramming. PRTs typically include entries
943 * with redundant pin->gsi mappings (but unique PCI devices);
944 * we only program the IOAPIC on the first.
945 */
946 bit = ioapic_pin % 32;
947 idx = (ioapic_pin < 32) ? 0 : (ioapic_pin / 32);
948 if (idx > 3) {
949 printk(KERN_ERR "Invalid reference to IOAPIC pin "
950 "%d-%d\n", mp_ioapic_routing[ioapic].apic_id,
951 ioapic_pin);
952 return gsi;
953 }
954 if ((1<<bit) & mp_ioapic_routing[ioapic].pin_programmed[idx]) {
955 Dprintk(KERN_DEBUG "Pin %d-%d already programmed\n",
956 mp_ioapic_routing[ioapic].apic_id, ioapic_pin);
957 return gsi_to_irq[gsi];
958 }
959
960 mp_ioapic_routing[ioapic].pin_programmed[idx] |= (1<<bit);
961
962 if (edge_level) {
963 /*
964 * For PCI devices assign IRQs in order, avoiding gaps
965 * due to unused I/O APIC pins.
966 */
967 int irq = gsi;
968 gsi = pci_irq++;
969 gsi_to_irq[irq] = gsi;
970 }
971
972 io_apic_set_pci_routing(ioapic, ioapic_pin, gsi,
973 edge_level == ACPI_EDGE_SENSITIVE ? 0 : 1,
974 active_high_low == ACPI_ACTIVE_HIGH ? 0 : 1);
975 return gsi;
976 }
977
978 #endif /*CONFIG_X86_IO_APIC*/
979 #endif /*CONFIG_ACPI_BOOT*/