include/asm-arm/arch-s3c2410/regs-serial.h

   1 /* linux/include/asm-arm/arch-s3c2410/regs-serial.h
   2  *
   3  *  From linux/include/asm-arm/hardware/serial_s3c2410.h
   4  *
   5  *  Internal header file for Samsung S3C2410 serial ports (UART0-2)
   6  *
   7  *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
   8  *
   9  *  Additional defines, (c) 2003 Simtec Electronics (linux@simtec.co.uk)
  10  *
  11  *  Adapted from:
  12  *
  13  *  Internal header file for MX1ADS serial ports (UART1 & 2)
  14  *
  15  *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
  16  *
  17  * This program is free software; you can redistribute it and/or modify
  18  * it under the terms of the GNU General Public License as published by
  19  * the Free Software Foundation; either version 2 of the License, or
  20  * (at your option) any later version.
  21  *
  22  * This program is distributed in the hope that it will be useful,
  23  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  24  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  25  * GNU General Public License for more details.
  26  *
  27  * You should have received a copy of the GNU General Public License
  28  * along with this program; if not, write to the Free Software
  29  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  30  *
  31  * Modifications:
  32  *     10-Mar-2005 LCVR  Changed S3C2410_VA to S3C24XX_VA (s3c2400 support)
  33  */
  34
  35 #ifndef __ASM_ARM_REGS_SERIAL_H
  36 #define __ASM_ARM_REGS_SERIAL_H
  37
  38 #define S3C24XX_VA_UART0      (S3C24XX_VA_UART)
  39 #define S3C24XX_VA_UART1      (S3C24XX_VA_UART + 0x4000 )
  40 #define S3C24XX_VA_UART2      (S3C24XX_VA_UART + 0x8000 )
  41
  42 #define S3C2410_PA_UART0      (S3C2410_PA_UART)
  43 #define S3C2410_PA_UART1      (S3C2410_PA_UART + 0x4000 )
  44 #define S3C2410_PA_UART2      (S3C2410_PA_UART + 0x8000 )
  45
  46 #define S3C2410_URXH      (0x24)
  47 #define S3C2410_UTXH      (0x20)
  48 #define S3C2410_ULCON     (0x00)
  49 #define S3C2410_UCON      (0x04)
  50 #define S3C2410_UFCON     (0x08)
  51 #define S3C2410_UMCON     (0x0C)
  52 #define S3C2410_UBRDIV    (0x28)
  53 #define S3C2410_UTRSTAT   (0x10)
  54 #define S3C2410_UERSTAT   (0x14)
  55 #define S3C2410_UFSTAT    (0x18)
  56 #define S3C2410_UMSTAT    (0x1C)
  57
  58 #define S3C2410_LCON_CFGMASK      ((0xF<<3)|(0x3))
  59
  60 #define S3C2410_LCON_CS5          (0x0)
  61 #define S3C2410_LCON_CS6          (0x1)
  62 #define S3C2410_LCON_CS7          (0x2)
  63 #define S3C2410_LCON_CS8          (0x3)
  64 #define S3C2410_LCON_CSMASK       (0x3)
  65
  66 #define S3C2410_LCON_PNONE        (0x0)
  67 #define S3C2410_LCON_PEVEN        (0x5 << 3)
  68 #define S3C2410_LCON_PODD         (0x4 << 3)
  69 #define S3C2410_LCON_PMASK        (0x7 << 3)
  70
  71 #define S3C2410_LCON_STOPB        (1<<2)
  72 #define S3C2410_LCON_IRM          (1<<6)
  73
  74 #define S3C2440_UCON_CLKMASK      (3<<10)
  75 #define S3C2440_UCON_PCLK         (0<<10)
  76 #define S3C2440_UCON_UCLK         (1<<10)
  77 #define S3C2440_UCON_PCLK2        (2<<10)
  78 #define S3C2440_UCON_FCLK         (3<<10)
  79 #define S3C2440_UCON2_FCLK_EN     (1<<15)
  80 #define S3C2440_UCON0_DIVMASK     (15 << 12)
  81 #define S3C2440_UCON1_DIVMASK     (15 << 12)
  82 #define S3C2440_UCON2_DIVMASK     (7 << 12)
  83 #define S3C2440_UCON_DIVSHIFT     (12)
  84
  85 #define S3C2410_UCON_UCLK         (1<<10)
  86 #define S3C2410_UCON_SBREAK       (1<<4)
  87
  88 #define S3C2410_UCON_TXILEVEL     (1<<9)
  89 #define S3C2410_UCON_RXILEVEL     (1<<8)
  90 #define S3C2410_UCON_TXIRQMODE    (1<<2)
  91 #define S3C2410_UCON_RXIRQMODE    (1<<0)
  92 #define S3C2410_UCON_RXFIFO_TOI   (1<<7)
  93
  94 #define S3C2410_UCON_DEFAULT      (S3C2410_UCON_TXILEVEL  | \
  95                                    S3C2410_UCON_RXILEVEL  | \
  96                                    S3C2410_UCON_TXIRQMODE | \
  97                                    S3C2410_UCON_RXIRQMODE | \
  98                                    S3C2410_UCON_RXFIFO_TOI)
  99
 100 #define S3C2410_UFCON_FIFOMODE    (1<<0)
 101 #define S3C2410_UFCON_TXTRIG0     (0<<6)
 102 #define S3C2410_UFCON_RXTRIG8     (1<<4)
 103 #define S3C2410_UFCON_RXTRIG12    (2<<4)
 104
 105 /* S3C2440 FIFO trigger levels */
 106 #define S3C2440_UFCON_RXTRIG1     (0<<4)
 107 #define S3C2440_UFCON_RXTRIG8     (1<<4)
 108 #define S3C2440_UFCON_RXTRIG16    (2<<4)
 109 #define S3C2440_UFCON_RXTRIG32    (3<<4)
 110
 111 #define S3C2440_UFCON_TXTRIG0     (0<<6)
 112 #define S3C2440_UFCON_TXTRIG16    (1<<6)
 113 #define S3C2440_UFCON_TXTRIG32    (2<<6)
 114 #define S3C2440_UFCON_TXTRIG48    (3<<6)
 115
 116 #define S3C2410_UFCON_RESETBOTH   (3<<1)
 117 #define S3C2410_UFCON_RESETTX     (1<<2)
 118 #define S3C2410_UFCON_RESETRX     (1<<1)
 119
 120 #define S3C2410_UFCON_DEFAULT     (S3C2410_UFCON_FIFOMODE | \
 121                                    S3C2410_UFCON_TXTRIG0  | \
 122                                    S3C2410_UFCON_RXTRIG8 )
 123
 124 #define S3C2410_UMCOM_AFC         (1<<4)
 125 #define S3C2410_UMCOM_RTS_LOW     (1<<0)
 126
 127 #define S3C2410_UFSTAT_TXFULL     (1<<9)
 128 #define S3C2410_UFSTAT_RXFULL     (1<<8)
 129 #define S3C2410_UFSTAT_TXMASK     (15<<4)
 130 #define S3C2410_UFSTAT_TXSHIFT    (4)
 131 #define S3C2410_UFSTAT_RXMASK     (15<<0)
 132 #define S3C2410_UFSTAT_RXSHIFT    (0)
 133
 134 #define S3C2440_UFSTAT_TXFULL     (1<<14)
 135 #define S3C2440_UFSTAT_RXFULL     (1<<6)
 136 #define S3C2440_UFSTAT_TXSHIFT    (8)
 137 #define S3C2440_UFSTAT_RXSHIFT    (0)
 138 #define S3C2440_UFSTAT_TXMASK     (63<<8)
 139 #define S3C2440_UFSTAT_RXMASK     (63)
 140
 141 #define S3C2410_UTRSTAT_TXE       (1<<2)
 142 #define S3C2410_UTRSTAT_TXFE      (1<<1)
 143 #define S3C2410_UTRSTAT_RXDR      (1<<0)
 144
 145 #define S3C2410_UERSTAT_OVERRUN   (1<<0)
 146 #define S3C2410_UERSTAT_FRAME     (1<<2)
 147 #define S3C2410_UERSTAT_BREAK     (1<<3)
 148 #define S3C2410_UERSTAT_ANY       (S3C2410_UERSTAT_OVERRUN | \
 149                                    S3C2410_UERSTAT_FRAME | \
 150                                    S3C2410_UERSTAT_BREAK)
 151
 152 #define S3C2410_UMSTAT_CTS        (1<<0)
 153 #define S3C2410_UMSTAT_DeltaCTS   (1<<2)
 154
 155 #ifndef __ASSEMBLY__
 156
 157 /* struct s3c24xx_uart_clksrc
 158  *
 159  * this structure defines a named clock source that can be used for the
 160  * uart, so that the best clock can be selected for the requested baud
 161  * rate.
 162  *
 163  * min_baud and max_baud define the range of baud-rates this clock is
 164  * acceptable for, if they are both zero, it is assumed any baud rate that
 165  * can be generated from this clock will be used.
 166  *
 167  * divisor gives the divisor from the clock to the one seen by the uart
 168 */
 169
 170 struct s3c24xx_uart_clksrc {
 171         const char      *name;
 172         unsigned int     divisor;
 173         unsigned int     min_baud;
 174         unsigned int     max_baud;
 175 };
 176
 177 /* configuration structure for per-machine configurations for the
 178  * serial port
 179  *
 180  * the pointer is setup by the machine specific initialisation from the
 181  * arch/arm/mach-s3c2410/ directory.
 182 */
 183
 184 struct s3c2410_uartcfg {
 185         unsigned char      hwport;       /* hardware port number */
 186         unsigned char      unused;
 187         unsigned short     flags;
 188         unsigned long      uart_flags;   /* default uart flags */
 189
 190         unsigned long      ucon;         /* value of ucon for port */
 191         unsigned long      ulcon;        /* value of ulcon for port */
 192         unsigned long      ufcon;        /* value of ufcon for port */
 193
 194         struct s3c24xx_uart_clksrc *clocks;
 195         unsigned int                clocks_size;
 196 };
 197
 198 /* s3c24xx_uart_devs
 199  *
 200  * this is exported from the core as we cannot use driver_register(),
 201  * or platform_add_device() before the console_initcall()
 202 */
 203
 204 extern struct platform_device *s3c24xx_uart_devs[3];
 205
 206 #endif /* __ASSEMBLY__ */
 207
 208 #endif /* __ASM_ARM_REGS_SERIAL_H */
 209