include/asm-mips/mach-db1x00/db1x00.h

   1 /*
   2  * AMD Alchemy DB1x00 Reference Boards
   3  *
   4  * Copyright 2001 MontaVista Software Inc.
   5  * Author: MontaVista Software, Inc.
   6  *              ppopov@mvista.com or source@mvista.com
   7  * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
   8  *
   9  * ########################################################################
  10  *
  11  *  This program is free software; you can distribute it and/or modify it
  12  *  under the terms of the GNU General Public License (Version 2) as
  13  *  published by the Free Software Foundation.
  14  *
  15  *  This program is distributed in the hope it will be useful, but WITHOUT
  16  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  17  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  18  *  for more details.
  19  *
  20  *  You should have received a copy of the GNU General Public License along
  21  *  with this program; if not, write to the Free Software Foundation, Inc.,
  22  *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  23  *
  24  * ########################################################################
  25  *
  26  *
  27  */
  28 #ifndef __ASM_DB1X00_H
  29 #define __ASM_DB1X00_H
  30
  31 #include <linux/config.h>
  32
  33 #ifdef CONFIG_MIPS_DB1550
  34 #define BCSR_KSEG1_ADDR 0xAF000000
  35 #define NAND_PHYS_ADDR  0x20000000
  36 #else
  37 #define BCSR_KSEG1_ADDR 0xAE000000
  38 #endif
  39
  40 /*
  41  * Overlay data structure of the Db1x00 board registers.
  42  * Registers located at physical 0E0000xx, KSEG1 0xAE0000xx
  43  */
  44 typedef volatile struct
  45 {
  46         /*00*/  unsigned short whoami;
  47         unsigned short reserved0;
  48         /*04*/  unsigned short status;
  49         unsigned short reserved1;
  50         /*08*/  unsigned short switches;
  51         unsigned short reserved2;
  52         /*0C*/  unsigned short resets;
  53         unsigned short reserved3;
  54         /*10*/  unsigned short pcmcia;
  55         unsigned short reserved4;
  56         /*14*/  unsigned short specific;
  57         unsigned short reserved5;
  58         /*18*/  unsigned short leds;
  59         unsigned short reserved6;
  60         /*1C*/  unsigned short swreset;
  61         unsigned short reserved7;
  62
  63 } BCSR;
  64
  65
  66 /*
  67  * Register/mask bit definitions for the BCSRs
  68  */
  69 #define BCSR_WHOAMI_DCID                0x000F
  70 #define BCSR_WHOAMI_CPLD                0x00F0
  71 #define BCSR_WHOAMI_BOARD               0x0F00
  72
  73 #define BCSR_STATUS_PC0VS               0x0003
  74 #define BCSR_STATUS_PC1VS               0x000C
  75 #define BCSR_STATUS_PC0FI               0x0010
  76 #define BCSR_STATUS_PC1FI               0x0020
  77 #define BCSR_STATUS_FLASHBUSY           0x0100
  78 #define BCSR_STATUS_ROMBUSY             0x0400
  79 #define BCSR_STATUS_SWAPBOOT            0x2000
  80 #define BCSR_STATUS_FLASHDEN            0xC000
  81
  82 #define BCSR_SWITCHES_DIP               0x00FF
  83 #define BCSR_SWITCHES_DIP_1             0x0080
  84 #define BCSR_SWITCHES_DIP_2             0x0040
  85 #define BCSR_SWITCHES_DIP_3             0x0020
  86 #define BCSR_SWITCHES_DIP_4             0x0010
  87 #define BCSR_SWITCHES_DIP_5             0x0008
  88 #define BCSR_SWITCHES_DIP_6             0x0004
  89 #define BCSR_SWITCHES_DIP_7             0x0002
  90 #define BCSR_SWITCHES_DIP_8             0x0001
  91 #define BCSR_SWITCHES_ROTARY            0x0F00
  92
  93 #define BCSR_RESETS_PHY0                0x0001
  94 #define BCSR_RESETS_PHY1                0x0002
  95 #define BCSR_RESETS_DC                  0x0004
  96 #define BCSR_RESETS_FIR_SEL             0x2000
  97 #define BCSR_RESETS_IRDA_MODE_MASK      0xC000
  98 #define BCSR_RESETS_IRDA_MODE_FULL      0x0000
  99 #define BCSR_RESETS_IRDA_MODE_OFF       0x4000
 100 #define BCSR_RESETS_IRDA_MODE_2_3       0x8000
 101 #define BCSR_RESETS_IRDA_MODE_1_3       0xC000
 102
 103 #define BCSR_PCMCIA_PC0VPP              0x0003
 104 #define BCSR_PCMCIA_PC0VCC              0x000C
 105 #define BCSR_PCMCIA_PC0DRVEN            0x0010
 106 #define BCSR_PCMCIA_PC0RST              0x0080
 107 #define BCSR_PCMCIA_PC1VPP              0x0300
 108 #define BCSR_PCMCIA_PC1VCC              0x0C00
 109 #define BCSR_PCMCIA_PC1DRVEN            0x1000
 110 #define BCSR_PCMCIA_PC1RST              0x8000
 111
 112 #define BCSR_BOARD_PCIM66EN             0x0001
 113 #define BCSR_BOARD_SD0_PWR              0x0040
 114 #define BCSR_BOARD_SD1_PWR              0x0080
 115 #define BCSR_BOARD_PCIM33               0x0100
 116 #define BCSR_BOARD_GPIO200RST           0x0400
 117 #define BCSR_BOARD_PCICFG               0x1000
 118 #define BCSR_BOARD_SD0_WP               0x4000
 119 #define BCSR_BOARD_SD1_WP               0x8000
 120
 121 #define BCSR_LEDS_DECIMALS              0x0003
 122 #define BCSR_LEDS_LED0                  0x0100
 123 #define BCSR_LEDS_LED1                  0x0200
 124 #define BCSR_LEDS_LED2                  0x0400
 125 #define BCSR_LEDS_LED3                  0x0800
 126
 127 #define BCSR_SWRESET_RESET              0x0080
 128
 129 /* PCMCIA Db1x00 specific defines */
 130 #define PCMCIA_MAX_SOCK 1
 131 #define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1)
 132
 133 /* VPP/VCC */
 134 #define SET_VCC_VPP(VCC, VPP, SLOT)\
 135         ((((VCC)<<2) | ((VPP)<<0)) << ((SLOT)*8))
 136
 137 /* SD controller macros */
 138 /*
 139  * Detect card.
 140  */
 141 #define mmc_card_inserted(_n_, _res_) \
 142         do { \
 143                 BCSR * const bcsr = (BCSR *)0xAE000000; \
 144                 unsigned long mmc_wp, board_specific; \
 145                 if ((_n_)) { \
 146                         mmc_wp = BCSR_BOARD_SD1_WP; \
 147                 } else { \
 148                         mmc_wp = BCSR_BOARD_SD0_WP; \
 149                 } \
 150                 board_specific = au_readl((unsigned long)(&bcsr->specific)); \
 151                 if (!(board_specific & mmc_wp)) {/* low means card present */ \
 152                         *(int *)(_res_) = 1; \
 153                 } else { \
 154                         *(int *)(_res_) = 0; \
 155                 } \
 156         } while (0)
 157
 158 /*
 159  * Apply power to card slot(s).
 160  */
 161 #define mmc_power_on(_n_) \
 162         do { \
 163                 BCSR * const bcsr = (BCSR *)0xAE000000; \
 164                 unsigned long mmc_pwr, mmc_wp, board_specific; \
 165                 if ((_n_)) { \
 166                         mmc_pwr = BCSR_BOARD_SD1_PWR; \
 167                         mmc_wp = BCSR_BOARD_SD1_WP; \
 168                 } else { \
 169                         mmc_pwr = BCSR_BOARD_SD0_PWR; \
 170                         mmc_wp = BCSR_BOARD_SD0_WP; \
 171                 } \
 172                 board_specific = au_readl((unsigned long)(&bcsr->specific)); \
 173                 if (!(board_specific & mmc_wp)) {/* low means card present */ \
 174                         board_specific |= mmc_pwr; \
 175                         au_writel(board_specific, (int)(&bcsr->specific)); \
 176                         au_sync(); \
 177                 } \
 178         } while (0)
 179
 180
 181 /* NAND defines */
 182 /* Timing values as described in databook, * ns value stripped of
 183  * lower 2 bits.
 184  * These defines are here rather than an SOC1550 generic file because
 185  * the parts chosen on another board may be different and may require
 186  * different timings.
 187  */
 188 #define NAND_T_H                        (18 >> 2)
 189 #define NAND_T_PUL                      (30 >> 2)
 190 #define NAND_T_SU                       (30 >> 2)
 191 #define NAND_T_WH                       (30 >> 2)
 192
 193 /* Bitfield shift amounts */
 194 #define NAND_T_H_SHIFT          0
 195 #define NAND_T_PUL_SHIFT        4
 196 #define NAND_T_SU_SHIFT         8
 197 #define NAND_T_WH_SHIFT         12
 198
 199 #define NAND_TIMING     ((NAND_T_H   & 0xF)     << NAND_T_H_SHIFT)   | \
 200                         ((NAND_T_PUL & 0xF)     << NAND_T_PUL_SHIFT) | \
 201                         ((NAND_T_SU  & 0xF)     << NAND_T_SU_SHIFT)  | \
 202                         ((NAND_T_WH  & 0xF)     << NAND_T_WH_SHIFT)
 203 #define NAND_CS 1
 204
 205 /* should be done by yamon */
 206 #define NAND_STCFG  0x00400005 /* 8-bit NAND */
 207 #define NAND_STTIME 0x00007774 /* valid for 396MHz SD=2 only */
 208 #define NAND_STADDR 0x12000FFF /* physical address 0x20000000 */
 209
 210 #endif /* __ASM_DB1X00_H */
 211