include/asm-ppc/ibm405.h

   1 /*
   2  * Author: Armin Kuster <akuster@mvista.com>
   3  *
   4  * 2002 (c) MontaVista, Software, Inc.  This file is licensed under
   5  * the terms of the GNU General Public License version 2.  This program
   6  * is licensed "as is" without any warranty of any kind, whether express
   7  * or implied.
   8  */
   9
  10 #ifdef __KERNEL__
  11 #ifndef __ASM_IBM405_H__
  12 #define __ASM_IBM405_H__
  13
  14 #ifdef DCRN_BE_BASE
  15 #define DCRN_BEAR       (DCRN_BE_BASE + 0x0)    /* Bus Error Address Register */
  16 #define DCRN_BESR       (DCRN_BE_BASE + 0x1)    /* Bus Error Syndrome Register */
  17 #endif
  18 /* DCRN_BESR */
  19 #define BESR_DSES       0x80000000      /* Data-Side Error Status */
  20 #define BESR_DMES       0x40000000      /* DMA Error Status */
  21 #define BESR_RWS        0x20000000      /* Read/Write Status */
  22 #define BESR_ETMASK     0x1C000000      /* Error Type */
  23 #define ET_PROT 0
  24 #define ET_PARITY       1
  25 #define ET_NCFG 2
  26 #define ET_BUSERR       4
  27 #define ET_BUSTO        6
  28
  29 /* Clock and power management shifts for emacs */
  30 #define IBM_CPM_EMMII   0       /* Shift value for MII */
  31 #define IBM_CPM_EMRX    1       /* Shift value for recv */
  32 #define IBM_CPM_EMTX    2       /* Shift value for MAC */
  33
  34 #ifdef DCRN_CHCR_BASE
  35 #define DCRN_CHCR0      (DCRN_CHCR_BASE + 0x0)  /* Chip Control Register 1 */
  36 #define DCRN_CHCR1      (DCRN_CHCR_BASE + 0x1)  /* Chip Control Register 2 */
  37 #endif
  38 #define CHR1_PCIPW      0x00008000      /* PCI Int enable/Peripheral Write enable */
  39
  40 #ifdef DCRN_CHPSR_BASE
  41 #define DCRN_CHPSR      (DCRN_CHPSR_BASE + 0x0) /* Chip Pin Strapping */
  42 #endif
  43
  44 #ifdef DCRN_CPMFR_BASE
  45 #define DCRN_CPMFR      (DCRN_CPMFR_BASE + 0x0) /* CPM Force */
  46 #endif
  47
  48 #ifdef DCRN_CPMSR_BASE
  49 #define DCRN_CPMSR      (DCRN_CPMSR_BASE + 0x0) /* CPM Status */
  50 #define DCRN_CPMER      (DCRN_CPMSR_BASE + 0x1) /* CPM Enable */
  51 #endif
  52
  53 #ifdef DCRN_DCP0_BASE
  54 /* Decompression Controller Address */
  55 #define DCRN_DCP0_CFGADDR       (DCRN_DCP0_BASE + 0x0)
  56 /* Decompression Controller Data */
  57 #define DCRN_DCP0_CFGDATA       (DCRN_DCP0_BASE + 0x1)
  58 #else
  59 #define DCRN_DCP0_CFGADDR       0x0
  60 #define DCRN_DCP0_CFGDATA       0x0
  61 #endif
  62
  63 #ifdef DCRN_DMA0_BASE
  64 /* DMA Channel Control Register 0 */
  65 #define DCRN_DMACR0     (DCRN_DMA0_BASE + 0x0)
  66 #define DCRN_DMACT0     (DCRN_DMA0_BASE + 0x1)  /* DMA Count Register 0 */
  67 /* DMA Destination Address Register 0 */
  68 #define DCRN_DMADA0     (DCRN_DMA0_BASE + 0x2)
  69 /* DMA Source Address Register 0 */
  70 #define DCRN_DMASA0     (DCRN_DMA0_BASE + 0x3)
  71 #ifdef DCRNCAP_DMA_CC
  72 /* DMA Chained Count Register 0 */
  73 #define DCRN_DMACC0     (DCRN_DMA0_BASE + 0x4)
  74 #endif
  75 #ifdef DCRNCAP_DMA_SG
  76 /* DMA Scatter/Gather Descriptor Addr 0 */
  77 #define DCRN_ASG0       (DCRN_DMA0_BASE + 0x4)
  78 #endif
  79 #endif
  80
  81 #ifdef DCRN_DMA1_BASE
  82 /* DMA Channel Control Register 1 */
  83 #define DCRN_DMACR1     (DCRN_DMA1_BASE + 0x0)
  84 #define DCRN_DMACT1     (DCRN_DMA1_BASE + 0x1)  /* DMA Count Register 1 */
  85 /* DMA Destination Address Register 1 */
  86 #define DCRN_DMADA1     (DCRN_DMA1_BASE + 0x2)
  87 /* DMA Source Address Register 1 */
  88 #define DCRN_DMASA1     (DCRN_DMA1_BASE + 0x3)  /* DMA Source Address Register 1 */
  89 #ifdef DCRNCAP_DMA_CC
  90 /* DMA Chained Count Register 1 */
  91 #define DCRN_DMACC1     (DCRN_DMA1_BASE + 0x4)
  92 #endif
  93 #ifdef DCRNCAP_DMA_SG
  94 /* DMA Scatter/Gather Descriptor Addr 1 */
  95 #define DCRN_ASG1       (DCRN_DMA1_BASE + 0x4)
  96 #endif
  97 #endif
  98
  99 #ifdef DCRN_DMA2_BASE
 100 #define DCRN_DMACR2     (DCRN_DMA2_BASE + 0x0)  /* DMA Channel Control Register 2 */
 101 #define DCRN_DMACT2     (DCRN_DMA2_BASE + 0x1)  /* DMA Count Register 2 */
 102 #define DCRN_DMADA2     (DCRN_DMA2_BASE + 0x2)  /* DMA Destination Address Register 2 */
 103 #define DCRN_DMASA2     (DCRN_DMA2_BASE + 0x3)  /* DMA Source Address Register 2 */
 104 #ifdef DCRNCAP_DMA_CC
 105 #define DCRN_DMACC2     (DCRN_DMA2_BASE + 0x4)  /* DMA Chained Count Register 2 */
 106 #endif
 107 #ifdef DCRNCAP_DMA_SG
 108 #define DCRN_ASG2       (DCRN_DMA2_BASE + 0x4)  /* DMA Scatter/Gather Descriptor Addr 2 */
 109 #endif
 110 #endif
 111
 112 #ifdef DCRN_DMA3_BASE
 113 #define DCRN_DMACR3     (DCRN_DMA3_BASE + 0x0)  /* DMA Channel Control Register 3 */
 114 #define DCRN_DMACT3     (DCRN_DMA3_BASE + 0x1)  /* DMA Count Register 3 */
 115 #define DCRN_DMADA3     (DCRN_DMA3_BASE + 0x2)  /* DMA Destination Address Register 3 */
 116 #define DCRN_DMASA3     (DCRN_DMA3_BASE + 0x3)  /* DMA Source Address Register 3 */
 117 #ifdef DCRNCAP_DMA_CC
 118 #define DCRN_DMACC3     (DCRN_DMA3_BASE + 0x4)  /* DMA Chained Count Register 3 */
 119 #endif
 120 #ifdef DCRNCAP_DMA_SG
 121 #define DCRN_ASG3       (DCRN_DMA3_BASE + 0x4)  /* DMA Scatter/Gather Descriptor Addr 3 */
 122 #endif
 123 #endif
 124
 125 #ifdef DCRN_DMASR_BASE
 126 #define DCRN_DMASR      (DCRN_DMASR_BASE + 0x0) /* DMA Status Register */
 127 #ifdef DCRNCAP_DMA_SG
 128 #define DCRN_ASGC       (DCRN_DMASR_BASE + 0x3) /* DMA Scatter/Gather Command */
 129 /* don't know if these two registers always exist if scatter/gather exists */
 130 #define DCRN_POL        (DCRN_DMASR_BASE + 0x6) /* DMA Polarity Register */
 131 #define DCRN_SLP        (DCRN_DMASR_BASE + 0x5) /* DMA Sleep Register */
 132 #endif
 133 #endif
 134
 135 #ifdef DCRN_EBC_BASE
 136 #define DCRN_EBCCFGADR  (DCRN_EBC_BASE + 0x0)   /* Peripheral Controller Address */
 137 #define DCRN_EBCCFGDATA (DCRN_EBC_BASE + 0x1)   /* Peripheral Controller Data */
 138 #endif
 139
 140 #ifdef DCRN_EXIER_BASE
 141 #define DCRN_EXIER      (DCRN_EXIER_BASE + 0x0) /* External Interrupt Enable Register */
 142 #endif
 143
 144 #ifdef DCRN_EXISR_BASE
 145 #define DCRN_EXISR      (DCRN_EXISR_BASE + 0x0) /* External Interrupt Status Register */
 146 #endif
 147
 148 #define EXIER_CIE       0x80000000      /* Critical Interrupt Enable */
 149 #define EXIER_SRIE      0x08000000      /* Serial Port Rx Int. Enable */
 150 #define EXIER_STIE      0x04000000      /* Serial Port Tx Int. Enable */
 151 #define EXIER_JRIE      0x02000000      /* JTAG Serial Port Rx Int. Enable */
 152 #define EXIER_JTIE      0x01000000      /* JTAG Serial Port Tx Int. Enable */
 153 #define EXIER_D0IE      0x00800000      /* DMA Channel 0 Interrupt Enable */
 154 #define EXIER_D1IE      0x00400000      /* DMA Channel 1 Interrupt Enable */
 155 #define EXIER_D2IE      0x00200000      /* DMA Channel 2 Interrupt Enable */
 156 #define EXIER_D3IE      0x00100000      /* DMA Channel 3 Interrupt Enable */
 157 #define EXIER_E0IE      0x00000010      /* External Interrupt 0 Enable */
 158 #define EXIER_E1IE      0x00000008      /* External Interrupt 1 Enable */
 159 #define EXIER_E2IE      0x00000004      /* External Interrupt 2 Enable */
 160 #define EXIER_E3IE      0x00000002      /* External Interrupt 3 Enable */
 161 #define EXIER_E4IE      0x00000001      /* External Interrupt 4 Enable */
 162
 163 #ifdef DCRN_IOCR_BASE
 164 #define DCRN_IOCR       (DCRN_IOCR_BASE + 0x0)  /* Input/Output Configuration Register */
 165 #endif
 166 #define IOCR_E0TE       0x80000000
 167 #define IOCR_E0LP       0x40000000
 168 #define IOCR_E1TE       0x20000000
 169 #define IOCR_E1LP       0x10000000
 170 #define IOCR_E2TE       0x08000000
 171 #define IOCR_E2LP       0x04000000
 172 #define IOCR_E3TE       0x02000000
 173 #define IOCR_E3LP       0x01000000
 174 #define IOCR_E4TE       0x00800000
 175 #define IOCR_E4LP       0x00400000
 176 #define IOCR_EDT        0x00080000
 177 #define IOCR_SOR        0x00040000
 178 #define IOCR_EDO        0x00008000
 179 #define IOCR_2XC        0x00004000
 180 #define IOCR_ATC        0x00002000
 181 #define IOCR_SPD        0x00001000
 182 #define IOCR_BEM        0x00000800
 183 #define IOCR_PTD        0x00000400
 184 #define IOCR_ARE        0x00000080
 185 #define IOCR_DRC        0x00000020
 186 #define IOCR_RDM(x)     (((x) & 0x3) << 3)
 187 #define IOCR_TCS        0x00000004
 188 #define IOCR_SCS        0x00000002
 189 #define IOCR_SPC        0x00000001
 190
 191 #define DCRN_MALCR(base)        (base + 0x0)    /* MAL Configuration */
 192 #define DCRN_MALDBR(base)       ((base) + 0x3)  /* Debug Register */
 193 #define DCRN_MALESR(base)       ((base) + 0x1)  /* Error Status */
 194 #define DCRN_MALIER(base)       ((base) + 0x2)  /* Interrupt Enable */
 195 #define DCRN_MALTXCARR(base)    ((base) + 0x5)  /* TX Channed Active Reset Register */
 196 #define DCRN_MALTXCASR(base)    ((base) + 0x4)  /* TX Channel Active Set Register */
 197 #define DCRN_MALTXDEIR(base)    ((base) + 0x7)  /* Tx Descriptor Error Interrupt */
 198 #define DCRN_MALTXEOBISR(base)  ((base) + 0x6)  /* Tx End of Buffer Interrupt Status */
 199 #define DCRN_MALRXCARR(base)    ((base) + 0x11) /* RX Channed Active Reset Register */
 200 #define DCRN_MALRXCASR(base)    ((base) + 0x10) /* RX Channel Active Set Register */
 201 #define DCRN_MALRXDEIR(base)    ((base) + 0x13) /* Rx Descriptor Error Interrupt */
 202 #define DCRN_MALRXEOBISR(base)  ((base) + 0x12) /* Rx End of Buffer Interrupt Status */
 203 #define DCRN_MALRXCTP0R(base)   ((base) + 0x40) /* Channel Rx 0 Channel Table Pointer */
 204 #define DCRN_MALRXCTP1R(base)   ((base) + 0x41) /* Channel Rx 1 Channel Table Pointer */
 205 #define DCRN_MALTXCTP0R(base)   ((base) + 0x20) /* Channel Tx 0 Channel Table Pointer */
 206 #define DCRN_MALTXCTP1R(base)   ((base) + 0x21) /* Channel Tx 1 Channel Table Pointer */
 207 #define DCRN_MALTXCTP2R(base)   ((base) + 0x22) /* Channel Tx 2 Channel Table Pointer */
 208 #define DCRN_MALTXCTP3R(base)   ((base) + 0x23) /* Channel Tx 3 Channel Table Pointer */
 209 #define DCRN_MALRCBS0(base)     ((base) + 0x60) /* Channel Rx 0 Channel Buffer Size */
 210 #define DCRN_MALRCBS1(base)     ((base) + 0x61) /* Channel Rx 1 Channel Buffer Size */
 211
 212  /* DCRN_MALCR */
 213 #define MALCR_MMSR              0x80000000      /* MAL Software reset */
 214 #define MALCR_PLBP_1            0x00400000      /* MAL reqest priority: */
 215 #define MALCR_PLBP_2            0x00800000      /* lowsest is 00 */
 216 #define MALCR_PLBP_3            0x00C00000      /* highest */
 217 #define MALCR_GA                0x00200000      /* Guarded Active Bit */
 218 #define MALCR_OA                0x00100000      /* Ordered Active Bit */
 219 #define MALCR_PLBLE             0x00080000      /* PLB Lock Error Bit */
 220 #define MALCR_PLBLT_1           0x00040000      /* PLB Latency Timer */
 221 #define MALCR_PLBLT_2           0x00020000
 222 #define MALCR_PLBLT_3           0x00010000
 223 #define MALCR_PLBLT_4           0x00008000
 224 #define MALCR_PLBLT_DEFAULT     0x00078000      /* JSP: Is this a valid default?? */
 225 #define MALCR_PLBB              0x00004000      /* PLB Burst Deactivation Bit */
 226 #define MALCR_OPBBL             0x00000080      /* OPB Lock Bit */
 227 #define MALCR_EOPIE             0x00000004      /* End Of Packet Interrupt Enable */
 228 #define MALCR_LEA               0x00000002      /* Locked Error Active */
 229 #define MALCR_MSD               0x00000001      /* MAL Scroll Descriptor Bit */
 230 /* DCRN_MALESR */
 231 #define MALESR_EVB              0x80000000      /* Error Valid Bit */
 232 #define MALESR_CIDRX            0x40000000      /* Channel ID Receive */
 233 #define MALESR_DE               0x00100000      /* Descriptor Error */
 234 #define MALESR_OEN              0x00080000      /* OPB Non-Fullword Error */
 235 #define MALESR_OTE              0x00040000      /* OPB Timeout Error */
 236 #define MALESR_OSE              0x00020000      /* OPB Slave Error */
 237 #define MALESR_PEIN             0x00010000      /* PLB Bus Error Indication */
 238 #define MALESR_DEI              0x00000010      /* Descriptor Error Interrupt */
 239 #define MALESR_ONEI             0x00000008      /* OPB Non-Fullword Error Interrupt */
 240 #define MALESR_OTEI             0x00000004      /* OPB Timeout Error Interrupt */
 241 #define MALESR_OSEI             0x00000002      /* OPB Slace Error Interrupt */
 242 #define MALESR_PBEI             0x00000001      /* PLB Bus Error Interrupt */
 243 /* DCRN_MALIER */
 244 #define MALIER_DE               0x00000010      /* Descriptor Error Interrupt Enable */
 245 #define MALIER_NE               0x00000008      /* OPB Non-word Transfer Int Enable */
 246 #define MALIER_TE               0x00000004      /* OPB Time Out Error Interrupt Enable */
 247 #define MALIER_OPBE             0x00000002      /* OPB Slave Error Interrupt Enable */
 248 #define MALIER_PLBE             0x00000001      /* PLB Error Interrupt Enable */
 249 /* DCRN_MALTXEOBISR */
 250 #define MALOBISR_CH0            0x80000000      /* EOB channel 1 bit */
 251 #define MALOBISR_CH2            0x40000000      /* EOB channel 2 bit */
 252
 253 #ifdef DCRN_PLB0_BASE
 254 #define DCRN_PLB0_BESR  (DCRN_PLB0_BASE + 0x0)
 255 #define DCRN_PLB0_BEAR  (DCRN_PLB0_BASE + 0x2)
 256 /* doesn't exist on stb03xxx? */
 257 #define DCRN_PLB0_ACR   (DCRN_PLB0_BASE + 0x3)
 258 #endif
 259
 260 #ifdef DCRN_PLB1_BASE
 261 #define DCRN_PLB1_BESR  (DCRN_PLB1_BASE + 0x0)
 262 #define DCRN_PLB1_BEAR  (DCRN_PLB1_BASE + 0x1)
 263 /* doesn't exist on stb03xxx? */
 264 #define DCRN_PLB1_ACR   (DCRN_PLB1_BASE + 0x2)
 265 #endif
 266
 267 #ifdef DCRN_PLLMR_BASE
 268 #define DCRN_PLLMR      (DCRN_PLLMR_BASE + 0x0) /* PL1 Mode */
 269 #endif
 270
 271 #ifdef DCRN_POB0_BASE
 272 #define DCRN_POB0_BESR0 (DCRN_POB0_BASE + 0x0)
 273 #define DCRN_POB0_BEAR  (DCRN_POB0_BASE + 0x2)
 274 #define DCRN_POB0_BESR1 (DCRN_POB0_BASE + 0x4)
 275 #endif
 276
 277 #define DCRN_UIC_SR(base)       (base + 0x0)
 278 #define DCRN_UIC_ER(base)       (base + 0x2)
 279 #define DCRN_UIC_CR(base)       (base + 0x3)
 280 #define DCRN_UIC_PR(base)       (base + 0x4)
 281 #define DCRN_UIC_TR(base)       (base + 0x5)
 282 #define DCRN_UIC_MSR(base)      (base + 0x6)
 283 #define DCRN_UIC_VR(base)       (base + 0x7)
 284 #define DCRN_UIC_VCR(base)      (base + 0x8)
 285
 286 #ifdef DCRN_SDRAM0_BASE
 287 #define DCRN_SDRAM0_CFGADDR     (DCRN_SDRAM0_BASE + 0x0)        /* Memory Controller Address */
 288 #define DCRN_SDRAM0_CFGDATA     (DCRN_SDRAM0_BASE + 0x1)        /* Memory Controller Data */
 289 #endif
 290
 291 #ifdef DCRN_OCM0_BASE
 292 #define DCRN_OCMISARC   (DCRN_OCM0_BASE + 0x0)  /* OCM Instr Side Addr Range Compare */
 293 #define DCRN_OCMISCR    (DCRN_OCM0_BASE + 0x1)  /* OCM Instr Side Control */
 294 #define DCRN_OCMDSARC   (DCRN_OCM0_BASE + 0x2)  /* OCM Data Side Addr Range Compare */
 295 #define DCRN_OCMDSCR    (DCRN_OCM0_BASE + 0x3)  /* OCM Data Side Control */
 296 #endif
 297
 298 #endif                          /* __ASM_IBM405_H__ */
 299 #endif                          /* __KERNEL__ */