include/asm-sparc/system.h

   1 /* $Id: system.h,v 1.86 2001/10/30 04:57:10 davem Exp $ */
   2 #include <linux/config.h>
   3
   4 #ifndef __SPARC_SYSTEM_H
   5 #define __SPARC_SYSTEM_H
   6
   7 #include <linux/config.h>
   8 #include <linux/kernel.h>
   9 #include <linux/threads.h>      /* NR_CPUS */
  10 #include <linux/thread_info.h>
  11
  12 #include <asm/page.h>
  13 #include <asm/psr.h>
  14 #include <asm/ptrace.h>
  15 #include <asm/btfixup.h>
  16
  17 #ifndef __ASSEMBLY__
  18
  19 /*
  20  * Sparc (general) CPU types
  21  */
  22 enum sparc_cpu {
  23   sun4        = 0x00,
  24   sun4c       = 0x01,
  25   sun4m       = 0x02,
  26   sun4d       = 0x03,
  27   sun4e       = 0x04,
  28   sun4u       = 0x05, /* V8 ploos ploos */
  29   sun_unknown = 0x06,
  30   ap1000      = 0x07, /* almost a sun4m */
  31 };
  32
  33 /* Really, userland should not be looking at any of this... */
  34 #ifdef __KERNEL__
  35
  36 extern enum sparc_cpu sparc_cpu_model;
  37
  38 #ifndef CONFIG_SUN4
  39 #define ARCH_SUN4C_SUN4 (sparc_cpu_model==sun4c)
  40 #define ARCH_SUN4 0
  41 #else
  42 #define ARCH_SUN4C_SUN4 1
  43 #define ARCH_SUN4 1
  44 #endif
  45
  46 #define SUN4M_NCPUS            4              /* Architectural limit of sun4m. */
  47
  48 extern struct thread_info *current_set[NR_CPUS];
  49
  50 extern unsigned long empty_bad_page;
  51 extern unsigned long empty_bad_page_table;
  52 extern unsigned long empty_zero_page;
  53
  54 extern void sun_do_break(void);
  55 extern int serial_console;
  56 extern int stop_a_enabled;
  57
  58 static __inline__ int con_is_present(void)
  59 {
  60         return serial_console ? 0 : 1;
  61 }
  62
  63 /* When a context switch happens we must flush all user windows so that
  64  * the windows of the current process are flushed onto its stack. This
  65  * way the windows are all clean for the next process and the stack
  66  * frames are up to date.
  67  */
  68 extern void flush_user_windows(void);
  69 extern void kill_user_windows(void);
  70 extern void synchronize_user_stack(void);
  71 extern void fpsave(unsigned long *fpregs, unsigned long *fsr,
  72                    void *fpqueue, unsigned long *fpqdepth);
  73
  74 #ifdef CONFIG_SMP
  75 #define SWITCH_ENTER(prv) \
  76         do {                    \
  77         if (test_tsk_thread_flag(prv, TIF_USEDFPU)) { \
  78                 put_psr(get_psr() | PSR_EF); \
  79                 fpsave(&(prv)->thread.float_regs[0], &(prv)->thread.fsr, \
  80                        &(prv)->thread.fpqueue[0], &(prv)->thread.fpqdepth); \
  81                 clear_tsk_thread_flag(prv, TIF_USEDFPU); \
  82                 (prv)->thread.kregs->psr &= ~PSR_EF; \
  83         } \
  84         } while(0)
  85
  86 #define SWITCH_DO_LAZY_FPU(next)        /* */
  87 #else
  88 #define SWITCH_ENTER(prv)               /* */
  89 #define SWITCH_DO_LAZY_FPU(nxt) \
  90         do {                    \
  91         if (last_task_used_math != (nxt))               \
  92                 (nxt)->thread.kregs->psr&=~PSR_EF;      \
  93         } while(0)
  94 #endif
  95
  96 /*
  97  * Flush windows so that the VM switch which follows
  98  * would not pull the stack from under us.
  99  *
 100  * SWITCH_ENTER and SWITH_DO_LAZY_FPU do not work yet (e.g. SMP does not work)
 101  * XXX WTF is the above comment? Found in late teen 2.4.x.
 102  */
 103 #define prepare_arch_switch(next) do { \
 104         __asm__ __volatile__( \
 105         ".globl\tflush_patch_switch\nflush_patch_switch:\n\t" \
 106         "save %sp, -0x40, %sp; save %sp, -0x40, %sp; save %sp, -0x40, %sp\n\t" \
 107         "save %sp, -0x40, %sp; save %sp, -0x40, %sp; save %sp, -0x40, %sp\n\t" \
 108         "save %sp, -0x40, %sp\n\t" \
 109         "restore; restore; restore; restore; restore; restore; restore"); \
 110 } while(0)
 111
 112         /* Much care has gone into this code, do not touch it.
 113          *
 114          * We need to loadup regs l0/l1 for the newly forked child
 115          * case because the trap return path relies on those registers
 116          * holding certain values, gcc is told that they are clobbered.
 117          * Gcc needs registers for 3 values in and 1 value out, so we
 118          * clobber every non-fixed-usage register besides l2/l3/o4/o5.  -DaveM
 119          *
 120          * Hey Dave, that do not touch sign is too much of an incentive
 121          * - Anton & Pete
 122          */
 123 #define switch_to(prev, next, last) do {                                                \
 124         SWITCH_ENTER(prev);                                                             \
 125         SWITCH_DO_LAZY_FPU(next);                                                       \
 126         cpu_set(smp_processor_id(), next->active_mm->cpu_vm_mask);                      \
 127         __asm__ __volatile__(                                                           \
 128         "sethi  %%hi(here - 0x8), %%o7\n\t"                                             \
 129         "mov    %%g6, %%g3\n\t"                                                         \
 130         "or     %%o7, %%lo(here - 0x8), %%o7\n\t"                                       \
 131         "rd     %%psr, %%g4\n\t"                                                        \
 132         "std    %%sp, [%%g6 + %4]\n\t"                                                  \
 133         "rd     %%wim, %%g5\n\t"                                                        \
 134         "wr     %%g4, 0x20, %%psr\n\t"                                                  \
 135         "nop\n\t"                                                                       \
 136         "std    %%g4, [%%g6 + %3]\n\t"                                                  \
 137         "ldd    [%2 + %3], %%g4\n\t"                                                    \
 138         "mov    %2, %%g6\n\t"                                                           \
 139         ".globl patchme_store_new_current\n"                                            \
 140 "patchme_store_new_current:\n\t"                                                        \
 141         "st     %2, [%1]\n\t"                                                           \
 142         "wr     %%g4, 0x20, %%psr\n\t"                                                  \
 143         "nop\n\t"                                                                       \
 144         "nop\n\t"                                                                       \
 145         "nop\n\t"       /* LEON needs all 3 nops: load to %sp depends on CWP. */                \
 146         "ldd    [%%g6 + %4], %%sp\n\t"                                                  \
 147         "wr     %%g5, 0x0, %%wim\n\t"                                                   \
 148         "ldd    [%%sp + 0x00], %%l0\n\t"                                                \
 149         "ldd    [%%sp + 0x38], %%i6\n\t"                                                \
 150         "wr     %%g4, 0x0, %%psr\n\t"                                                   \
 151         "nop\n\t"                                                                       \
 152         "nop\n\t"                                                                       \
 153         "jmpl   %%o7 + 0x8, %%g0\n\t"                                                   \
 154         " ld    [%%g3 + %5], %0\n\t"                                                    \
 155         "here:\n"                                                                       \
 156         : "=&r" (last)                                                                  \
 157         : "r" (&(current_set[hard_smp_processor_id()])),        \
 158           "r" ((next)->thread_info),                            \
 159           "i" (TI_KPSR),                                        \
 160           "i" (TI_KSP),                                         \
 161           "i" (TI_TASK)                                         \
 162         :       "g1", "g2", "g3", "g4", "g5",       "g7",       \
 163           "l0", "l1",       "l3", "l4", "l5", "l6", "l7",       \
 164           "i0", "i1", "i2", "i3", "i4", "i5",                   \
 165           "o0", "o1", "o2", "o3",                   "o7");      \
 166         } while(0)
 167
 168 /*
 169  * Changing the IRQ level on the Sparc.
 170  */
 171 extern void local_irq_restore(unsigned long);
 172 extern unsigned long __local_irq_save(void);
 173 extern void local_irq_enable(void);
 174
 175 static inline unsigned long getipl(void)
 176 {
 177         unsigned long retval;
 178
 179         __asm__ __volatile__("rd        %%psr, %0" : "=r" (retval));
 180         return retval;
 181 }
 182
 183 #define local_save_flags(flags) ((flags) = getipl())
 184 #define local_irq_save(flags)   ((flags) = __local_irq_save())
 185 #define local_irq_disable()     ((void) __local_irq_save())
 186 #define irqs_disabled()         ((getipl() & PSR_PIL) != 0)
 187
 188 /* XXX Change this if we ever use a PSO mode kernel. */
 189 #define mb()    __asm__ __volatile__ ("" : : : "memory")
 190 #define rmb()   mb()
 191 #define wmb()   mb()
 192 #define read_barrier_depends()  do { } while(0)
 193 #define set_mb(__var, __value)  do { __var = __value; mb(); } while(0)
 194 #define set_wmb(__var, __value) set_mb(__var, __value)
 195 #define smp_mb()        __asm__ __volatile__("":::"memory")
 196 #define smp_rmb()       __asm__ __volatile__("":::"memory")
 197 #define smp_wmb()       __asm__ __volatile__("":::"memory")
 198 #define smp_read_barrier_depends()      do { } while(0)
 199
 200 #define nop() __asm__ __volatile__ ("nop")
 201
 202 /* This has special calling conventions */
 203 #ifndef CONFIG_SMP
 204 BTFIXUPDEF_CALL(void, ___xchg32, void)
 205 #endif
 206
 207 static inline unsigned long xchg_u32(__volatile__ unsigned long *m, unsigned long val)
 208 {
 209 #ifdef CONFIG_SMP
 210         __asm__ __volatile__("swap [%2], %0"
 211                              : "=&r" (val)
 212                              : "0" (val), "r" (m)
 213                              : "memory");
 214         return val;
 215 #else
 216         register unsigned long *ptr asm("g1");
 217         register unsigned long ret asm("g2");
 218
 219         ptr = (unsigned long *) m;
 220         ret = val;
 221
 222         /* Note: this is magic and the nop there is
 223            really needed. */
 224         __asm__ __volatile__(
 225         "mov    %%o7, %%g4\n\t"
 226         "call   ___f____xchg32\n\t"
 227         " nop\n\t"
 228         : "=&r" (ret)
 229         : "0" (ret), "r" (ptr)
 230         : "g3", "g4", "g7", "memory", "cc");
 231
 232         return ret;
 233 #endif
 234 }
 235
 236 #define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
 237 #define tas(ptr) (xchg((ptr),1))
 238
 239 extern void __xchg_called_with_bad_pointer(void);
 240
 241 static __inline__ unsigned long __xchg(unsigned long x, __volatile__ void * ptr, int size)
 242 {
 243         switch (size) {
 244         case 4:
 245                 return xchg_u32(ptr, x);
 246         };
 247         __xchg_called_with_bad_pointer();
 248         return x;
 249 }
 250
 251 extern void die_if_kernel(char *str, struct pt_regs *regs) __attribute__ ((noreturn));
 252
 253 #endif /* __KERNEL__ */
 254
 255 #endif /* __ASSEMBLY__ */
 256
 257 #define arch_align_stack(x) (x)
 258
 259 #endif /* !(__SPARC_SYSTEM_H) */