include/linux/fd1772.h

   1 #ifndef _LINUX_FD1772REG_H
   2 #define _LINUX_FD1772REG_H
   3
   4 /*
   5 ** WD1772 stuff - originally from the M68K Linux
   6  * Modified for Archimedes by Dave Gilbert (gilbertd@cs.man.ac.uk)
   7  */
   8
   9 /* register codes */
  10
  11 #define FDC1772SELREG_STP   (0x80)   /* command/status register */
  12 #define FDC1772SELREG_TRA   (0x82)   /* track register */
  13 #define FDC1772SELREG_SEC   (0x84)   /* sector register */
  14 #define FDC1772SELREG_DTA   (0x86)   /* data register */
  15
  16 /* register names for FDC1772_READ/WRITE macros */
  17
  18 #define FDC1772REG_CMD         0
  19 #define FDC1772REG_STATUS      0
  20 #define FDC1772REG_TRACK       2
  21 #define FDC1772REG_SECTOR      4
  22 #define FDC1772REG_DATA                6
  23
  24 /* command opcodes */
  25
  26 #define FDC1772CMD_RESTORE  (0x00)   /*  -                   */
  27 #define FDC1772CMD_SEEK     (0x10)   /*   |                  */
  28 #define FDC1772CMD_STEP     (0x20)   /*   |  TYP 1 Commands  */
  29 #define FDC1772CMD_STIN     (0x40)   /*   |                  */
  30 #define FDC1772CMD_STOT     (0x60)   /*  -                   */
  31 #define FDC1772CMD_RDSEC    (0x80)   /*  -   TYP 2 Commands  */
  32 #define FDC1772CMD_WRSEC    (0xa0)   /*  -          "        */
  33 #define FDC1772CMD_RDADR    (0xc0)   /*  -                   */
  34 #define FDC1772CMD_RDTRA    (0xe0)   /*   |  TYP 3 Commands  */
  35 #define FDC1772CMD_WRTRA    (0xf0)   /*  -                   */
  36 #define FDC1772CMD_FORCI    (0xd0)   /*  -   TYP 4 Command   */
  37
  38 /* command modifier bits */
  39
  40 #define FDC1772CMDADD_SR6   (0x00)   /* step rate settings */
  41 #define FDC1772CMDADD_SR12  (0x01)
  42 #define FDC1772CMDADD_SR2   (0x02)
  43 #define FDC1772CMDADD_SR3   (0x03)
  44 #define FDC1772CMDADD_V     (0x04)   /* verify */
  45 #define FDC1772CMDADD_H     (0x08)   /* wait for spin-up */
  46 #define FDC1772CMDADD_U     (0x10)   /* update track register */
  47 #define FDC1772CMDADD_M     (0x10)   /* multiple sector access */
  48 #define FDC1772CMDADD_E     (0x04)   /* head settling flag */
  49 #define FDC1772CMDADD_P     (0x02)   /* precompensation */
  50 #define FDC1772CMDADD_A0    (0x01)   /* DAM flag */
  51
  52 /* status register bits */
  53
  54 #define        FDC1772STAT_MOTORON     (0x80)   /* motor on */
  55 #define        FDC1772STAT_WPROT       (0x40)   /* write protected (FDC1772CMD_WR*) */
  56 #define        FDC1772STAT_SPINUP      (0x20)   /* motor speed stable (Type I) */
  57 #define        FDC1772STAT_DELDAM      (0x20)   /* sector has deleted DAM (Type II+III) */
  58 #define        FDC1772STAT_RECNF       (0x10)   /* record not found */
  59 #define        FDC1772STAT_CRC         (0x08)   /* CRC error */
  60 #define        FDC1772STAT_TR00        (0x04)   /* Track 00 flag (Type I) */
  61 #define        FDC1772STAT_LOST        (0x04)   /* Lost Data (Type II+III) */
  62 #define        FDC1772STAT_IDX         (0x02)   /* Index status (Type I) */
  63 #define        FDC1772STAT_DRQ         (0x02)   /* DRQ status (Type II+III) */
  64 #define        FDC1772STAT_BUSY        (0x01)   /* FDC1772 is busy */
  65
  66
  67 /* PSG Port A Bit Nr 0 .. Side Sel .. 0 -> Side 1  1 -> Side 2 */
  68 #define DSKSIDE     (0x01)
  69
  70 #define DSKDRVNONE  (0x06)
  71 #define DSKDRV0     (0x02)
  72 #define DSKDRV1     (0x04)
  73
  74 /* step rates */
  75 #define        FDC1772STEP_6   0x00
  76 #define        FDC1772STEP_12  0x01
  77 #define        FDC1772STEP_2   0x02
  78 #define        FDC1772STEP_3   0x03
  79
  80 #endif