include/asm-arm/arch-sa1100/dma.h

   1 /*
   2  * linux/include/asm-arm/arch-sa1100/dma.h
   3  *
   4  * Generic SA1100 DMA support
   5  *
   6  * Copyright (C) 2000 Nicolas Pitre
   7  *
   8  */
   9
  10 #ifndef __ASM_ARCH_DMA_H
  11 #define __ASM_ARCH_DMA_H
  12
  13 #include <linux/config.h>
  14 #include "hardware.h"
  15
  16
  17 /*
  18  * This is the maximum DMA address that can be DMAd to.
  19  */
  20 #define MAX_DMA_ADDRESS         0xffffffff
  21
  22
  23 /*
  24  * The regular generic DMA interface is inappropriate for the
  25  * SA1100 DMA model.  None of the SA1100 specific drivers using
  26  * DMA are portable anyway so it's pointless to try to twist the
  27  * regular DMA API to accommodate them.
  28  */
  29 #define MAX_DMA_CHANNELS        0
  30
  31 /*
  32  * The SA1100 has six internal DMA channels.
  33  */
  34 #define SA1100_DMA_CHANNELS     6
  35
  36 /*
  37  * Maximum physical DMA buffer size
  38  */
  39 #define MAX_DMA_SIZE            0x1fff
  40 #define CUT_DMA_SIZE            0x1000
  41
  42 /*
  43  * All possible SA1100 devices a DMA channel can be attached to.
  44  */
  45 typedef enum {
  46         DMA_Ser0UDCWr  = DDAR_Ser0UDCWr,   /* Ser. port 0 UDC Write */
  47         DMA_Ser0UDCRd  = DDAR_Ser0UDCRd,   /* Ser. port 0 UDC Read */
  48         DMA_Ser1UARTWr = DDAR_Ser1UARTWr,  /* Ser. port 1 UART Write */
  49         DMA_Ser1UARTRd = DDAR_Ser1UARTRd,  /* Ser. port 1 UART Read */
  50         DMA_Ser1SDLCWr = DDAR_Ser1SDLCWr,  /* Ser. port 1 SDLC Write */
  51         DMA_Ser1SDLCRd = DDAR_Ser1SDLCRd,  /* Ser. port 1 SDLC Read */
  52         DMA_Ser2UARTWr = DDAR_Ser2UARTWr,  /* Ser. port 2 UART Write */
  53         DMA_Ser2UARTRd = DDAR_Ser2UARTRd,  /* Ser. port 2 UART Read */
  54         DMA_Ser2HSSPWr = DDAR_Ser2HSSPWr,  /* Ser. port 2 HSSP Write */
  55         DMA_Ser2HSSPRd = DDAR_Ser2HSSPRd,  /* Ser. port 2 HSSP Read */
  56         DMA_Ser3UARTWr = DDAR_Ser3UARTWr,  /* Ser. port 3 UART Write */
  57         DMA_Ser3UARTRd = DDAR_Ser3UARTRd,  /* Ser. port 3 UART Read */
  58         DMA_Ser4MCP0Wr = DDAR_Ser4MCP0Wr,  /* Ser. port 4 MCP 0 Write (audio) */
  59         DMA_Ser4MCP0Rd = DDAR_Ser4MCP0Rd,  /* Ser. port 4 MCP 0 Read (audio) */
  60         DMA_Ser4MCP1Wr = DDAR_Ser4MCP1Wr,  /* Ser. port 4 MCP 1 Write */
  61         DMA_Ser4MCP1Rd = DDAR_Ser4MCP1Rd,  /* Ser. port 4 MCP 1 Read */
  62         DMA_Ser4SSPWr  = DDAR_Ser4SSPWr,   /* Ser. port 4 SSP Write (16 bits) */
  63         DMA_Ser4SSPRd  = DDAR_Ser4SSPRd    /* Ser. port 4 SSP Read (16 bits) */
  64 } dma_device_t;
  65
  66 typedef struct {
  67         volatile u_long DDAR;
  68         volatile u_long SetDCSR;
  69         volatile u_long ClrDCSR;
  70         volatile u_long RdDCSR;
  71         volatile dma_addr_t DBSA;
  72         volatile u_long DBTA;
  73         volatile dma_addr_t DBSB;
  74         volatile u_long DBTB;
  75 } dma_regs_t;
  76
  77 typedef void (*dma_callback_t)(void *data);
  78
  79 /*
  80  * DMA function prototypes
  81  */
  82
  83 extern int sa1100_request_dma( dma_device_t device, const char *device_id,
  84                                dma_callback_t callback, void *data,
  85                                dma_regs_t **regs );
  86 extern void sa1100_free_dma( dma_regs_t *regs );
  87 extern int sa1100_start_dma( dma_regs_t *regs, dma_addr_t dma_ptr, u_int size );
  88 extern dma_addr_t sa1100_get_dma_pos(dma_regs_t *regs);
  89 extern void sa1100_reset_dma(dma_regs_t *regs);
  90
  91 /**
  92  *      sa1100_stop_dma - stop DMA in progress
  93  *      @regs: identifier for the channel to use
  94  *
  95  *      This stops DMA without clearing buffer pointers. Unlike
  96  *      sa1100_clear_dma() this allows subsequent use of sa1100_resume_dma()
  97  *      or sa1100_get_dma_pos().
  98  *
  99  *      The @regs identifier is provided by a successful call to
 100  *      sa1100_request_dma().
 101  **/
 102
 103 #define sa1100_stop_dma(regs)   ((regs)->ClrDCSR = DCSR_IE|DCSR_RUN)
 104
 105 /**
 106  *      sa1100_resume_dma - resume DMA on a stopped channel
 107  *      @regs: identifier for the channel to use
 108  *
 109  *      This resumes DMA on a channel previously stopped with
 110  *      sa1100_stop_dma().
 111  *
 112  *      The @regs identifier is provided by a successful call to
 113  *      sa1100_request_dma().
 114  **/
 115
 116 #define sa1100_resume_dma(regs) ((regs)->SetDCSR = DCSR_IE|DCSR_RUN)
 117
 118 /**
 119  *      sa1100_clear_dma - clear DMA pointers
 120  *      @regs: identifier for the channel to use
 121  *
 122  *      This clear any DMA state so the DMA engine is ready to restart
 123  *      with new buffers through sa1100_start_dma(). Any buffers in flight
 124  *      are discarded.
 125  *
 126  *      The @regs identifier is provided by a successful call to
 127  *      sa1100_request_dma().
 128  **/
 129
 130 #define sa1100_clear_dma(regs)  ((regs)->ClrDCSR = DCSR_IE|DCSR_RUN|DCSR_STRTA|DCSR_STRTB)
 131
 132 #endif /* _ASM_ARCH_DMA_H */