2 * Copyright (C) 2011, 2012 glevand <geoffrey.levand@mail.ru>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/types.h>
37 #include <sys/ioctl.h>
40 #include <sys/consio.h>
44 #include "ps3gpu_ctl.h"
45 #include "ps3gpu_mth.h"
46 #include "reset_gpu_state.h"
50 main(int argc
, char **argv
)
52 struct ps3gpu_ctl_context_allocate context_allocate
;
53 struct ps3gpu_ctl_context_free context_free
;
55 volatile uint32_t *control
;
56 volatile uint8_t *driver_info
;
57 uint32_t *fifo
, *reset_gpu
, *db
[2], *zb
;
58 unsigned long fifo_handle
, reset_gpu_handle
, db_handle
[2], zb_handle
;
59 unsigned int fifo_gaddr
, reset_gpu_gaddr
, db_gaddr
[2], zb_gaddr
;
65 fd
= open(PS3GPU_DEV_PATH
, O_RDWR
);
71 /* Create GPU context */
73 context_allocate
.vram_size
= 64; /* MB */
75 err
= ioctl(fd
, PS3GPU_CTL_CONTEXT_ALLOCATE
, &context_allocate
);
81 context_id
= context_allocate
.context_id
;
83 printf("context id %d\n", context_id
);
84 printf("control handle 0x%lx size %d\n",
85 context_allocate
.control_handle
, context_allocate
.control_size
);
86 printf("driver_info handle 0x%lx size %d\n",
87 context_allocate
.driver_info_handle
, context_allocate
.driver_info_size
);
89 /* Map control registers */
91 control
= mmap(NULL
, context_allocate
.control_size
,
92 PROT_READ
| PROT_WRITE
, MAP_SHARED
, fd
, context_allocate
.control_handle
);
93 if (control
== (void *) MAP_FAILED
) {
100 driver_info
= mmap(NULL
, context_allocate
.driver_info_size
,
101 PROT_READ
| PROT_WRITE
, MAP_SHARED
, fd
, context_allocate
.driver_info_handle
);
102 if (driver_info
== (void *) MAP_FAILED
) {
107 printf("channel id %d\n", get_channel_id(driver_info
));
108 printf("flip status %d %d\n", get_flip_status(driver_info
, 0), get_flip_status(driver_info
, 1));
112 err
= set_flip_mode(fd
, context_id
, PS3GPU_CTL_HEAD_A
, PS3GPU_CTL_FLIP_MODE_VSYNC
);
114 perror("set_flip_mode");
118 err
= set_flip_mode(fd
, context_id
, PS3GPU_CTL_HEAD_B
, PS3GPU_CTL_FLIP_MODE_VSYNC
);
120 perror("set_flip_mode");
124 /* Reset flip status */
126 err
= reset_flip_status(fd
, context_id
, PS3GPU_CTL_HEAD_A
);
128 perror("reset_flip_status");
132 err
= reset_flip_status(fd
, context_id
, PS3GPU_CTL_HEAD_B
);
134 perror("reset_flip_status");
140 err
= memory_allocate(fd
, context_id
, PS3GPU_CTL_MEMORY_TYPE_GART
,
141 64 * 1024, 12, &fifo_handle
, &fifo_gaddr
, (void **) &fifo
);
143 perror("memory_allocate");
147 printf("FIFO handle 0x%lx gpu addr 0x%08x\n",
148 fifo_handle
, fifo_gaddr
);
152 err
= setup_control(fd
, context_id
, fifo_handle
, fifo_handle
, 0xdeadbabe);
154 perror("setup_control");
158 printf("FIFO put 0x%08x get 0x%08x ref 0x%08x\n",
159 control
[0x10], control
[0x11], control
[0x12]);
161 /* Allocate FIFO for resetting GPU state */
163 err
= memory_allocate(fd
, context_id
, PS3GPU_CTL_MEMORY_TYPE_GART
,
164 4 * 1024, 12, &reset_gpu_handle
, &reset_gpu_gaddr
, (void **) &reset_gpu
);
166 perror("memory_allocate");
170 printf("reset GPU state handle 0x%lx gpu addr 0x%08x\n",
171 reset_gpu_handle
, reset_gpu_gaddr
);
173 memcpy(reset_gpu
, reset_gpu_state_3d
, reset_gpu_state_3d_size
);
177 fifo
[0] = PS3GPU_MTH_HDR(0, 0, reset_gpu_gaddr
| PS3GPU_MTH_ADDR_CALL
);
178 fifo
[1] = PS3GPU_MTH_HDR(1, 0, PS3GPU_MTH_ADDR_REF
);
179 fifo
[2] = 0xcafef00d;
181 control
[0x10] = fifo_gaddr
+ 3 * sizeof(uint32_t);
183 err
= wait_fifo_idle(control
);
185 fprintf(stderr
, "FIFO timeout: put 0x%08x get 0x%08x ref 0x%08x\n",
186 control
[0x10], control
[0x11], control
[0x12]);
187 dump_fifo(stderr
, fifo
, 0x400);
191 printf("FIFO put 0x%08x get 0x%08x ref 0x%08x\n",
192 control
[0x10], control
[0x11], control
[0x12]);
194 /* Allocate display buffers */
196 err
= memory_allocate(fd
, context_id
, PS3GPU_CTL_MEMORY_TYPE_VIDEO
,
197 ROUNDUP(DISPLAY_HEIGHT
* DISPLAY_PITCH
, 4 * 1024), 12,
198 &db_handle
[0], &db_gaddr
[0], (void **) &db
[0]);
200 perror("memory_allocate");
204 printf("DB0 handle 0x%lx gpu addr 0x%08x\n",
205 db_handle
[0], db_gaddr
[0]);
207 err
= memory_allocate(fd
, context_id
, PS3GPU_CTL_MEMORY_TYPE_VIDEO
,
208 ROUNDUP(DISPLAY_HEIGHT
* DISPLAY_PITCH
, 4 * 1024), 12,
209 &db_handle
[1], &db_gaddr
[1], (void **) &db
[1]);
211 perror("memory_allocate");
215 printf("DB1 handle 0x%lx gpu addr 0x%08x\n",
216 db_handle
[1], db_gaddr
[1]);
218 /* Allocate depth buffer */
220 err
= memory_allocate(fd
, context_id
, PS3GPU_CTL_MEMORY_TYPE_VIDEO
,
221 ROUNDUP(DISPLAY_HEIGHT
* DISPLAY_PITCH
, 4 * 1024), 12,
222 &zb_handle
, &zb_gaddr
, (void **) &zb
);
224 perror("memory_allocate");
228 printf("ZB handle 0x%lx gpu addr 0x%08x\n",
229 zb_handle
, zb_gaddr
);
231 /* Set display buffers */
233 err
= display_buffer_set(fd
, context_id
, 0, DISPLAY_WIDTH
, DISPLAY_HEIGHT
,
234 DISPLAY_PITCH
, db_handle
[0]);
236 perror("display_buffer_set");
240 err
= display_buffer_set(fd
, context_id
, 1, DISPLAY_WIDTH
, DISPLAY_HEIGHT
,
241 DISPLAY_PITCH
, db_handle
[1]);
243 perror("display_buffer_set");
247 const struct surface_desc surf_desc
[] = {
248 /* display buffer 0 */
250 .sd_color_loc
= { 0xfeed0000, 0xfeed0000, 0xfeed0000, 0xfeed0000 },
251 .sd_color_off
= { db_gaddr
[0], 0, 0, 0 },
252 .sd_color_pitch
= { DISPLAY_PITCH
, 64, 64, 64 },
254 .sd_color_target
= 0x1,
255 .sd_depth_loc
= 0xfeed0000,
256 .sd_depth_off
= zb_gaddr
,
257 .sd_depth_pitch
= DISPLAY_PITCH
,
261 .sd_w
= DISPLAY_WIDTH
,
262 .sd_h
= DISPLAY_HEIGHT
,
264 /* display buffer 1 */
266 .sd_color_loc
= { 0xfeed0000, 0xfeed0000, 0xfeed0000, 0xfeed0000 },
267 .sd_color_off
= { db_gaddr
[1], 0, 0, 0 },
268 .sd_color_pitch
= { DISPLAY_PITCH
, 64, 64, 64 },
270 .sd_color_target
= 0x1,
271 .sd_depth_loc
= 0xfeed0000,
272 .sd_depth_off
= zb_gaddr
,
273 .sd_depth_pitch
= DISPLAY_PITCH
,
277 .sd_w
= DISPLAY_WIDTH
,
278 .sd_h
= DISPLAY_HEIGHT
,
282 const uint32_t clear_color
[] = {
287 for (i
= 0; i
< ARRAY_SIZE(surf_desc
); i
++) {
288 err
= setup_control(fd
, context_id
, fifo_handle
, fifo_handle
, 0xdeadbabe);
290 perror("setup_control");
294 err
+= set_surface(fifo
+ err
, &surf_desc
[i
]);
295 err
+= set_depth_mask(fifo
+ err
, 0x00000000);
296 err
+= set_color_mask(fifo
+ err
, 0x01010101);
297 err
+= set_color_mask_mrt(fifo
+ err
, 0x00000000);
298 err
+= set_clear_color(fifo
+ err
, clear_color
[i
]);
299 err
+= set_scissor(fifo
+ err
, 0, 0, 4095, 4095);
300 err
+= clear_surface(fifo
+ err
, 0x000000f1);
302 err
+= flip_display_buffer(fifo
+ err
, get_channel_id(driver_info
), i
, 0);
305 * Label with index 0 (head 0) is set by LV1 to 0x00000000 when flip is complete.
306 * Let GPU wait for it.
309 err
+= wait_label(fifo
+ err
, 0, 0x00000000);
311 control
[0x10] = fifo_gaddr
+ err
* sizeof(uint32_t);
313 err
= wait_fifo_idle(control
);
315 fprintf(stderr
, "FIFO timeout: put 0x%08x get 0x%08x ref 0x%08x\n",
316 control
[0x10], control
[0x11], control
[0x12]);
317 dump_fifo(stderr
, fifo
, 0x400);
321 printf("FIFO put 0x%08x get 0x%08x ref 0x%08x\n",
322 control
[0x10], control
[0x11], control
[0x12]);
327 /* Destroy GPU context */
329 context_free
.context_id
= context_id
;
331 err
= ioctl(fd
, PS3GPU_CTL_CONTEXT_FREE
, &context_free
);
342 /* Restore console */
344 ioctl(0, SW_TEXT_80x25
, NULL
);