model_view_proj.c

   1 /*-
   2  * Copyright (C) 2011, 2012 glevand <geoffrey.levand@mail.ru>
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer,
  10  *    without modification, immediately at the beginning of the file.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  *
  15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  16  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  17  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  18  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  19  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  20  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  21  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  22  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  23  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  24  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  25  *
  26  * $FreeBSD$
  27  */
  28
  29 #include <stdio.h>
  30 #include <stdlib.h>
  31 #include <stdint.h>
  32 #include <string.h>
  33
  34 #include <sys/types.h>
  35 #include <sys/stat.h>
  36 #include <sys/uio.h>
  37 #include <sys/ioctl.h>
  38 #include <sys/mman.h>
  39 #include <sys/fbio.h>
  40 #include <sys/consio.h>
  41 #include <fcntl.h>
  42 #include <unistd.h>
  43
  44 #include "ps3gpu_ctl.h"
  45 #include "ps3gpu_mth.h"
  46 #include "reset_gpu_state.h"
  47 #include "util.h"
  48 #include "matrix.h"
  49
  50 int
  51 main(int argc, char **argv)
  52 {
  53         struct ps3gpu_ctl_context_allocate context_allocate;
  54         struct ps3gpu_ctl_context_free context_free;
  55         int context_id;
  56         volatile uint32_t *control;
  57         volatile uint8_t *driver_info;
  58         uint32_t *fifo, *reset_gpu, *db[2], *zb, *fp;
  59         unsigned long fifo_handle, reset_gpu_handle, db_handle[2], zb_handle, fp_handle;
  60         unsigned int fifo_gaddr, reset_gpu_gaddr, db_gaddr[2], zb_gaddr, fp_gaddr;
  61         matrix_t mat_proj, mat_view, mat;
  62         int fd = -1;
  63         int i, err;
  64
  65         /* Open GPU device */
  66
  67         fd = open(PS3GPU_DEV_PATH, O_RDWR);
  68         if (fd < 0) {
  69                 perror("open");
  70                 goto done;
  71         }
  72
  73         /* Create GPU context */
  74
  75         context_allocate.vram_size = 64; /* MB */
  76
  77         err = ioctl(fd, PS3GPU_CTL_CONTEXT_ALLOCATE, &context_allocate);
  78         if (err < 0) {
  79                 perror("ioctl");
  80                 goto done;
  81         }
  82
  83         context_id = context_allocate.context_id;
  84
  85         printf("context id %d\n", context_id);
  86         printf("control handle 0x%lx size %d\n",
  87             context_allocate.control_handle, context_allocate.control_size);
  88         printf("driver_info handle 0x%lx size %d\n",
  89             context_allocate.driver_info_handle, context_allocate.driver_info_size);
  90
  91         /* Map control registers */
  92
  93         control = mmap(NULL, context_allocate.control_size,
  94             PROT_READ | PROT_WRITE, MAP_SHARED, fd, context_allocate.control_handle);
  95         if (control == (void *) MAP_FAILED) {
  96                 perror("mmap");
  97                 goto done;
  98         }
  99
 100         /* Map driver info */
 101
 102         driver_info = mmap(NULL, context_allocate.driver_info_size,
 103             PROT_READ | PROT_WRITE, MAP_SHARED, fd, context_allocate.driver_info_handle);
 104         if (driver_info == (void *) MAP_FAILED) {
 105                 perror("mmap");
 106                 goto done;
 107         }
 108
 109         printf("channel id %d\n", get_channel_id(driver_info));
 110
 111         /* Allocate FIFO */
 112
 113         err = memory_allocate(fd, context_id, PS3GPU_CTL_MEMORY_TYPE_GART,
 114             64 * 1024, 12, &fifo_handle, &fifo_gaddr, (void **) &fifo);
 115         if (err < 0) {
 116                 perror("memory_allocate");
 117                 goto done;
 118         }
 119
 120         printf("FIFO handle 0x%lx gpu addr 0x%08x\n",
 121             fifo_handle, fifo_gaddr);
 122
 123         /* Setup FIFO */
 124
 125         err = setup_control(fd, context_id, fifo_handle, fifo_handle, 0xdeadbabe);
 126         if (err < 0) {
 127                 perror("setup_control");
 128                 goto done;
 129         }
 130
 131         printf("FIFO put 0x%08x get 0x%08x ref 0x%08x\n",
 132             control[0x10], control[0x11], control[0x12]);
 133
 134         /* Allocate FIFO for resetting GPU state */
 135
 136         err = memory_allocate(fd, context_id, PS3GPU_CTL_MEMORY_TYPE_GART,
 137             4 * 1024, 12, &reset_gpu_handle, &reset_gpu_gaddr, (void **)&reset_gpu);
 138         if (err < 0) {
 139                 perror("memory_allocate");
 140                 goto done;
 141         }
 142
 143         printf("reset GPU state handle 0x%lx gpu addr 0x%08x\n",
 144             reset_gpu_handle, reset_gpu_gaddr);
 145
 146         memcpy(reset_gpu, reset_gpu_state_3d, reset_gpu_state_3d_size);
 147
 148         /* Kick FIFO */
 149
 150         fifo[0] = PS3GPU_MTH_HDR(0, 0, reset_gpu_gaddr | PS3GPU_MTH_ADDR_CALL);
 151         fifo[1] = PS3GPU_MTH_HDR(1, 0, PS3GPU_MTH_ADDR_REF);
 152         fifo[2] = 0xcafef00d;
 153
 154         control[0x10] = fifo_gaddr + 3 * sizeof(uint32_t);
 155
 156         err = wait_fifo_idle(control);
 157         if (err < 0) {
 158                 fprintf(stderr, "FIFO timeout: put 0x%08x get 0x%08x ref 0x%08x\n",
 159                     control[0x10], control[0x11], control[0x12]);
 160                 dump_fifo(stderr, fifo, 0x400);
 161                 goto done;
 162         }
 163
 164         printf("FIFO put 0x%08x get 0x%08x ref 0x%08x\n",
 165             control[0x10], control[0x11], control[0x12]);
 166
 167         /* Allocate display buffers */
 168
 169         err = memory_allocate(fd, context_id, PS3GPU_CTL_MEMORY_TYPE_VIDEO,
 170             ROUNDUP(DISPLAY_HEIGHT * DISPLAY_PITCH, 4 * 1024), 12,
 171             &db_handle[0], &db_gaddr[0], (void **) &db[0]);
 172         if (err < 0) {
 173                 perror("memory_allocate");
 174                 goto done;
 175         }
 176
 177         printf("DB0 handle 0x%lx gpu addr 0x%08x\n",
 178             db_handle[0], db_gaddr[0]);
 179
 180         err = memory_allocate(fd, context_id, PS3GPU_CTL_MEMORY_TYPE_VIDEO,
 181             ROUNDUP(DISPLAY_HEIGHT * DISPLAY_PITCH, 4 * 1024), 12,
 182             &db_handle[1], &db_gaddr[1], (void **) &db[1]);
 183         if (err < 0) {
 184                 perror("memory_allocate");
 185                 goto done;
 186         }
 187
 188         printf("DB1 handle 0x%lx gpu addr 0x%08x\n",
 189             db_handle[1], db_gaddr[1]);
 190
 191         /* Allocate depth buffer */
 192
 193         err = memory_allocate(fd, context_id, PS3GPU_CTL_MEMORY_TYPE_VIDEO,
 194             ROUNDUP(DISPLAY_HEIGHT * DISPLAY_PITCH, 4 * 1024), 12,
 195             &zb_handle, &zb_gaddr, (void **) &zb);
 196         if (err < 0) {
 197                 perror("memory_allocate");
 198                 goto done;
 199         }
 200
 201         printf("ZB handle 0x%lx gpu addr 0x%08x\n",
 202             zb_handle, zb_gaddr);
 203
 204         /* Allocate fragment program */
 205
 206         err = memory_allocate(fd, context_id, PS3GPU_CTL_MEMORY_TYPE_VIDEO,
 207             4 * 1024, 12, &fp_handle, &fp_gaddr, (void **) &fp);
 208         if (err < 0) {
 209                 perror("memory_allocate");
 210                 goto done;
 211         }
 212
 213         printf("FP handle 0x%lx gpu addr 0x%08x\n",
 214             fp_handle, fp_gaddr);
 215
 216         /* Set display buffers */
 217
 218         err = display_buffer_set(fd, context_id, 0, DISPLAY_WIDTH, DISPLAY_HEIGHT,
 219             DISPLAY_PITCH, db_handle[0]);
 220         if (err < 0) {
 221                 perror("display_buffer_set");
 222                 goto done;
 223         }
 224
 225         err = display_buffer_set(fd, context_id, 1, DISPLAY_WIDTH, DISPLAY_HEIGHT,
 226             DISPLAY_PITCH, db_handle[1]);
 227         if (err < 0) {
 228                 perror("display_buffer_set");
 229                 goto done;
 230         }
 231
 232         const struct surface_desc surf_desc[] = {
 233                 /* display buffer 0 */
 234                 {
 235                         .sd_color_loc = { 0xfeed0000, 0xfeed0000, 0xfeed0000, 0xfeed0000 },
 236                         .sd_color_off = { db_gaddr[0], 0, 0, 0 },
 237                         .sd_color_pitch = { DISPLAY_PITCH, 64, 64, 64 },
 238                         .sd_color_fmt = 0x8,
 239                         .sd_color_target = 0x1,
 240                         .sd_depth_loc = 0xfeed0000,
 241                         .sd_depth_off = zb_gaddr,
 242                         .sd_depth_pitch = DISPLAY_PITCH,
 243                         .sd_depth_fmt = 0x2,
 244                         .sd_x = 0,
 245                         .sd_y = 0,
 246                         .sd_w = DISPLAY_WIDTH,
 247                         .sd_h = DISPLAY_HEIGHT,
 248                 },
 249                 /* display buffer 1 */
 250                 {
 251                         .sd_color_loc = { 0xfeed0000, 0xfeed0000, 0xfeed0000, 0xfeed0000 },
 252                         .sd_color_off = { db_gaddr[1], 0, 0, 0 },
 253                         .sd_color_pitch = { DISPLAY_PITCH, 64, 64, 64 },
 254                         .sd_color_fmt = 0x8,
 255                         .sd_color_target = 0x1,
 256                         .sd_depth_loc = 0xfeed0000,
 257                         .sd_depth_off = zb_gaddr,
 258                         .sd_depth_pitch = DISPLAY_PITCH,
 259                         .sd_depth_fmt = 0x2,
 260                         .sd_x = 0,
 261                         .sd_y = 0,
 262                         .sd_w = DISPLAY_WIDTH,
 263                         .sd_h = DISPLAY_HEIGHT,
 264                 },
 265         };
 266
 267         const uint32_t clear_color[] = {
 268                 0xff404040,
 269                 0xffffffff,
 270         };
 271
 272         const float vp_offset[] = { DISPLAY_WIDTH * 0.5f, DISPLAY_HEIGHT * 0.5f, 0.5f, 0.0f };
 273         const float vp_scale[] = { DISPLAY_WIDTH * 0.5f, DISPLAY_HEIGHT * 0.5f, 0.5f, 0.0f };
 274
 275         const uint32_t vertex_prg[] = {
 276                 /* MOV o[1], v[3] */
 277                 0x401f9c6c, 0x0040030d, 0x8106c083, 0x6041ff84,
 278                 /* DP4 o[0].w, v[0], c[259] */
 279                 0x401f9c6c, 0x01d0300d, 0x8106c0c3, 0x60403f80,
 280                 /* DP4 o[0].z, v[0], c[258] */
 281                 0x401f9c6c, 0x01d0200d, 0x8106c0c3, 0x60405f80,
 282                 /* DP4 o[0].y, v[0], c[257] */
 283                 0x401f9c6c, 0x01d0100d, 0x8106c0c3, 0x60409f80,
 284                 /* DP4 o[0].x, v[0], c[256] */
 285                 0x401f9c6c, 0x01d0000d, 0x8106c0c3, 0x60411f81,
 286         };
 287
 288         uint32_t frag_prg[] = {
 289                 /* MOVR R0, f[1] */
 290                 0x3e010100, 0xc8011c9d, 0xc8000001, 0xc8003fe1,
 291         };
 292
 293         /*
 294          *            (0.0, -0.5)
 295          *                 /\
 296          *                /  \
 297          *               /    \
 298          *              /      \
 299          * (-0.5, 0.5) /________\ (0.5, 0.5)
 300          *
 301          */
 302
 303         const float triangle_pos[][4] = {
 304                 /* xyzw */
 305                 {  0.0f, -0.5f, -1.0f, 1.0f },
 306                 { -0.5f,  0.5f, -1.0f, 1.0f },
 307                 {  0.5f,  0.5f, -1.0f, 1.0f },
 308         };
 309         const float triangle_color[][4] = {
 310                 /* rgba */
 311                 { 1.0f, 0.0f, 0.0f, 1.0f },
 312                 { 0.0f, 1.0f, 0.0f, 1.0f },
 313                 { 0.0f, 0.0f, 1.0f, 1.0f },
 314         };
 315
 316         err = setup_control(fd, context_id, fifo_handle, fifo_handle, 0xdeadbabe);
 317         if (err < 0) {
 318                 perror("setup_control");
 319                 goto done;
 320         }
 321
 322         printf("FIFO put 0x%08x get 0x%08x ref 0x%08x\n",
 323             control[0x10], control[0x11], control[0x12]);
 324
 325         /* Transfer fragment program to VRAM */
 326
 327         err += transfer_inline(fifo + err, 0xfeed0000, fp_gaddr,
 328             frag_prg, ARRAY_SIZE(frag_prg));
 329
 330         control[0x10] = fifo_gaddr + err * sizeof(uint32_t);
 331
 332         err = wait_fifo_idle(control);
 333         if (err < 0) {
 334                 fprintf(stderr, "FIFO timeout: put 0x%08x get 0x%08x ref 0x%08x\n",
 335                     control[0x10], control[0x11], control[0x12]);
 336                 dump_fifo(stderr, fifo, 0x400);
 337                 goto done;
 338         }
 339
 340         printf("FIFO put 0x%08x get 0x%08x ref 0x%08x\n",
 341             control[0x10], control[0x11], control[0x12]);
 342
 343         for (i = 0; i < ARRAY_SIZE(surf_desc); i++) {
 344                 err = setup_control(fd, context_id, fifo_handle, fifo_handle, 0xdeadbabe);
 345                 if (err < 0) {
 346                         perror("setup_control");
 347                         goto done;
 348                 }
 349
 350                 printf("FIFO put 0x%08x get 0x%08x ref 0x%08x\n",
 351                     control[0x10], control[0x11], control[0x12]);
 352
 353                 err += set_surface(fifo + err, &surf_desc[i]);
 354                 err += set_depth_mask(fifo + err, 0x00000000);
 355                 err += set_color_mask(fifo + err, 0x01010101);
 356                 err += set_color_mask_mrt(fifo + err, 0x00000000);
 357                 err += set_clear_color(fifo + err, clear_color[i]);
 358                 err += set_scissor(fifo + err, 0, 0, 4095, 4095);
 359                 err += clear_surface(fifo + err, 0x000000f1);
 360
 361                 err += set_viewport(fifo + err, 0, 0, DISPLAY_WIDTH, DISPLAY_HEIGHT,
 362                     0.0f, 1.0f, vp_offset, vp_scale);
 363
 364                 /* Compute MVP matrix */
 365
 366                 matrix_proj(mat_proj, -1.0f, 1.0f, -1.0f, 1.0f, 1.0f, 10000.0f);
 367                 matrix_trans(mat_view, 0.0f, 0.0f, -4.0f);
 368                 MATRIX_ELEM(mat_view, 0, 0) = 1.0f / (16.0f / 9.0f);
 369                 matrix_mult(mat, mat_proj, mat_view);
 370
 371                 /* Set vertex shader */
 372
 373                 err += load_vertex_prg(fifo + err, 0, vertex_prg, ARRAY_SIZE(vertex_prg) / 4);
 374                 err += set_vertex_prg_start_slot(fifo + err, 0);
 375                 err += set_vertex_prg_reg_count(fifo + err, 1);
 376                 err += set_vertex_prg_const(fifo + err, 256, 16, mat);
 377                 err += set_vertex_attr_inmask(fifo + err, (1 << 3) | (1 << 0));
 378                 err += set_vertex_attr_outmask(fifo + err, (1 << 2) | (1 << 0));
 379
 380                 /* Set fragment shader */
 381
 382                 err += set_frag_prg(fifo + err, 0x1, fp_gaddr);
 383                 err += frag_prg_ctrl(fifo + err, 2, 0, 0, 0, 0);
 384
 385                 err += set_front_poly_mode(fifo + err, 0x1b02);
 386                 err += set_shade_mode(fifo + err, 0x1d01);
 387
 388                 /* register 0 - position */
 389                 err += set_vertex_data_arrfmt(fifo + err, 0, 0, 0, 0, 2);
 390                 /* register 3 - color */
 391                 err += set_vertex_data_arrfmt(fifo + err, 3, 0, 0, 0, 2);
 392
 393                 err += draw_begin(fifo + err, 0x5);
 394                 err += set_vertex_data_4f(fifo + err, 3, triangle_color[0]);
 395                 err += set_vertex_data_4f(fifo + err, 0, triangle_pos[0]);
 396                 err += set_vertex_data_4f(fifo + err, 3, triangle_color[1]);
 397                 err += set_vertex_data_4f(fifo + err, 0, triangle_pos[1]);
 398                 err += set_vertex_data_4f(fifo + err, 3, triangle_color[2]);
 399                 err += set_vertex_data_4f(fifo + err, 0, triangle_pos[2]);
 400                 err += draw_end(fifo + err);
 401
 402                 err += flip_display_buffer(fifo + err, get_channel_id(driver_info), i, 0);
 403
 404                 /*
 405                  * Label with index 0 (head 0) is set by LV1 to 0x00000000 when flip is complete.
 406                  * Let GPU wait for it.
 407                  */
 408
 409                 err += wait_label(fifo + err, 0, 0x00000000);
 410
 411                 control[0x10] = fifo_gaddr + err * sizeof(uint32_t);
 412
 413                 err = wait_fifo_idle(control);
 414                 if (err < 0) {
 415                         fprintf(stderr, "FIFO timeout: put 0x%08x get 0x%08x ref 0x%08x\n",
 416                             control[0x10], control[0x11], control[0x12]);
 417                         dump_fifo(stderr, fifo, 0x400);
 418                         goto done;
 419                 }
 420
 421                 printf("FIFO put 0x%08x get 0x%08x ref 0x%08x\n",
 422                     control[0x10], control[0x11], control[0x12]);
 423
 424                 usleep(1000000);
 425         }
 426
 427         save_image("image.argb", (const char *) db[0], DISPLAY_PITCH * DISPLAY_HEIGHT);
 428
 429         /* Destroy GPU context */
 430
 431         context_free.context_id = context_id;
 432
 433         err = ioctl(fd, PS3GPU_CTL_CONTEXT_FREE, &context_free);
 434         if (err < 0) {
 435                 perror("ioctl");
 436                 goto done;
 437         }
 438
 439 done:
 440
 441         if (fd >= 0)
 442                 close(fd);
 443
 444         /* Restore console */
 445
 446         ioctl(0, SW_TEXT_80x25, NULL);
 447
 448         exit(0);
 449 }