2 * Copyright (C) 2011, 2012 glevand <geoffrey.levand@mail.ru>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/types.h>
37 #include <sys/ioctl.h>
40 #include <sys/consio.h>
44 #include "ps3gpu_ctl.h"
45 #include "ps3gpu_mth.h"
46 #include "reset_gpu_state.h"
50 main(int argc
, char **argv
)
52 struct ps3gpu_ctl_context_allocate context_allocate
;
53 struct ps3gpu_ctl_context_free context_free
;
55 volatile uint32_t *control
;
56 uint32_t *fifo
, *reset_gpu
, *vram
, *gart
;
57 unsigned long fifo_handle
, reset_gpu_handle
, vram_handle
, gart_handle
;
58 unsigned int fifo_gaddr
, reset_gpu_gaddr
, vram_gaddr
, gart_gaddr
;
64 fd
= open(PS3GPU_DEV_PATH
, O_RDWR
);
70 /* Create GPU context */
72 context_allocate
.vram_size
= 64; /* MB */
74 err
= ioctl(fd
, PS3GPU_CTL_CONTEXT_ALLOCATE
, &context_allocate
);
80 context_id
= context_allocate
.context_id
;
82 printf("context id %d\n", context_id
);
83 printf("control handle 0x%lx size %d\n",
84 context_allocate
.control_handle
, context_allocate
.control_size
);
86 /* Map control registers */
88 control
= mmap(NULL
, context_allocate
.control_size
,
89 PROT_READ
| PROT_WRITE
, MAP_SHARED
, fd
, context_allocate
.control_handle
);
90 if (control
== (void *) MAP_FAILED
) {
97 err
= memory_allocate(fd
, context_id
, PS3GPU_CTL_MEMORY_TYPE_GART
,
98 64 * 1024, 12, &fifo_handle
, &fifo_gaddr
, (void **) &fifo
);
100 perror("memory_allocate");
104 printf("FIFO handle 0x%lx gpu addr 0x%08x\n",
105 fifo_handle
, fifo_gaddr
);
109 err
= setup_control(fd
, context_id
, fifo_handle
, fifo_handle
, 0xdeadbabe);
111 perror("setup_control");
115 printf("FIFO put 0x%08x get 0x%08x ref 0x%08x\n",
116 control
[0x10], control
[0x11], control
[0x12]);
118 /* Allocate FIFO for resetting GPU state */
120 err
= memory_allocate(fd
, context_id
, PS3GPU_CTL_MEMORY_TYPE_GART
,
121 4 * 1024, 12, &reset_gpu_handle
, &reset_gpu_gaddr
, (void **) &reset_gpu
);
123 perror("memory_allocate");
127 printf("reset GPU state handle 0x%lx gpu addr 0x%08x\n",
128 reset_gpu_handle
, reset_gpu_gaddr
);
130 memcpy(reset_gpu
, reset_gpu_state
, reset_gpu_state_size
);
134 fifo
[0] = PS3GPU_MTH_HDR(0, 0, reset_gpu_gaddr
| PS3GPU_MTH_ADDR_CALL
);
135 fifo
[1] = PS3GPU_MTH_HDR(1, 0, PS3GPU_MTH_ADDR_REF
);
136 fifo
[2] = 0xcafef00d;
138 control
[0x10] = fifo_gaddr
+ 3 * sizeof(uint32_t);
140 err
= wait_fifo_idle(control
);
142 fprintf(stderr
, "FIFO timeout: put 0x%08x get 0x%08x ref 0x%08x\n",
143 control
[0x10], control
[0x11], control
[0x12]);
144 dump_fifo(stderr
, fifo
, 0x400);
148 printf("FIFO put 0x%08x get 0x%08x ref 0x%08x\n",
149 control
[0x10], control
[0x11], control
[0x12]);
153 err
= memory_allocate(fd
, context_id
, PS3GPU_CTL_MEMORY_TYPE_VIDEO
,
154 ROUNDUP(DISPLAY_HEIGHT
* DISPLAY_PITCH
, 4 * 1024), 12,
155 &vram_handle
, &vram_gaddr
, (void **) &vram
);
157 perror("memory_allocate");
161 printf("VRAM handle 0x%lx gpu addr 0x%08x\n",
162 vram_handle
, vram_gaddr
);
164 memset32(vram
, 0xff404040, DISPLAY_HEIGHT
* DISPLAY_WIDTH
);
168 err
= flip(fd
, context_id
, PS3GPU_CTL_HEAD_A
, vram_handle
);
174 err
= flip(fd
, context_id
, PS3GPU_CTL_HEAD_B
, vram_handle
);
184 err
= memory_allocate(fd
, context_id
, PS3GPU_CTL_MEMORY_TYPE_GART
,
185 ROUNDUP(DISPLAY_HEIGHT
* DISPLAY_PITCH
, 4 * 1024), 12,
186 &gart_handle
, &gart_gaddr
, (void **) &gart
);
188 perror("memory_allocate");
192 printf("GART handle 0x%lx gpu addr 0x%08x\n",
193 gart_handle
, gart_gaddr
);
195 memset32(gart
, 0xff0000ff, DISPLAY_HEIGHT
* DISPLAY_WIDTH
);
197 /* Blit GART buffer to VRAM with RSX DMA */
199 err
= setup_control(fd
, context_id
, fifo_handle
, fifo_handle
, 0xdeadbabe);
201 perror("setup_control");
205 err
= transfer_data(fifo
, 0xfeed0001, 0xfeed0000,
206 vram_gaddr
, DISPLAY_PITCH
, gart_gaddr
, DISPLAY_PITCH
,
207 DISPLAY_PITCH
, DISPLAY_HEIGHT
);
209 control
[0x10] = fifo_gaddr
+ err
* sizeof(uint32_t);
211 err
= wait_fifo_idle(control
);
213 fprintf(stderr
, "FIFO timeout: put 0x%08x get 0x%08x ref 0x%08x\n",
214 control
[0x10], control
[0x11], control
[0x12]);
215 dump_fifo(stderr
, fifo
, 0x400);
219 printf("FIFO put 0x%08x get 0x%08x ref 0x%08x\n",
220 control
[0x10], control
[0x11], control
[0x12]);
222 save_image("image.argb", (const char *) vram
, DISPLAY_PITCH
* DISPLAY_HEIGHT
);
224 /* Destroy GPU context */
226 context_free
.context_id
= context_id
;
228 err
= ioctl(fd
, PS3GPU_CTL_CONTEXT_FREE
, &context_free
);
239 /* Restore console */
241 ioctl(0, SW_TEXT_80x25
, NULL
);