vertex_buffer.c

   1 /*-
   2  * Copyright (C) 2011, 2012 glevand <geoffrey.levand@mail.ru>
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer,
  10  *    without modification, immediately at the beginning of the file.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  *
  15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  16  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  17  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  18  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  19  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  20  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  21  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  22  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  23  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  24  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  25  *
  26  * $FreeBSD$
  27  */
  28
  29 #include <stdio.h>
  30 #include <stdlib.h>
  31 #include <stdint.h>
  32 #include <stddef.h>
  33 #include <string.h>
  34
  35 #include <sys/types.h>
  36 #include <sys/stat.h>
  37 #include <sys/uio.h>
  38 #include <sys/ioctl.h>
  39 #include <sys/mman.h>
  40 #include <sys/fbio.h>
  41 #include <sys/consio.h>
  42 #include <fcntl.h>
  43 #include <unistd.h>
  44
  45 #include "ps3gpu_ctl.h"
  46 #include "ps3gpu_mth.h"
  47 #include "reset_gpu_state.h"
  48 #include "util.h"
  49
  50 struct vertex {
  51         float x, y, z;
  52         uint32_t rgba;
  53 };
  54
  55 int
  56 main(int argc, char **argv)
  57 {
  58         struct ps3gpu_ctl_context_allocate context_allocate;
  59         struct ps3gpu_ctl_context_free context_free;
  60         int context_id;
  61         volatile uint32_t *control;
  62         volatile uint8_t *driver_info;
  63         uint32_t *fifo, *reset_gpu, *db[2], *zb, *fp, *verts;
  64         unsigned long fifo_handle, reset_gpu_handle, db_handle[2], zb_handle, fp_handle, verts_handle;
  65         unsigned int fifo_gaddr, reset_gpu_gaddr, db_gaddr[2], zb_gaddr, fp_gaddr, verts_gaddr;
  66         int fd = -1;
  67         int i, err;
  68
  69         /* Open GPU device */
  70
  71         fd = open(PS3GPU_DEV_PATH, O_RDWR);
  72         if (fd < 0) {
  73                 perror("open");
  74                 goto done;
  75         }
  76
  77         /* Create GPU context */
  78
  79         context_allocate.vram_size = 64; /* MB */
  80
  81         err = ioctl(fd, PS3GPU_CTL_CONTEXT_ALLOCATE, &context_allocate);
  82         if (err < 0) {
  83                 perror("ioctl");
  84                 goto done;
  85         }
  86
  87         context_id = context_allocate.context_id;
  88
  89         printf("context id %d\n", context_id);
  90         printf("control handle 0x%lx size %d\n",
  91             context_allocate.control_handle, context_allocate.control_size);
  92         printf("driver_info handle 0x%lx size %d\n",
  93             context_allocate.driver_info_handle, context_allocate.driver_info_size);
  94
  95         /* Map control registers */
  96
  97         control = mmap(NULL, context_allocate.control_size,
  98             PROT_READ | PROT_WRITE, MAP_SHARED, fd, context_allocate.control_handle);
  99         if (control == (void *) MAP_FAILED) {
 100                 perror("mmap");
 101                 goto done;
 102         }
 103
 104         /* Map driver info */
 105
 106         driver_info = mmap(NULL, context_allocate.driver_info_size,
 107             PROT_READ | PROT_WRITE, MAP_SHARED, fd, context_allocate.driver_info_handle);
 108         if (driver_info == (void *) MAP_FAILED) {
 109                 perror("mmap");
 110                 goto done;
 111         }
 112
 113         printf("channel id %d\n", get_channel_id(driver_info));
 114
 115         /* Allocate FIFO */
 116
 117         err = memory_allocate(fd, context_id, PS3GPU_CTL_MEMORY_TYPE_GART,
 118             64 * 1024, 12, &fifo_handle, &fifo_gaddr, (void **) &fifo);
 119         if (err < 0) {
 120                 perror("memory_allocate");
 121                 goto done;
 122         }
 123
 124         printf("FIFO handle 0x%lx gpu addr 0x%08x\n",
 125             fifo_handle, fifo_gaddr);
 126
 127         /* Setup FIFO */
 128
 129         err = setup_control(fd, context_id, fifo_handle, fifo_handle, 0xdeadbabe);
 130         if (err < 0) {
 131                 perror("setup_control");
 132                 goto done;
 133         }
 134
 135         printf("FIFO put 0x%08x get 0x%08x ref 0x%08x\n",
 136             control[0x10], control[0x11], control[0x12]);
 137
 138         /* Allocate FIFO for resetting GPU state */
 139
 140         err = memory_allocate(fd, context_id, PS3GPU_CTL_MEMORY_TYPE_GART,
 141             4 * 1024, 12, &reset_gpu_handle, &reset_gpu_gaddr, (void **) &reset_gpu);
 142         if (err < 0) {
 143                 perror("memory_allocate");
 144                 goto done;
 145         }
 146
 147         printf("reset GPU state handle 0x%lx gpu addr 0x%08x\n",
 148             reset_gpu_handle, reset_gpu_gaddr);
 149
 150         memcpy(reset_gpu, reset_gpu_state_3d, reset_gpu_state_3d_size);
 151
 152         /* Kick FIFO */
 153
 154         fifo[0] = PS3GPU_MTH_HDR(0, 0, reset_gpu_gaddr | PS3GPU_MTH_ADDR_CALL);
 155         fifo[1] = PS3GPU_MTH_HDR(1, 0, PS3GPU_MTH_ADDR_REF);
 156         fifo[2] = 0xcafef00d;
 157
 158         control[0x10] = fifo_gaddr + 3 * sizeof(uint32_t);
 159
 160         err = wait_fifo_idle(control);
 161         if (err < 0) {
 162                 fprintf(stderr, "FIFO timeout: put 0x%08x get 0x%08x ref 0x%08x\n",
 163                     control[0x10], control[0x11], control[0x12]);
 164                 dump_fifo(stderr, fifo, 0x400);
 165                 goto done;
 166         }
 167
 168         printf("FIFO put 0x%08x get 0x%08x ref 0x%08x\n",
 169             control[0x10], control[0x11], control[0x12]);
 170
 171         /* Allocate display buffers */
 172
 173         err = memory_allocate(fd, context_id, PS3GPU_CTL_MEMORY_TYPE_VIDEO,
 174             ROUNDUP(DISPLAY_HEIGHT * DISPLAY_PITCH, 4 * 1024), 12,
 175             &db_handle[0], &db_gaddr[0], (void **) &db[0]);
 176         if (err < 0) {
 177                 perror("memory_allocate");
 178                 goto done;
 179         }
 180
 181         printf("DB0 handle 0x%lx gpu addr 0x%08x\n",
 182             db_handle[0], db_gaddr[0]);
 183
 184         err = memory_allocate(fd, context_id, PS3GPU_CTL_MEMORY_TYPE_VIDEO,
 185             ROUNDUP(DISPLAY_HEIGHT * DISPLAY_PITCH, 4 * 1024), 12,
 186             &db_handle[1], &db_gaddr[1], (void **) &db[1]);
 187         if (err < 0) {
 188                 perror("memory_allocate");
 189                 goto done;
 190         }
 191
 192         printf("DB1 handle 0x%lx gpu addr 0x%08x\n",
 193             db_handle[1], db_gaddr[1]);
 194
 195         /* Allocate depth buffer */
 196
 197         err = memory_allocate(fd, context_id, PS3GPU_CTL_MEMORY_TYPE_VIDEO,
 198             ROUNDUP(DISPLAY_HEIGHT * DISPLAY_PITCH, 4 * 1024), 12,
 199             &zb_handle, &zb_gaddr, (void **) &zb);
 200         if (err < 0) {
 201                 perror("memory_allocate");
 202                 goto done;
 203         }
 204
 205         printf("ZB handle 0x%lx gpu addr 0x%08x\n",
 206             zb_handle, zb_gaddr);
 207
 208         /* Allocate fragment program */
 209
 210         err = memory_allocate(fd, context_id, PS3GPU_CTL_MEMORY_TYPE_VIDEO,
 211             4 * 1024, 12, &fp_handle, &fp_gaddr, (void **) &fp);
 212         if (err < 0) {
 213                 perror("memory_allocate");
 214                 goto done;
 215         }
 216
 217         printf("FP handle 0x%lx gpu addr 0x%08x\n",
 218             fp_handle, fp_gaddr);
 219
 220         /* Allocate vertices */
 221
 222         err = memory_allocate(fd, context_id, PS3GPU_CTL_MEMORY_TYPE_VIDEO,
 223             4 * 1024, 12, &verts_handle, &verts_gaddr, (void **) &verts);
 224         if (err < 0) {
 225                 perror("memory_allocate");
 226                 goto done;
 227         }
 228
 229         printf("VERTS handle 0x%lx gpu addr 0x%08x\n",
 230             verts_handle, verts_gaddr);
 231
 232         /* Set display buffers */
 233
 234         err = display_buffer_set(fd, context_id, 0, DISPLAY_WIDTH, DISPLAY_HEIGHT,
 235             DISPLAY_PITCH, db_handle[0]);
 236         if (err < 0) {
 237                 perror("display_buffer_set");
 238                 goto done;
 239         }
 240
 241         err = display_buffer_set(fd, context_id, 1, DISPLAY_WIDTH, DISPLAY_HEIGHT,
 242             DISPLAY_PITCH, db_handle[1]);
 243         if (err < 0) {
 244                 perror("display_buffer_set");
 245                 goto done;
 246         }
 247
 248         const struct surface_desc surf_desc[] = {
 249                 /* display buffer 0 */
 250                 {
 251                         .sd_color_loc = { 0xfeed0000, 0xfeed0000, 0xfeed0000, 0xfeed0000 },
 252                         .sd_color_off = { db_gaddr[0], 0, 0, 0 },
 253                         .sd_color_pitch = { DISPLAY_PITCH, 64, 64, 64 },
 254                         .sd_color_fmt = 0x8,
 255                         .sd_color_target = 0x1,
 256                         .sd_depth_loc = 0xfeed0000,
 257                         .sd_depth_off = zb_gaddr,
 258                         .sd_depth_pitch = DISPLAY_PITCH,
 259                         .sd_depth_fmt = 0x2,
 260                         .sd_x = 0,
 261                         .sd_y = 0,
 262                         .sd_w = DISPLAY_WIDTH,
 263                         .sd_h = DISPLAY_HEIGHT,
 264                 },
 265                 /* display buffer 1 */
 266                 {
 267                         .sd_color_loc = { 0xfeed0000, 0xfeed0000, 0xfeed0000, 0xfeed0000 },
 268                         .sd_color_off = { db_gaddr[1], 0, 0, 0 },
 269                         .sd_color_pitch = { DISPLAY_PITCH, 64, 64, 64 },
 270                         .sd_color_fmt = 0x8,
 271                         .sd_color_target = 0x1,
 272                         .sd_depth_loc = 0xfeed0000,
 273                         .sd_depth_off = zb_gaddr,
 274                         .sd_depth_pitch = DISPLAY_PITCH,
 275                         .sd_depth_fmt = 0x2,
 276                         .sd_x = 0,
 277                         .sd_y = 0,
 278                         .sd_w = DISPLAY_WIDTH,
 279                         .sd_h = DISPLAY_HEIGHT,
 280                 },
 281         };
 282
 283         const uint32_t clear_color[] = {
 284                 0xff404040,
 285                 0xffffffff,
 286         };
 287
 288         const float vp_offset[] = { DISPLAY_WIDTH * 0.5f, DISPLAY_HEIGHT * 0.5f, 0.5f, 0.0f };
 289         const float vp_scale[] = { DISPLAY_WIDTH * 0.5f, DISPLAY_HEIGHT * 0.5f, 0.5f, 0.0f };
 290
 291         const uint32_t vertex_prg[] = {
 292                 /* MOV o[0], v[0] */
 293                 0x401f9c6c, 0x0040000d, 0x8106c083, 0x6041ff80,
 294                 /* MOV o[1], v[3] */
 295                 0x401f9c6c, 0x0040030d, 0x8106c083, 0x6041ff85,
 296         };
 297
 298         uint32_t frag_prg[] = {
 299                 /* MOVR R0, f[1] */
 300                 0x3e010100, 0xc8011c9d, 0xc8000001, 0xc8003fe1,
 301         };
 302
 303         /*
 304          *            (0.0, -0.5)
 305          *                 /\
 306          *                /  \
 307          *               /    \
 308          *              /      \
 309          * (-0.5, 0.5) /________\ (0.5, 0.5)
 310          *
 311          */
 312
 313         const struct vertex triangle_verts[] = {
 314                 {  0.0f, -0.5f, -1.0f, 0xff0000ff },
 315                 { -0.5f,  0.5f, -1.0f, 0x00ff00ff },
 316                 {  0.5f,  0.5f, -1.0f, 0x0000ffff },
 317         };
 318
 319         err = setup_control(fd, context_id, fifo_handle, fifo_handle, 0xdeadbabe);
 320         if (err < 0) {
 321                 perror("setup_control");
 322                 goto done;
 323         }
 324
 325         printf("FIFO put 0x%08x get 0x%08x ref 0x%08x\n",
 326             control[0x10], control[0x11], control[0x12]);
 327
 328         /* Transfer fragment program to VRAM */
 329
 330         err += transfer_inline(fifo + err, 0xfeed0000, fp_gaddr,
 331             frag_prg, ARRAY_SIZE(frag_prg));
 332
 333         /* Transfer vertices to VRAM */
 334
 335         err += transfer_inline(fifo + err, 0xfeed0000, verts_gaddr,
 336             (uint32_t *) triangle_verts, sizeof(triangle_verts) / sizeof(uint32_t));
 337
 338         control[0x10] = fifo_gaddr + err * sizeof(uint32_t);
 339
 340         err = wait_fifo_idle(control);
 341         if (err < 0) {
 342                 fprintf(stderr, "FIFO timeout: put 0x%08x get 0x%08x ref 0x%08x\n",
 343                     control[0x10], control[0x11], control[0x12]);
 344                 dump_fifo(stderr, fifo, 0x400);
 345                 goto done;
 346         }
 347
 348         printf("FIFO put 0x%08x get 0x%08x ref 0x%08x\n",
 349             control[0x10], control[0x11], control[0x12]);
 350
 351         for (i = 0; i < ARRAY_SIZE(surf_desc); i++) {
 352                 err = setup_control(fd, context_id, fifo_handle, fifo_handle, 0xdeadbabe);
 353                 if (err < 0) {
 354                         perror("setup_control");
 355                         goto done;
 356                 }
 357
 358                 printf("FIFO put 0x%08x get 0x%08x ref 0x%08x\n",
 359                     control[0x10], control[0x11], control[0x12]);
 360
 361                 err += set_surface(fifo + err, &surf_desc[i]);
 362                 err += set_depth_mask(fifo + err, 0x00000000);
 363                 err += set_color_mask(fifo + err, 0x01010101);
 364                 err += set_color_mask_mrt(fifo + err, 0x00000000);
 365                 err += set_clear_color(fifo + err, clear_color[i]);
 366                 err += set_scissor(fifo + err, 0, 0, 4095, 4095);
 367                 err += clear_surface(fifo + err, 0x000000f1);
 368
 369                 err += set_viewport(fifo + err, 0, 0, DISPLAY_WIDTH, DISPLAY_HEIGHT,
 370                     0.0f, 1.0f, vp_offset, vp_scale);
 371
 372                 /* Set vertex shader */
 373
 374                 err += load_vertex_prg(fifo + err, 0, vertex_prg, ARRAY_SIZE(vertex_prg) / 4);
 375                 err += set_vertex_prg_start_slot(fifo + err, 0);
 376                 err += set_vertex_prg_reg_count(fifo + err, 1);
 377                 err += set_vertex_attr_inmask(fifo + err, (1 << 3) | (1 << 0));
 378                 err += set_vertex_attr_outmask(fifo + err, (1 << 2) | (1 << 0));
 379
 380                 /* Set fragment shader */
 381
 382                 err += set_frag_prg(fifo + err, 0x1, fp_gaddr);
 383                 err += frag_prg_ctrl(fifo + err, 2, 0, 0, 0, 0);
 384
 385                 err += set_front_poly_mode(fifo + err, 0x1b02);
 386                 err += set_shade_mode(fifo + err, 0x1d01);
 387
 388                 /* register 0 - position */
 389                 err += set_vertex_data_arr(fifo + err, 0, 0, sizeof(struct vertex),
 390                     3, 2, 0x0, verts_gaddr + offsetof(struct vertex, x));
 391                 /* register 3 - color */
 392                 err += set_vertex_data_arr(fifo + err, 3, 0, sizeof(struct vertex),
 393                     4, 4, 0x0, verts_gaddr + offsetof(struct vertex, rgba));
 394
 395                 err += draw_arrays(fifo + err, 0x5, 0, ARRAY_SIZE(triangle_verts));
 396
 397                 err += flip_display_buffer(fifo + err, get_channel_id(driver_info), i, 0);
 398
 399                 /*
 400                  * Label with index 0 (head 0) is set by LV1 to 0x00000000 when flip is complete.
 401                  * Let GPU wait for it.
 402                  */
 403
 404                 err += wait_label(fifo + err, 0, 0x00000000);
 405
 406                 control[0x10] = fifo_gaddr + err * sizeof(uint32_t);
 407
 408                 err = wait_fifo_idle(control);
 409                 if (err < 0) {
 410                         fprintf(stderr, "FIFO timeout: put 0x%08x get 0x%08x ref 0x%08x\n",
 411                             control[0x10], control[0x11], control[0x12]);
 412                         dump_fifo(stderr, fifo, 0x400);
 413                         goto done;
 414                 }
 415
 416                 printf("FIFO put 0x%08x get 0x%08x ref 0x%08x\n",
 417                     control[0x10], control[0x11], control[0x12]);
 418
 419                 usleep(1000000);
 420         }
 421
 422         save_image("image.argb", (const char *) db[0], DISPLAY_PITCH * DISPLAY_HEIGHT);
 423
 424         /* Destroy GPU context */
 425
 426         context_free.context_id = context_id;
 427
 428         err = ioctl(fd, PS3GPU_CTL_CONTEXT_FREE, &context_free);
 429         if (err < 0) {
 430                 perror("ioctl");
 431                 goto done;
 432         }
 433
 434 done:
 435
 436         if (fd >= 0)
 437                 close(fd);
 438
 439         /* Restore console */
 440
 441         ioctl(0, SW_TEXT_80x25, NULL);
 442
 443         exit(0);
 444 }