bluetooth: hci_core: defer hci_unregister_sysfs()
[pv_ops_mirror.git] / arch / x86 / kernel / cpu / cpufreq / speedstep-lib.c
blob98d4fdb7dc046b73cfc00402be21da9a9d303686
1 /*
2 * (C) 2002 - 2003 Dominik Brodowski <linux@brodo.de>
4 * Licensed under the terms of the GNU GPL License version 2.
6 * Library for common functions for Intel SpeedStep v.1 and v.2 support
8 * BIG FAT DISCLAIMER: Work in progress code. Possibly *dangerous*
9 */
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/moduleparam.h>
14 #include <linux/init.h>
15 #include <linux/cpufreq.h>
16 #include <linux/slab.h>
18 #include <asm/msr.h>
19 #include "speedstep-lib.h"
21 #define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, "speedstep-lib", msg)
23 #ifdef CONFIG_X86_SPEEDSTEP_RELAXED_CAP_CHECK
24 static int relaxed_check = 0;
25 #else
26 #define relaxed_check 0
27 #endif
29 /*********************************************************************
30 * GET PROCESSOR CORE SPEED IN KHZ *
31 *********************************************************************/
33 static unsigned int pentium3_get_frequency (unsigned int processor)
35 /* See table 14 of p3_ds.pdf and table 22 of 29834003.pdf */
36 struct {
37 unsigned int ratio; /* Frequency Multiplier (x10) */
38 u8 bitmap; /* power on configuration bits
39 [27, 25:22] (in MSR 0x2a) */
40 } msr_decode_mult [] = {
41 { 30, 0x01 },
42 { 35, 0x05 },
43 { 40, 0x02 },
44 { 45, 0x06 },
45 { 50, 0x00 },
46 { 55, 0x04 },
47 { 60, 0x0b },
48 { 65, 0x0f },
49 { 70, 0x09 },
50 { 75, 0x0d },
51 { 80, 0x0a },
52 { 85, 0x26 },
53 { 90, 0x20 },
54 { 100, 0x2b },
55 { 0, 0xff } /* error or unknown value */
58 /* PIII(-M) FSB settings: see table b1-b of 24547206.pdf */
59 struct {
60 unsigned int value; /* Front Side Bus speed in MHz */
61 u8 bitmap; /* power on configuration bits [18: 19]
62 (in MSR 0x2a) */
63 } msr_decode_fsb [] = {
64 { 66, 0x0 },
65 { 100, 0x2 },
66 { 133, 0x1 },
67 { 0, 0xff}
70 u32 msr_lo, msr_tmp;
71 int i = 0, j = 0;
73 /* read MSR 0x2a - we only need the low 32 bits */
74 rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_tmp);
75 dprintk("P3 - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n", msr_lo, msr_tmp);
76 msr_tmp = msr_lo;
78 /* decode the FSB */
79 msr_tmp &= 0x00c0000;
80 msr_tmp >>= 18;
81 while (msr_tmp != msr_decode_fsb[i].bitmap) {
82 if (msr_decode_fsb[i].bitmap == 0xff)
83 return 0;
84 i++;
87 /* decode the multiplier */
88 if (processor == SPEEDSTEP_PROCESSOR_PIII_C_EARLY) {
89 dprintk("workaround for early PIIIs\n");
90 msr_lo &= 0x03c00000;
91 } else
92 msr_lo &= 0x0bc00000;
93 msr_lo >>= 22;
94 while (msr_lo != msr_decode_mult[j].bitmap) {
95 if (msr_decode_mult[j].bitmap == 0xff)
96 return 0;
97 j++;
100 dprintk("speed is %u\n", (msr_decode_mult[j].ratio * msr_decode_fsb[i].value * 100));
102 return (msr_decode_mult[j].ratio * msr_decode_fsb[i].value * 100);
106 static unsigned int pentiumM_get_frequency(void)
108 u32 msr_lo, msr_tmp;
110 rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_tmp);
111 dprintk("PM - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n", msr_lo, msr_tmp);
113 /* see table B-2 of 24547212.pdf */
114 if (msr_lo & 0x00040000) {
115 printk(KERN_DEBUG "speedstep-lib: PM - invalid FSB: 0x%x 0x%x\n", msr_lo, msr_tmp);
116 return 0;
119 msr_tmp = (msr_lo >> 22) & 0x1f;
120 dprintk("bits 22-26 are 0x%x, speed is %u\n", msr_tmp, (msr_tmp * 100 * 1000));
122 return (msr_tmp * 100 * 1000);
125 static unsigned int pentium_core_get_frequency(void)
127 u32 fsb = 0;
128 u32 msr_lo, msr_tmp;
130 rdmsr(MSR_FSB_FREQ, msr_lo, msr_tmp);
131 /* see table B-2 of 25366920.pdf */
132 switch (msr_lo & 0x07) {
133 case 5:
134 fsb = 100000;
135 break;
136 case 1:
137 fsb = 133333;
138 break;
139 case 3:
140 fsb = 166667;
141 break;
142 default:
143 printk(KERN_ERR "PCORE - MSR_FSB_FREQ undefined value");
146 rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_tmp);
147 dprintk("PCORE - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n", msr_lo, msr_tmp);
149 msr_tmp = (msr_lo >> 22) & 0x1f;
150 dprintk("bits 22-26 are 0x%x, speed is %u\n", msr_tmp, (msr_tmp * fsb));
152 return (msr_tmp * fsb);
156 static unsigned int pentium4_get_frequency(void)
158 struct cpuinfo_x86 *c = &boot_cpu_data;
159 u32 msr_lo, msr_hi, mult;
160 unsigned int fsb = 0;
162 rdmsr(0x2c, msr_lo, msr_hi);
164 dprintk("P4 - MSR_EBC_FREQUENCY_ID: 0x%x 0x%x\n", msr_lo, msr_hi);
166 /* decode the FSB: see IA-32 Intel (C) Architecture Software
167 * Developer's Manual, Volume 3: System Prgramming Guide,
168 * revision #12 in Table B-1: MSRs in the Pentium 4 and
169 * Intel Xeon Processors, on page B-4 and B-5.
171 if (c->x86_model < 2)
172 fsb = 100 * 1000;
173 else {
174 u8 fsb_code = (msr_lo >> 16) & 0x7;
175 switch (fsb_code) {
176 case 0:
177 fsb = 100 * 1000;
178 break;
179 case 1:
180 fsb = 13333 * 10;
181 break;
182 case 2:
183 fsb = 200 * 1000;
184 break;
188 if (!fsb)
189 printk(KERN_DEBUG "speedstep-lib: couldn't detect FSB speed. Please send an e-mail to <linux@brodo.de>\n");
191 /* Multiplier. */
192 mult = msr_lo >> 24;
194 dprintk("P4 - FSB %u kHz; Multiplier %u; Speed %u kHz\n", fsb, mult, (fsb * mult));
196 return (fsb * mult);
200 unsigned int speedstep_get_processor_frequency(unsigned int processor)
202 switch (processor) {
203 case SPEEDSTEP_PROCESSOR_PCORE:
204 return pentium_core_get_frequency();
205 case SPEEDSTEP_PROCESSOR_PM:
206 return pentiumM_get_frequency();
207 case SPEEDSTEP_PROCESSOR_P4D:
208 case SPEEDSTEP_PROCESSOR_P4M:
209 return pentium4_get_frequency();
210 case SPEEDSTEP_PROCESSOR_PIII_T:
211 case SPEEDSTEP_PROCESSOR_PIII_C:
212 case SPEEDSTEP_PROCESSOR_PIII_C_EARLY:
213 return pentium3_get_frequency(processor);
214 default:
215 return 0;
217 return 0;
219 EXPORT_SYMBOL_GPL(speedstep_get_processor_frequency);
222 /*********************************************************************
223 * DETECT SPEEDSTEP-CAPABLE PROCESSOR *
224 *********************************************************************/
226 unsigned int speedstep_detect_processor (void)
228 struct cpuinfo_x86 *c = &cpu_data(0);
229 u32 ebx, msr_lo, msr_hi;
231 dprintk("x86: %x, model: %x\n", c->x86, c->x86_model);
233 if ((c->x86_vendor != X86_VENDOR_INTEL) ||
234 ((c->x86 != 6) && (c->x86 != 0xF)))
235 return 0;
237 if (c->x86 == 0xF) {
238 /* Intel Mobile Pentium 4-M
239 * or Intel Mobile Pentium 4 with 533 MHz FSB */
240 if (c->x86_model != 2)
241 return 0;
243 ebx = cpuid_ebx(0x00000001);
244 ebx &= 0x000000FF;
246 dprintk("ebx value is %x, x86_mask is %x\n", ebx, c->x86_mask);
248 switch (c->x86_mask) {
249 case 4:
251 * B-stepping [M-P4-M]
252 * sample has ebx = 0x0f, production has 0x0e.
254 if ((ebx == 0x0e) || (ebx == 0x0f))
255 return SPEEDSTEP_PROCESSOR_P4M;
256 break;
257 case 7:
259 * C-stepping [M-P4-M]
260 * needs to have ebx=0x0e, else it's a celeron:
261 * cf. 25130917.pdf / page 7, footnote 5 even
262 * though 25072120.pdf / page 7 doesn't say
263 * samples are only of B-stepping...
265 if (ebx == 0x0e)
266 return SPEEDSTEP_PROCESSOR_P4M;
267 break;
268 case 9:
270 * D-stepping [M-P4-M or M-P4/533]
272 * this is totally strange: CPUID 0x0F29 is
273 * used by M-P4-M, M-P4/533 and(!) Celeron CPUs.
274 * The latter need to be sorted out as they don't
275 * support speedstep.
276 * Celerons with CPUID 0x0F29 may have either
277 * ebx=0x8 or 0xf -- 25130917.pdf doesn't say anything
278 * specific.
279 * M-P4-Ms may have either ebx=0xe or 0xf [see above]
280 * M-P4/533 have either ebx=0xe or 0xf. [25317607.pdf]
281 * also, M-P4M HTs have ebx=0x8, too
282 * For now, they are distinguished by the model_id string
284 if ((ebx == 0x0e) || (strstr(c->x86_model_id,"Mobile Intel(R) Pentium(R) 4") != NULL))
285 return SPEEDSTEP_PROCESSOR_P4M;
286 break;
287 default:
288 break;
290 return 0;
293 switch (c->x86_model) {
294 case 0x0B: /* Intel PIII [Tualatin] */
295 /* cpuid_ebx(1) is 0x04 for desktop PIII, 0x06 for mobile PIII-M */
296 ebx = cpuid_ebx(0x00000001);
297 dprintk("ebx is %x\n", ebx);
299 ebx &= 0x000000FF;
301 if (ebx != 0x06)
302 return 0;
304 /* So far all PIII-M processors support SpeedStep. See
305 * Intel's 24540640.pdf of June 2003
307 return SPEEDSTEP_PROCESSOR_PIII_T;
309 case 0x08: /* Intel PIII [Coppermine] */
311 /* all mobile PIII Coppermines have FSB 100 MHz
312 * ==> sort out a few desktop PIIIs. */
313 rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_hi);
314 dprintk("Coppermine: MSR_IA32_EBL_CR_POWERON is 0x%x, 0x%x\n", msr_lo, msr_hi);
315 msr_lo &= 0x00c0000;
316 if (msr_lo != 0x0080000)
317 return 0;
320 * If the processor is a mobile version,
321 * platform ID has bit 50 set
322 * it has SpeedStep technology if either
323 * bit 56 or 57 is set
325 rdmsr(MSR_IA32_PLATFORM_ID, msr_lo, msr_hi);
326 dprintk("Coppermine: MSR_IA32_PLATFORM ID is 0x%x, 0x%x\n", msr_lo, msr_hi);
327 if ((msr_hi & (1<<18)) && (relaxed_check ? 1 : (msr_hi & (3<<24)))) {
328 if (c->x86_mask == 0x01) {
329 dprintk("early PIII version\n");
330 return SPEEDSTEP_PROCESSOR_PIII_C_EARLY;
331 } else
332 return SPEEDSTEP_PROCESSOR_PIII_C;
335 default:
336 return 0;
339 EXPORT_SYMBOL_GPL(speedstep_detect_processor);
342 /*********************************************************************
343 * DETECT SPEEDSTEP SPEEDS *
344 *********************************************************************/
346 unsigned int speedstep_get_freqs(unsigned int processor,
347 unsigned int *low_speed,
348 unsigned int *high_speed,
349 unsigned int *transition_latency,
350 void (*set_state) (unsigned int state))
352 unsigned int prev_speed;
353 unsigned int ret = 0;
354 unsigned long flags;
355 struct timeval tv1, tv2;
357 if ((!processor) || (!low_speed) || (!high_speed) || (!set_state))
358 return -EINVAL;
360 dprintk("trying to determine both speeds\n");
362 /* get current speed */
363 prev_speed = speedstep_get_processor_frequency(processor);
364 if (!prev_speed)
365 return -EIO;
367 dprintk("previous speed is %u\n", prev_speed);
369 local_irq_save(flags);
371 /* switch to low state */
372 set_state(SPEEDSTEP_LOW);
373 *low_speed = speedstep_get_processor_frequency(processor);
374 if (!*low_speed) {
375 ret = -EIO;
376 goto out;
379 dprintk("low speed is %u\n", *low_speed);
381 /* start latency measurement */
382 if (transition_latency)
383 do_gettimeofday(&tv1);
385 /* switch to high state */
386 set_state(SPEEDSTEP_HIGH);
388 /* end latency measurement */
389 if (transition_latency)
390 do_gettimeofday(&tv2);
392 *high_speed = speedstep_get_processor_frequency(processor);
393 if (!*high_speed) {
394 ret = -EIO;
395 goto out;
398 dprintk("high speed is %u\n", *high_speed);
400 if (*low_speed == *high_speed) {
401 ret = -ENODEV;
402 goto out;
405 /* switch to previous state, if necessary */
406 if (*high_speed != prev_speed)
407 set_state(SPEEDSTEP_LOW);
409 if (transition_latency) {
410 *transition_latency = (tv2.tv_sec - tv1.tv_sec) * USEC_PER_SEC +
411 tv2.tv_usec - tv1.tv_usec;
412 dprintk("transition latency is %u uSec\n", *transition_latency);
414 /* convert uSec to nSec and add 20% for safety reasons */
415 *transition_latency *= 1200;
417 /* check if the latency measurement is too high or too low
418 * and set it to a safe value (500uSec) in that case
420 if (*transition_latency > 10000000 || *transition_latency < 50000) {
421 printk (KERN_WARNING "speedstep: frequency transition measured seems out of "
422 "range (%u nSec), falling back to a safe one of %u nSec.\n",
423 *transition_latency, 500000);
424 *transition_latency = 500000;
428 out:
429 local_irq_restore(flags);
430 return (ret);
432 EXPORT_SYMBOL_GPL(speedstep_get_freqs);
434 #ifdef CONFIG_X86_SPEEDSTEP_RELAXED_CAP_CHECK
435 module_param(relaxed_check, int, 0444);
436 MODULE_PARM_DESC(relaxed_check, "Don't do all checks for speedstep capability.");
437 #endif
439 MODULE_AUTHOR ("Dominik Brodowski <linux@brodo.de>");
440 MODULE_DESCRIPTION ("Library for Intel SpeedStep 1 or 2 cpufreq drivers.");
441 MODULE_LICENSE ("GPL");