include/asm-sparc64/spitfire.h

   1 /* spitfire.h: SpitFire/BlackBird/Cheetah inline MMU operations.
   2  *
   3  * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
   4  */
   5
   6 #ifndef _SPARC64_SPITFIRE_H
   7 #define _SPARC64_SPITFIRE_H
   8
   9 #include <asm/asi.h>
  10
  11 /* The following register addresses are accessible via ASI_DMMU
  12  * and ASI_IMMU, that is there is a distinct and unique copy of
  13  * each these registers for each TLB.
  14  */
  15 #define TSB_TAG_TARGET          0x0000000000000000 /* All chips                         */
  16 #define TLB_SFSR                0x0000000000000018 /* All chips                         */
  17 #define TSB_REG                 0x0000000000000028 /* All chips                         */
  18 #define TLB_TAG_ACCESS          0x0000000000000030 /* All chips                         */
  19 #define VIRT_WATCHPOINT         0x0000000000000038 /* All chips                         */
  20 #define PHYS_WATCHPOINT         0x0000000000000040 /* All chips                         */
  21 #define TSB_EXTENSION_P         0x0000000000000048 /* Ultra-III and later               */
  22 #define TSB_EXTENSION_S         0x0000000000000050 /* Ultra-III and later, D-TLB only   */
  23 #define TSB_EXTENSION_N         0x0000000000000058 /* Ultra-III and later               */
  24 #define TLB_TAG_ACCESS_EXT      0x0000000000000060 /* Ultra-III+ and later              */
  25
  26 /* These registers only exist as one entity, and are accessed
  27  * via ASI_DMMU only.
  28  */
  29 #define PRIMARY_CONTEXT         0x0000000000000008
  30 #define SECONDARY_CONTEXT       0x0000000000000010
  31 #define DMMU_SFAR               0x0000000000000020
  32 #define VIRT_WATCHPOINT         0x0000000000000038
  33 #define PHYS_WATCHPOINT         0x0000000000000040
  34
  35 #define SPITFIRE_HIGHEST_LOCKED_TLBENT  (64 - 1)
  36 #define CHEETAH_HIGHEST_LOCKED_TLBENT   (16 - 1)
  37
  38 #define L1DCACHE_SIZE           0x4000
  39
  40 #define SUN4V_CHIP_INVALID      0x00
  41 #define SUN4V_CHIP_NIAGARA1     0x01
  42 #define SUN4V_CHIP_NIAGARA2     0x02
  43 #define SUN4V_CHIP_UNKNOWN      0xff
  44
  45 #ifndef __ASSEMBLY__
  46
  47 enum ultra_tlb_layout {
  48         spitfire = 0,
  49         cheetah = 1,
  50         cheetah_plus = 2,
  51         hypervisor = 3,
  52 };
  53
  54 extern enum ultra_tlb_layout tlb_type;
  55
  56 extern int sun4v_chip_type;
  57
  58 extern int cheetah_pcache_forced_on;
  59 extern void cheetah_enable_pcache(void);
  60
  61 #define sparc64_highest_locked_tlbent() \
  62         (tlb_type == spitfire ? \
  63          SPITFIRE_HIGHEST_LOCKED_TLBENT : \
  64          CHEETAH_HIGHEST_LOCKED_TLBENT)
  65
  66 /* The data cache is write through, so this just invalidates the
  67  * specified line.
  68  */
  69 static inline void spitfire_put_dcache_tag(unsigned long addr, unsigned long tag)
  70 {
  71         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
  72                              "membar    #Sync"
  73                              : /* No outputs */
  74                              : "r" (tag), "r" (addr), "i" (ASI_DCACHE_TAG));
  75 }
  76
  77 /* The instruction cache lines are flushed with this, but note that
  78  * this does not flush the pipeline.  It is possible for a line to
  79  * get flushed but stale instructions to still be in the pipeline,
  80  * a flush instruction (to any address) is sufficient to handle
  81  * this issue after the line is invalidated.
  82  */
  83 static inline void spitfire_put_icache_tag(unsigned long addr, unsigned long tag)
  84 {
  85         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
  86                              "membar    #Sync"
  87                              : /* No outputs */
  88                              : "r" (tag), "r" (addr), "i" (ASI_IC_TAG));
  89 }
  90
  91 static inline unsigned long spitfire_get_dtlb_data(int entry)
  92 {
  93         unsigned long data;
  94
  95         __asm__ __volatile__("ldxa      [%1] %2, %0"
  96                              : "=r" (data)
  97                              : "r" (entry << 3), "i" (ASI_DTLB_DATA_ACCESS));
  98
  99         /* Clear TTE diag bits. */
 100         data &= ~0x0003fe0000000000UL;
 101
 102         return data;
 103 }
 104
 105 static inline unsigned long spitfire_get_dtlb_tag(int entry)
 106 {
 107         unsigned long tag;
 108
 109         __asm__ __volatile__("ldxa      [%1] %2, %0"
 110                              : "=r" (tag)
 111                              : "r" (entry << 3), "i" (ASI_DTLB_TAG_READ));
 112         return tag;
 113 }
 114
 115 static inline void spitfire_put_dtlb_data(int entry, unsigned long data)
 116 {
 117         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
 118                              "membar    #Sync"
 119                              : /* No outputs */
 120                              : "r" (data), "r" (entry << 3),
 121                                "i" (ASI_DTLB_DATA_ACCESS));
 122 }
 123
 124 static inline unsigned long spitfire_get_itlb_data(int entry)
 125 {
 126         unsigned long data;
 127
 128         __asm__ __volatile__("ldxa      [%1] %2, %0"
 129                              : "=r" (data)
 130                              : "r" (entry << 3), "i" (ASI_ITLB_DATA_ACCESS));
 131
 132         /* Clear TTE diag bits. */
 133         data &= ~0x0003fe0000000000UL;
 134
 135         return data;
 136 }
 137
 138 static inline unsigned long spitfire_get_itlb_tag(int entry)
 139 {
 140         unsigned long tag;
 141
 142         __asm__ __volatile__("ldxa      [%1] %2, %0"
 143                              : "=r" (tag)
 144                              : "r" (entry << 3), "i" (ASI_ITLB_TAG_READ));
 145         return tag;
 146 }
 147
 148 static inline void spitfire_put_itlb_data(int entry, unsigned long data)
 149 {
 150         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
 151                              "membar    #Sync"
 152                              : /* No outputs */
 153                              : "r" (data), "r" (entry << 3),
 154                                "i" (ASI_ITLB_DATA_ACCESS));
 155 }
 156
 157 static inline void spitfire_flush_dtlb_nucleus_page(unsigned long page)
 158 {
 159         __asm__ __volatile__("stxa      %%g0, [%0] %1\n\t"
 160                              "membar    #Sync"
 161                              : /* No outputs */
 162                              : "r" (page | 0x20), "i" (ASI_DMMU_DEMAP));
 163 }
 164
 165 static inline void spitfire_flush_itlb_nucleus_page(unsigned long page)
 166 {
 167         __asm__ __volatile__("stxa      %%g0, [%0] %1\n\t"
 168                              "membar    #Sync"
 169                              : /* No outputs */
 170                              : "r" (page | 0x20), "i" (ASI_IMMU_DEMAP));
 171 }
 172
 173 /* Cheetah has "all non-locked" tlb flushes. */
 174 static inline void cheetah_flush_dtlb_all(void)
 175 {
 176         __asm__ __volatile__("stxa      %%g0, [%0] %1\n\t"
 177                              "membar    #Sync"
 178                              : /* No outputs */
 179                              : "r" (0x80), "i" (ASI_DMMU_DEMAP));
 180 }
 181
 182 static inline void cheetah_flush_itlb_all(void)
 183 {
 184         __asm__ __volatile__("stxa      %%g0, [%0] %1\n\t"
 185                              "membar    #Sync"
 186                              : /* No outputs */
 187                              : "r" (0x80), "i" (ASI_IMMU_DEMAP));
 188 }
 189
 190 /* Cheetah has a 4-tlb layout so direct access is a bit different.
 191  * The first two TLBs are fully assosciative, hold 16 entries, and are
 192  * used only for locked and >8K sized translations.  One exists for
 193  * data accesses and one for instruction accesses.
 194  *
 195  * The third TLB is for data accesses to 8K non-locked translations, is
 196  * 2 way assosciative, and holds 512 entries.  The fourth TLB is for
 197  * instruction accesses to 8K non-locked translations, is 2 way
 198  * assosciative, and holds 128 entries.
 199  *
 200  * Cheetah has some bug where bogus data can be returned from
 201  * ASI_{D,I}TLB_DATA_ACCESS loads, doing the load twice fixes
 202  * the problem for me. -DaveM
 203  */
 204 static inline unsigned long cheetah_get_ldtlb_data(int entry)
 205 {
 206         unsigned long data;
 207
 208         __asm__ __volatile__("ldxa      [%1] %2, %%g0\n\t"
 209                              "ldxa      [%1] %2, %0"
 210                              : "=r" (data)
 211                              : "r" ((0 << 16) | (entry << 3)),
 212                              "i" (ASI_DTLB_DATA_ACCESS));
 213
 214         return data;
 215 }
 216
 217 static inline unsigned long cheetah_get_litlb_data(int entry)
 218 {
 219         unsigned long data;
 220
 221         __asm__ __volatile__("ldxa      [%1] %2, %%g0\n\t"
 222                              "ldxa      [%1] %2, %0"
 223                              : "=r" (data)
 224                              : "r" ((0 << 16) | (entry << 3)),
 225                              "i" (ASI_ITLB_DATA_ACCESS));
 226
 227         return data;
 228 }
 229
 230 static inline unsigned long cheetah_get_ldtlb_tag(int entry)
 231 {
 232         unsigned long tag;
 233
 234         __asm__ __volatile__("ldxa      [%1] %2, %0"
 235                              : "=r" (tag)
 236                              : "r" ((0 << 16) | (entry << 3)),
 237                              "i" (ASI_DTLB_TAG_READ));
 238
 239         return tag;
 240 }
 241
 242 static inline unsigned long cheetah_get_litlb_tag(int entry)
 243 {
 244         unsigned long tag;
 245
 246         __asm__ __volatile__("ldxa      [%1] %2, %0"
 247                              : "=r" (tag)
 248                              : "r" ((0 << 16) | (entry << 3)),
 249                              "i" (ASI_ITLB_TAG_READ));
 250
 251         return tag;
 252 }
 253
 254 static inline void cheetah_put_ldtlb_data(int entry, unsigned long data)
 255 {
 256         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
 257                              "membar    #Sync"
 258                              : /* No outputs */
 259                              : "r" (data),
 260                                "r" ((0 << 16) | (entry << 3)),
 261                                "i" (ASI_DTLB_DATA_ACCESS));
 262 }
 263
 264 static inline void cheetah_put_litlb_data(int entry, unsigned long data)
 265 {
 266         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
 267                              "membar    #Sync"
 268                              : /* No outputs */
 269                              : "r" (data),
 270                                "r" ((0 << 16) | (entry << 3)),
 271                                "i" (ASI_ITLB_DATA_ACCESS));
 272 }
 273
 274 static inline unsigned long cheetah_get_dtlb_data(int entry, int tlb)
 275 {
 276         unsigned long data;
 277
 278         __asm__ __volatile__("ldxa      [%1] %2, %%g0\n\t"
 279                              "ldxa      [%1] %2, %0"
 280                              : "=r" (data)
 281                              : "r" ((tlb << 16) | (entry << 3)), "i" (ASI_DTLB_DATA_ACCESS));
 282
 283         return data;
 284 }
 285
 286 static inline unsigned long cheetah_get_dtlb_tag(int entry, int tlb)
 287 {
 288         unsigned long tag;
 289
 290         __asm__ __volatile__("ldxa      [%1] %2, %0"
 291                              : "=r" (tag)
 292                              : "r" ((tlb << 16) | (entry << 3)), "i" (ASI_DTLB_TAG_READ));
 293         return tag;
 294 }
 295
 296 static inline void cheetah_put_dtlb_data(int entry, unsigned long data, int tlb)
 297 {
 298         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
 299                              "membar    #Sync"
 300                              : /* No outputs */
 301                              : "r" (data),
 302                                "r" ((tlb << 16) | (entry << 3)),
 303                                "i" (ASI_DTLB_DATA_ACCESS));
 304 }
 305
 306 static inline unsigned long cheetah_get_itlb_data(int entry)
 307 {
 308         unsigned long data;
 309
 310         __asm__ __volatile__("ldxa      [%1] %2, %%g0\n\t"
 311                              "ldxa      [%1] %2, %0"
 312                              : "=r" (data)
 313                              : "r" ((2 << 16) | (entry << 3)),
 314                                "i" (ASI_ITLB_DATA_ACCESS));
 315
 316         return data;
 317 }
 318
 319 static inline unsigned long cheetah_get_itlb_tag(int entry)
 320 {
 321         unsigned long tag;
 322
 323         __asm__ __volatile__("ldxa      [%1] %2, %0"
 324                              : "=r" (tag)
 325                              : "r" ((2 << 16) | (entry << 3)), "i" (ASI_ITLB_TAG_READ));
 326         return tag;
 327 }
 328
 329 static inline void cheetah_put_itlb_data(int entry, unsigned long data)
 330 {
 331         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
 332                              "membar    #Sync"
 333                              : /* No outputs */
 334                              : "r" (data), "r" ((2 << 16) | (entry << 3)),
 335                                "i" (ASI_ITLB_DATA_ACCESS));
 336 }
 337
 338 #endif /* !(__ASSEMBLY__) */
 339
 340 #endif /* !(_SPARC64_SPITFIRE_H) */