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pcmcia: CompactFlash driver for PA Semi Electra boards
[pv_ops_mirror.git] / drivers / char / agp / nvidia-agp.c
blob225ed2a53d45515655073bee3fea84c3a12df3af
1 /*
2 * Nvidia AGPGART routines.
3 * Based upon a 2.4 agpgart diff by the folks from NVIDIA, and hacked up
4 * to work in 2.5 by Dave Jones <davej@codemonkey.org.uk>
5 */
6
7 #include <linux/module.h>
8 #include <linux/pci.h>
9 #include <linux/init.h>
10 #include <linux/agp_backend.h>
11 #include <linux/gfp.h>
12 #include <linux/page-flags.h>
13 #include <linux/mm.h>
14 #include <linux/jiffies.h>
15 #include "agp.h"
16
17 /* NVIDIA registers */
18 #define NVIDIA_0_APSIZE 0x80
19 #define NVIDIA_1_WBC 0xf0
20 #define NVIDIA_2_GARTCTRL 0xd0
21 #define NVIDIA_2_APBASE 0xd8
22 #define NVIDIA_2_APLIMIT 0xdc
23 #define NVIDIA_2_ATTBASE(i) (0xe0 + (i) * 4)
24 #define NVIDIA_3_APBASE 0x50
25 #define NVIDIA_3_APLIMIT 0x54
26
27
28 static struct _nvidia_private {
29 struct pci_dev *dev_1;
30 struct pci_dev *dev_2;
31 struct pci_dev *dev_3;
32 volatile u32 __iomem *aperture;
33 int num_active_entries;
34 off_t pg_offset;
35 u32 wbc_mask;
36 } nvidia_private;
37
38
39 static int nvidia_fetch_size(void)
40 {
41 int i;
42 u8 size_value;
43 struct aper_size_info_8 *values;
44
45 pci_read_config_byte(agp_bridge->dev, NVIDIA_0_APSIZE, &size_value);
46 size_value &= 0x0f;
47 values = A_SIZE_8(agp_bridge->driver->aperture_sizes);
48
49 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
50 if (size_value == values[i].size_value) {
51 agp_bridge->previous_size =
52 agp_bridge->current_size = (void *) (values + i);
53 agp_bridge->aperture_size_idx = i;
54 return values[i].size;
55 }
56 }
57
58 return 0;
59 }
60
61 #define SYSCFG 0xC0010010
62 #define IORR_BASE0 0xC0010016
63 #define IORR_MASK0 0xC0010017
64 #define AMD_K7_NUM_IORR 2
65
66 static int nvidia_init_iorr(u32 base, u32 size)
67 {
68 u32 base_hi, base_lo;
69 u32 mask_hi, mask_lo;
70 u32 sys_hi, sys_lo;
71 u32 iorr_addr, free_iorr_addr;
72
73 /* Find the iorr that is already used for the base */
74 /* If not found, determine the uppermost available iorr */
75 free_iorr_addr = AMD_K7_NUM_IORR;
76 for (iorr_addr = 0; iorr_addr < AMD_K7_NUM_IORR; iorr_addr++) {
77 rdmsr(IORR_BASE0 + 2 * iorr_addr, base_lo, base_hi);
78 rdmsr(IORR_MASK0 + 2 * iorr_addr, mask_lo, mask_hi);
79
80 if ((base_lo & 0xfffff000) == (base & 0xfffff000))
81 break;
82
83 if ((mask_lo & 0x00000800) == 0)
84 free_iorr_addr = iorr_addr;
85 }
86
87 if (iorr_addr >= AMD_K7_NUM_IORR) {
88 iorr_addr = free_iorr_addr;
89 if (iorr_addr >= AMD_K7_NUM_IORR)
90 return -EINVAL;
91 }
92 base_hi = 0x0;
93 base_lo = (base & ~0xfff) | 0x18;
94 mask_hi = 0xf;
95 mask_lo = ((~(size - 1)) & 0xfffff000) | 0x800;
96 wrmsr(IORR_BASE0 + 2 * iorr_addr, base_lo, base_hi);
97 wrmsr(IORR_MASK0 + 2 * iorr_addr, mask_lo, mask_hi);
98
99 rdmsr(SYSCFG, sys_lo, sys_hi);
100 sys_lo |= 0x00100000;
101 wrmsr(SYSCFG, sys_lo, sys_hi);
102
103 return 0;
104 }
105
106 static int nvidia_configure(void)
107 {
108 int i, rc, num_dirs;
109 u32 apbase, aplimit;
110 struct aper_size_info_8 *current_size;
111 u32 temp;
112
113 current_size = A_SIZE_8(agp_bridge->current_size);
114
115 /* aperture size */
116 pci_write_config_byte(agp_bridge->dev, NVIDIA_0_APSIZE,
117 current_size->size_value);
118
119 /* address to map to */
120 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &apbase);
121 apbase &= PCI_BASE_ADDRESS_MEM_MASK;
122 agp_bridge->gart_bus_addr = apbase;
123 aplimit = apbase + (current_size->size * 1024 * 1024) - 1;
124 pci_write_config_dword(nvidia_private.dev_2, NVIDIA_2_APBASE, apbase);
125 pci_write_config_dword(nvidia_private.dev_2, NVIDIA_2_APLIMIT, aplimit);
126 pci_write_config_dword(nvidia_private.dev_3, NVIDIA_3_APBASE, apbase);
127 pci_write_config_dword(nvidia_private.dev_3, NVIDIA_3_APLIMIT, aplimit);
128 if (0 != (rc = nvidia_init_iorr(apbase, current_size->size * 1024 * 1024)))
129 return rc;
130
131 /* directory size is 64k */
132 num_dirs = current_size->size / 64;
133 nvidia_private.num_active_entries = current_size->num_entries;
134 nvidia_private.pg_offset = 0;
135 if (num_dirs == 0) {
136 num_dirs = 1;
137 nvidia_private.num_active_entries /= (64 / current_size->size);
138 nvidia_private.pg_offset = (apbase & (64 * 1024 * 1024 - 1) &
139 ~(current_size->size * 1024 * 1024 - 1)) / PAGE_SIZE;
140 }
141
142 /* attbase */
143 for (i = 0; i < 8; i++) {
144 pci_write_config_dword(nvidia_private.dev_2, NVIDIA_2_ATTBASE(i),
145 (agp_bridge->gatt_bus_addr + (i % num_dirs) * 64 * 1024) | 1);
146 }
147
148 /* gtlb control */
149 pci_read_config_dword(nvidia_private.dev_2, NVIDIA_2_GARTCTRL, &temp);
150 pci_write_config_dword(nvidia_private.dev_2, NVIDIA_2_GARTCTRL, temp | 0x11);
151
152 /* gart control */
153 pci_read_config_dword(agp_bridge->dev, NVIDIA_0_APSIZE, &temp);
154 pci_write_config_dword(agp_bridge->dev, NVIDIA_0_APSIZE, temp | 0x100);
155
156 /* map aperture */
157 nvidia_private.aperture =
158 (volatile u32 __iomem *) ioremap(apbase, 33 * PAGE_SIZE);
159
160 if (!nvidia_private.aperture)
161 return -ENOMEM;
162
163 return 0;
164 }
165
166 static void nvidia_cleanup(void)
167 {
168 struct aper_size_info_8 *previous_size;
169 u32 temp;
170
171 /* gart control */
172 pci_read_config_dword(agp_bridge->dev, NVIDIA_0_APSIZE, &temp);
173 pci_write_config_dword(agp_bridge->dev, NVIDIA_0_APSIZE, temp & ~(0x100));
174
175 /* gtlb control */
176 pci_read_config_dword(nvidia_private.dev_2, NVIDIA_2_GARTCTRL, &temp);
177 pci_write_config_dword(nvidia_private.dev_2, NVIDIA_2_GARTCTRL, temp & ~(0x11));
178
179 /* unmap aperture */
180 iounmap((void __iomem *) nvidia_private.aperture);
181
182 /* restore previous aperture size */
183 previous_size = A_SIZE_8(agp_bridge->previous_size);
184 pci_write_config_byte(agp_bridge->dev, NVIDIA_0_APSIZE,
185 previous_size->size_value);
186
187 /* restore iorr for previous aperture size */
188 nvidia_init_iorr(agp_bridge->gart_bus_addr,
189 previous_size->size * 1024 * 1024);
190 }
191
192
193 /*
194 * Note we can't use the generic routines, even though they are 99% the same.
195 * Aperture sizes <64M still requires a full 64k GART directory, but
196 * only use the portion of the TLB entries that correspond to the apertures
197 * alignment inside the surrounding 64M block.
198 */
199 extern int agp_memory_reserved;
200
201 static int nvidia_insert_memory(struct agp_memory *mem, off_t pg_start, int type)
202 {
203 int i, j;
204
205 if ((type != 0) || (mem->type != 0))
206 return -EINVAL;
207
208 if ((pg_start + mem->page_count) >
209 (nvidia_private.num_active_entries - agp_memory_reserved/PAGE_SIZE))
210 return -EINVAL;
211
212 for (j = pg_start; j < (pg_start + mem->page_count); j++) {
213 if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+nvidia_private.pg_offset+j)))
214 return -EBUSY;
215 }
216
217 if (mem->is_flushed == FALSE) {
218 global_cache_flush();
219 mem->is_flushed = TRUE;
220 }
221 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
222 writel(agp_bridge->driver->mask_memory(agp_bridge,
223 mem->memory[i], mem->type),
224 agp_bridge->gatt_table+nvidia_private.pg_offset+j);
225 readl(agp_bridge->gatt_table+nvidia_private.pg_offset+j); /* PCI Posting. */
226 }
227 agp_bridge->driver->tlb_flush(mem);
228 return 0;
229 }
230
231
232 static int nvidia_remove_memory(struct agp_memory *mem, off_t pg_start, int type)
233 {
234 int i;
235
236 if ((type != 0) || (mem->type != 0))
237 return -EINVAL;
238
239 for (i = pg_start; i < (mem->page_count + pg_start); i++)
240 writel(agp_bridge->scratch_page, agp_bridge->gatt_table+nvidia_private.pg_offset+i);
241
242 agp_bridge->driver->tlb_flush(mem);
243 return 0;
244 }
245
246
247 static void nvidia_tlbflush(struct agp_memory *mem)
248 {
249 unsigned long end;
250 u32 wbc_reg, temp;
251 int i;
252
253 /* flush chipset */
254 if (nvidia_private.wbc_mask) {
255 pci_read_config_dword(nvidia_private.dev_1, NVIDIA_1_WBC, &wbc_reg);
256 wbc_reg |= nvidia_private.wbc_mask;
257 pci_write_config_dword(nvidia_private.dev_1, NVIDIA_1_WBC, wbc_reg);
258
259 end = jiffies + 3*HZ;
260 do {
261 pci_read_config_dword(nvidia_private.dev_1,
262 NVIDIA_1_WBC, &wbc_reg);
263 if (time_before_eq(end, jiffies)) {
264 printk(KERN_ERR PFX
265 "TLB flush took more than 3 seconds.\n");
266 }
267 } while (wbc_reg & nvidia_private.wbc_mask);
268 }
269
270 /* flush TLB entries */
271 for (i = 0; i < 32 + 1; i++)
272 temp = readl(nvidia_private.aperture+(i * PAGE_SIZE / sizeof(u32)));
273 for (i = 0; i < 32 + 1; i++)
274 temp = readl(nvidia_private.aperture+(i * PAGE_SIZE / sizeof(u32)));
275 }
276
277
278 static const struct aper_size_info_8 nvidia_generic_sizes[5] =
279 {
280 {512, 131072, 7, 0},
281 {256, 65536, 6, 8},
282 {128, 32768, 5, 12},
283 {64, 16384, 4, 14},
284 /* The 32M mode still requires a 64k gatt */
285 {32, 16384, 4, 15}
286 };
287
288
289 static const struct gatt_mask nvidia_generic_masks[] =
290 {
291 { .mask = 1, .type = 0}
292 };
293
294
295 static const struct agp_bridge_driver nvidia_driver = {
296 .owner = THIS_MODULE,
297 .aperture_sizes = nvidia_generic_sizes,
298 .size_type = U8_APER_SIZE,
299 .num_aperture_sizes = 5,
300 .configure = nvidia_configure,
301 .fetch_size = nvidia_fetch_size,
302 .cleanup = nvidia_cleanup,
303 .tlb_flush = nvidia_tlbflush,
304 .mask_memory = agp_generic_mask_memory,
305 .masks = nvidia_generic_masks,
306 .agp_enable = agp_generic_enable,
307 .cache_flush = global_cache_flush,
308 .create_gatt_table = agp_generic_create_gatt_table,
309 .free_gatt_table = agp_generic_free_gatt_table,
310 .insert_memory = nvidia_insert_memory,
311 .remove_memory = nvidia_remove_memory,
312 .alloc_by_type = agp_generic_alloc_by_type,
313 .free_by_type = agp_generic_free_by_type,
314 .agp_alloc_page = agp_generic_alloc_page,
315 .agp_destroy_page = agp_generic_destroy_page,
316 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
317 };
318
319 static int __devinit agp_nvidia_probe(struct pci_dev *pdev,
320 const struct pci_device_id *ent)
321 {
322 struct agp_bridge_data *bridge;
323 u8 cap_ptr;
324
325 nvidia_private.dev_1 =
326 pci_get_bus_and_slot((unsigned int)pdev->bus->number, PCI_DEVFN(0, 1));
327 nvidia_private.dev_2 =
328 pci_get_bus_and_slot((unsigned int)pdev->bus->number, PCI_DEVFN(0, 2));
329 nvidia_private.dev_3 =
330 pci_get_bus_and_slot((unsigned int)pdev->bus->number, PCI_DEVFN(30, 0));
331
332 if (!nvidia_private.dev_1 || !nvidia_private.dev_2 || !nvidia_private.dev_3) {
333 printk(KERN_INFO PFX "Detected an NVIDIA nForce/nForce2 "
334 "chipset, but could not find the secondary devices.\n");
335 return -ENODEV;
336 }
337
338 cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
339 if (!cap_ptr)
340 return -ENODEV;
341
342 switch (pdev->device) {
343 case PCI_DEVICE_ID_NVIDIA_NFORCE:
344 printk(KERN_INFO PFX "Detected NVIDIA nForce chipset\n");
345 nvidia_private.wbc_mask = 0x00010000;
346 break;
347 case PCI_DEVICE_ID_NVIDIA_NFORCE2:
348 printk(KERN_INFO PFX "Detected NVIDIA nForce2 chipset\n");
349 nvidia_private.wbc_mask = 0x80000000;
350 break;
351 default:
352 printk(KERN_ERR PFX "Unsupported NVIDIA chipset (device id: %04x)\n",
353 pdev->device);
354 return -ENODEV;
355 }
356
357 bridge = agp_alloc_bridge();
358 if (!bridge)
359 return -ENOMEM;
360
361 bridge->driver = &nvidia_driver;
362 bridge->dev_private_data = &nvidia_private,
363 bridge->dev = pdev;
364 bridge->capndx = cap_ptr;
365
366 /* Fill in the mode register */
367 pci_read_config_dword(pdev,
368 bridge->capndx+PCI_AGP_STATUS,
369 &bridge->mode);
370
371 pci_set_drvdata(pdev, bridge);
372 return agp_add_bridge(bridge);
373 }
374
375 static void __devexit agp_nvidia_remove(struct pci_dev *pdev)
376 {
377 struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
378
379 agp_remove_bridge(bridge);
380 agp_put_bridge(bridge);
381 }
382
383 #ifdef CONFIG_PM
384 static int agp_nvidia_suspend(struct pci_dev *pdev, pm_message_t state)
385 {
386 pci_save_state (pdev);
387 pci_set_power_state (pdev, 3);
388
389 return 0;
390 }
391
392 static int agp_nvidia_resume(struct pci_dev *pdev)
393 {
394 /* set power state 0 and restore PCI space */
395 pci_set_power_state (pdev, 0);
396 pci_restore_state(pdev);
397
398 /* reconfigure AGP hardware again */
399 nvidia_configure();
400
401 return 0;
402 }
403 #endif
404
405
406 static struct pci_device_id agp_nvidia_pci_table[] = {
407 {
408 .class = (PCI_CLASS_BRIDGE_HOST << 8),
409 .class_mask = ~0,
410 .vendor = PCI_VENDOR_ID_NVIDIA,
411 .device = PCI_DEVICE_ID_NVIDIA_NFORCE,
412 .subvendor = PCI_ANY_ID,
413 .subdevice = PCI_ANY_ID,
414 },
415 {
416 .class = (PCI_CLASS_BRIDGE_HOST << 8),
417 .class_mask = ~0,
418 .vendor = PCI_VENDOR_ID_NVIDIA,
419 .device = PCI_DEVICE_ID_NVIDIA_NFORCE2,
420 .subvendor = PCI_ANY_ID,
421 .subdevice = PCI_ANY_ID,
422 },
423 { }
424 };
425
426 MODULE_DEVICE_TABLE(pci, agp_nvidia_pci_table);
427
428 static struct pci_driver agp_nvidia_pci_driver = {
429 .name = "agpgart-nvidia",
430 .id_table = agp_nvidia_pci_table,
431 .probe = agp_nvidia_probe,
432 .remove = agp_nvidia_remove,
433 #ifdef CONFIG_PM
434 .suspend = agp_nvidia_suspend,
435 .resume = agp_nvidia_resume,
436 #endif
437 };
438
439 static int __init agp_nvidia_init(void)
440 {
441 if (agp_off)
442 return -EINVAL;
443 return pci_register_driver(&agp_nvidia_pci_driver);
444 }
445
446 static void __exit agp_nvidia_cleanup(void)
447 {
448 pci_unregister_driver(&agp_nvidia_pci_driver);
449 pci_dev_put(nvidia_private.dev_1);
450 pci_dev_put(nvidia_private.dev_2);
451 pci_dev_put(nvidia_private.dev_3);
452 }
453
454 module_init(agp_nvidia_init);
455 module_exit(agp_nvidia_cleanup);
456
457 MODULE_LICENSE("GPL and additional rights");
458 MODULE_AUTHOR("NVIDIA Corporation");
459
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