drivers/ide/pci/aec62xx.c

   1 /*
   2  * linux/drivers/ide/pci/aec62xx.c              Version 0.25    Aug 1, 2007
   3  *
   4  * Copyright (C) 1999-2002      Andre Hedrick <andre@linux-ide.org>
   5  * Copyright (C) 2007           MontaVista Software, Inc. <source@mvista.com>
   6  *
   7  */
   8
   9 #include <linux/module.h>
  10 #include <linux/types.h>
  11 #include <linux/pci.h>
  12 #include <linux/delay.h>
  13 #include <linux/hdreg.h>
  14 #include <linux/ide.h>
  15 #include <linux/init.h>
  16
  17 #include <asm/io.h>
  18
  19 struct chipset_bus_clock_list_entry {
  20         u8 xfer_speed;
  21         u8 chipset_settings;
  22         u8 ultra_settings;
  23 };
  24
  25 static const struct chipset_bus_clock_list_entry aec6xxx_33_base [] = {
  26         {       XFER_UDMA_6,    0x31,   0x07    },
  27         {       XFER_UDMA_5,    0x31,   0x06    },
  28         {       XFER_UDMA_4,    0x31,   0x05    },
  29         {       XFER_UDMA_3,    0x31,   0x04    },
  30         {       XFER_UDMA_2,    0x31,   0x03    },
  31         {       XFER_UDMA_1,    0x31,   0x02    },
  32         {       XFER_UDMA_0,    0x31,   0x01    },
  33
  34         {       XFER_MW_DMA_2,  0x31,   0x00    },
  35         {       XFER_MW_DMA_1,  0x31,   0x00    },
  36         {       XFER_MW_DMA_0,  0x0a,   0x00    },
  37         {       XFER_PIO_4,     0x31,   0x00    },
  38         {       XFER_PIO_3,     0x33,   0x00    },
  39         {       XFER_PIO_2,     0x08,   0x00    },
  40         {       XFER_PIO_1,     0x0a,   0x00    },
  41         {       XFER_PIO_0,     0x00,   0x00    },
  42         {       0,              0x00,   0x00    }
  43 };
  44
  45 static const struct chipset_bus_clock_list_entry aec6xxx_34_base [] = {
  46         {       XFER_UDMA_6,    0x41,   0x06    },
  47         {       XFER_UDMA_5,    0x41,   0x05    },
  48         {       XFER_UDMA_4,    0x41,   0x04    },
  49         {       XFER_UDMA_3,    0x41,   0x03    },
  50         {       XFER_UDMA_2,    0x41,   0x02    },
  51         {       XFER_UDMA_1,    0x41,   0x01    },
  52         {       XFER_UDMA_0,    0x41,   0x01    },
  53
  54         {       XFER_MW_DMA_2,  0x41,   0x00    },
  55         {       XFER_MW_DMA_1,  0x42,   0x00    },
  56         {       XFER_MW_DMA_0,  0x7a,   0x00    },
  57         {       XFER_PIO_4,     0x41,   0x00    },
  58         {       XFER_PIO_3,     0x43,   0x00    },
  59         {       XFER_PIO_2,     0x78,   0x00    },
  60         {       XFER_PIO_1,     0x7a,   0x00    },
  61         {       XFER_PIO_0,     0x70,   0x00    },
  62         {       0,              0x00,   0x00    }
  63 };
  64
  65 #define BUSCLOCK(D)     \
  66         ((struct chipset_bus_clock_list_entry *) pci_get_drvdata((D)))
  67
  68
  69 /*
  70  * TO DO: active tuning and correction of cards without a bios.
  71  */
  72 static u8 pci_bus_clock_list (u8 speed, struct chipset_bus_clock_list_entry * chipset_table)
  73 {
  74         for ( ; chipset_table->xfer_speed ; chipset_table++)
  75                 if (chipset_table->xfer_speed == speed) {
  76                         return chipset_table->chipset_settings;
  77                 }
  78         return chipset_table->chipset_settings;
  79 }
  80
  81 static u8 pci_bus_clock_list_ultra (u8 speed, struct chipset_bus_clock_list_entry * chipset_table)
  82 {
  83         for ( ; chipset_table->xfer_speed ; chipset_table++)
  84                 if (chipset_table->xfer_speed == speed) {
  85                         return chipset_table->ultra_settings;
  86                 }
  87         return chipset_table->ultra_settings;
  88 }
  89
  90 static void aec6210_set_mode(ide_drive_t *drive, const u8 speed)
  91 {
  92         ide_hwif_t *hwif        = HWIF(drive);
  93         struct pci_dev *dev     = hwif->pci_dev;
  94         u16 d_conf              = 0;
  95         u8 ultra = 0, ultra_conf = 0;
  96         u8 tmp0 = 0, tmp1 = 0, tmp2 = 0;
  97         unsigned long flags;
  98
  99         local_irq_save(flags);
 100         /* 0x40|(2*drive->dn): Active, 0x41|(2*drive->dn): Recovery */
 101         pci_read_config_word(dev, 0x40|(2*drive->dn), &d_conf);
 102         tmp0 = pci_bus_clock_list(speed, BUSCLOCK(dev));
 103         d_conf = ((tmp0 & 0xf0) << 4) | (tmp0 & 0xf);
 104         pci_write_config_word(dev, 0x40|(2*drive->dn), d_conf);
 105
 106         tmp1 = 0x00;
 107         tmp2 = 0x00;
 108         pci_read_config_byte(dev, 0x54, &ultra);
 109         tmp1 = ((0x00 << (2*drive->dn)) | (ultra & ~(3 << (2*drive->dn))));
 110         ultra_conf = pci_bus_clock_list_ultra(speed, BUSCLOCK(dev));
 111         tmp2 = ((ultra_conf << (2*drive->dn)) | (tmp1 & ~(3 << (2*drive->dn))));
 112         pci_write_config_byte(dev, 0x54, tmp2);
 113         local_irq_restore(flags);
 114 }
 115
 116 static void aec6260_set_mode(ide_drive_t *drive, const u8 speed)
 117 {
 118         ide_hwif_t *hwif        = HWIF(drive);
 119         struct pci_dev *dev     = hwif->pci_dev;
 120         u8 unit         = (drive->select.b.unit & 0x01);
 121         u8 tmp1 = 0, tmp2 = 0;
 122         u8 ultra = 0, drive_conf = 0, ultra_conf = 0;
 123         unsigned long flags;
 124
 125         local_irq_save(flags);
 126         /* high 4-bits: Active, low 4-bits: Recovery */
 127         pci_read_config_byte(dev, 0x40|drive->dn, &drive_conf);
 128         drive_conf = pci_bus_clock_list(speed, BUSCLOCK(dev));
 129         pci_write_config_byte(dev, 0x40|drive->dn, drive_conf);
 130
 131         pci_read_config_byte(dev, (0x44|hwif->channel), &ultra);
 132         tmp1 = ((0x00 << (4*unit)) | (ultra & ~(7 << (4*unit))));
 133         ultra_conf = pci_bus_clock_list_ultra(speed, BUSCLOCK(dev));
 134         tmp2 = ((ultra_conf << (4*unit)) | (tmp1 & ~(7 << (4*unit))));
 135         pci_write_config_byte(dev, (0x44|hwif->channel), tmp2);
 136         local_irq_restore(flags);
 137 }
 138
 139 static void aec_set_pio_mode(ide_drive_t *drive, const u8 pio)
 140 {
 141         drive->hwif->set_dma_mode(drive, pio + XFER_PIO_0);
 142 }
 143
 144 static void aec62xx_dma_lost_irq (ide_drive_t *drive)
 145 {
 146         switch (HWIF(drive)->pci_dev->device) {
 147                 case PCI_DEVICE_ID_ARTOP_ATP860:
 148                 case PCI_DEVICE_ID_ARTOP_ATP860R:
 149                 case PCI_DEVICE_ID_ARTOP_ATP865:
 150                 case PCI_DEVICE_ID_ARTOP_ATP865R:
 151                         printk(" AEC62XX time out ");
 152                 default:
 153                         break;
 154         }
 155 }
 156
 157 static unsigned int __devinit init_chipset_aec62xx(struct pci_dev *dev, const char *name)
 158 {
 159         int bus_speed = system_bus_clock();
 160
 161         if (bus_speed <= 33)
 162                 pci_set_drvdata(dev, (void *) aec6xxx_33_base);
 163         else
 164                 pci_set_drvdata(dev, (void *) aec6xxx_34_base);
 165
 166         /* These are necessary to get AEC6280 Macintosh cards to work */
 167         if ((dev->device == PCI_DEVICE_ID_ARTOP_ATP865) ||
 168             (dev->device == PCI_DEVICE_ID_ARTOP_ATP865R)) {
 169                 u8 reg49h = 0, reg4ah = 0;
 170                 /* Clear reset and test bits.  */
 171                 pci_read_config_byte(dev, 0x49, &reg49h);
 172                 pci_write_config_byte(dev, 0x49, reg49h & ~0x30);
 173                 /* Enable chip interrupt output.  */
 174                 pci_read_config_byte(dev, 0x4a, &reg4ah);
 175                 pci_write_config_byte(dev, 0x4a, reg4ah & ~0x01);
 176                 /* Enable burst mode. */
 177                 pci_read_config_byte(dev, 0x4a, &reg4ah);
 178                 pci_write_config_byte(dev, 0x4a, reg4ah | 0x80);
 179         }
 180
 181         return dev->irq;
 182 }
 183
 184 static void __devinit init_hwif_aec62xx(ide_hwif_t *hwif)
 185 {
 186         struct pci_dev *dev     = hwif->pci_dev;
 187         u8 reg54 = 0,  mask     = hwif->channel ? 0xf0 : 0x0f;
 188         unsigned long flags;
 189
 190         hwif->set_pio_mode = &aec_set_pio_mode;
 191
 192         if (dev->device == PCI_DEVICE_ID_ARTOP_ATP850UF) {
 193                 if(hwif->mate)
 194                         hwif->mate->serialized = hwif->serialized = 1;
 195                 hwif->set_dma_mode = &aec6210_set_mode;
 196         } else
 197                 hwif->set_dma_mode = &aec6260_set_mode;
 198
 199         hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
 200
 201         if (hwif->dma_base == 0)
 202                 return;
 203
 204         hwif->ultra_mask = hwif->cds->udma_mask;
 205         hwif->mwdma_mask = 0x07;
 206
 207         hwif->dma_lost_irq      = &aec62xx_dma_lost_irq;
 208
 209         if (dev->device == PCI_DEVICE_ID_ARTOP_ATP850UF) {
 210                 spin_lock_irqsave(&ide_lock, flags);
 211                 pci_read_config_byte (dev, 0x54, &reg54);
 212                 pci_write_config_byte(dev, 0x54, (reg54 & ~mask));
 213                 spin_unlock_irqrestore(&ide_lock, flags);
 214         } else if (hwif->cbl != ATA_CBL_PATA40_SHORT) {
 215                 u8 ata66 = 0, mask = hwif->channel ? 0x02 : 0x01;
 216
 217                 pci_read_config_byte(hwif->pci_dev, 0x49, &ata66);
 218
 219                 hwif->cbl = (ata66 & mask) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
 220         }
 221 }
 222
 223 static int __devinit init_setup_aec62xx(struct pci_dev *dev, ide_pci_device_t *d)
 224 {
 225         return ide_setup_pci_device(dev, d);
 226 }
 227
 228 static int __devinit init_setup_aec6x80(struct pci_dev *dev, ide_pci_device_t *d)
 229 {
 230         unsigned long dma_base = pci_resource_start(dev, 4);
 231
 232         if (inb(dma_base + 2) & 0x10) {
 233                 d->name = (dev->device == PCI_DEVICE_ID_ARTOP_ATP865R) ?
 234                           "AEC6880R" : "AEC6880";
 235                 d->udma_mask = 0x7f; /* udma0-6 */
 236         }
 237
 238         return ide_setup_pci_device(dev, d);
 239 }
 240
 241 static ide_pci_device_t aec62xx_chipsets[] __devinitdata = {
 242         {       /* 0 */
 243                 .name           = "AEC6210",
 244                 .init_setup     = init_setup_aec62xx,
 245                 .init_chipset   = init_chipset_aec62xx,
 246                 .init_hwif      = init_hwif_aec62xx,
 247                 .autodma        = AUTODMA,
 248                 .enablebits     = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
 249                 .bootable       = OFF_BOARD,
 250                 .pio_mask       = ATA_PIO4,
 251                 .udma_mask      = 0x07, /* udma0-2 */
 252         },{     /* 1 */
 253                 .name           = "AEC6260",
 254                 .init_setup     = init_setup_aec62xx,
 255                 .init_chipset   = init_chipset_aec62xx,
 256                 .init_hwif      = init_hwif_aec62xx,
 257                 .autodma        = NOAUTODMA,
 258                 .bootable       = OFF_BOARD,
 259                 .pio_mask       = ATA_PIO4,
 260                 .udma_mask      = 0x1f, /* udma0-4 */
 261         },{     /* 2 */
 262                 .name           = "AEC6260R",
 263                 .init_setup     = init_setup_aec62xx,
 264                 .init_chipset   = init_chipset_aec62xx,
 265                 .init_hwif      = init_hwif_aec62xx,
 266                 .autodma        = AUTODMA,
 267                 .enablebits     = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
 268                 .bootable       = NEVER_BOARD,
 269                 .pio_mask       = ATA_PIO4,
 270                 .udma_mask      = 0x1f, /* udma0-4 */
 271         },{     /* 3 */
 272                 .name           = "AEC6280",
 273                 .init_setup     = init_setup_aec6x80,
 274                 .init_chipset   = init_chipset_aec62xx,
 275                 .init_hwif      = init_hwif_aec62xx,
 276                 .autodma        = AUTODMA,
 277                 .bootable       = OFF_BOARD,
 278                 .pio_mask       = ATA_PIO4,
 279                 .udma_mask      = 0x3f, /* udma0-5 */
 280         },{     /* 4 */
 281                 .name           = "AEC6280R",
 282                 .init_setup     = init_setup_aec6x80,
 283                 .init_chipset   = init_chipset_aec62xx,
 284                 .init_hwif      = init_hwif_aec62xx,
 285                 .autodma        = AUTODMA,
 286                 .enablebits     = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
 287                 .bootable       = OFF_BOARD,
 288                 .pio_mask       = ATA_PIO4,
 289                 .udma_mask      = 0x3f, /* udma0-5 */
 290         }
 291 };
 292
 293 /**
 294  *      aec62xx_init_one        -       called when a AEC is found
 295  *      @dev: the aec62xx device
 296  *      @id: the matching pci id
 297  *
 298  *      Called when the PCI registration layer (or the IDE initialization)
 299  *      finds a device matching our IDE device tables.
 300  *
 301  *      NOTE: since we're going to modify the 'name' field for AEC-6[26]80[R]
 302  *      chips, pass a local copy of 'struct pci_device_id' down the call chain.
 303  */
 304
 305 static int __devinit aec62xx_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 306 {
 307         ide_pci_device_t d = aec62xx_chipsets[id->driver_data];
 308
 309         return d.init_setup(dev, &d);
 310 }
 311
 312 static const struct pci_device_id aec62xx_pci_tbl[] = {
 313         { PCI_VDEVICE(ARTOP, PCI_DEVICE_ID_ARTOP_ATP850UF), 0 },
 314         { PCI_VDEVICE(ARTOP, PCI_DEVICE_ID_ARTOP_ATP860),   1 },
 315         { PCI_VDEVICE(ARTOP, PCI_DEVICE_ID_ARTOP_ATP860R),  2 },
 316         { PCI_VDEVICE(ARTOP, PCI_DEVICE_ID_ARTOP_ATP865),   3 },
 317         { PCI_VDEVICE(ARTOP, PCI_DEVICE_ID_ARTOP_ATP865R),  4 },
 318         { 0, },
 319 };
 320 MODULE_DEVICE_TABLE(pci, aec62xx_pci_tbl);
 321
 322 static struct pci_driver driver = {
 323         .name           = "AEC62xx_IDE",
 324         .id_table       = aec62xx_pci_tbl,
 325         .probe          = aec62xx_init_one,
 326 };
 327
 328 static int __init aec62xx_ide_init(void)
 329 {
 330         return ide_pci_register_driver(&driver);
 331 }
 332
 333 module_init(aec62xx_ide_init);
 334
 335 MODULE_AUTHOR("Andre Hedrick");
 336 MODULE_DESCRIPTION("PCI driver module for ARTOP AEC62xx IDE");
 337 MODULE_LICENSE("GPL");