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pcmcia: CompactFlash driver for PA Semi Electra boards
[pv_ops_mirror.git] / drivers / usb / host / ehci-sched.c
blob80d99bce2b38fb3d5a6459cdff8eeb5642fa0b06
1 /*
2 * Copyright (c) 2001-2004 by David Brownell
3 * Copyright (c) 2003 Michal Sojka, for high-speed iso transfers
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software Foundation,
17 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 */
19
20 /* this file is part of ehci-hcd.c */
21
22 /*-------------------------------------------------------------------------*/
23
24 /*
25 * EHCI scheduled transaction support: interrupt, iso, split iso
26 * These are called "periodic" transactions in the EHCI spec.
27 *
28 * Note that for interrupt transfers, the QH/QTD manipulation is shared
29 * with the "asynchronous" transaction support (control/bulk transfers).
30 * The only real difference is in how interrupt transfers are scheduled.
31 *
32 * For ISO, we make an "iso_stream" head to serve the same role as a QH.
33 * It keeps track of every ITD (or SITD) that's linked, and holds enough
34 * pre-calculated schedule data to make appending to the queue be quick.
35 */
36
37 static int ehci_get_frame (struct usb_hcd *hcd);
38
39 /*-------------------------------------------------------------------------*/
40
41 /*
42 * periodic_next_shadow - return "next" pointer on shadow list
43 * @periodic: host pointer to qh/itd/sitd
44 * @tag: hardware tag for type of this record
45 */
46 static union ehci_shadow *
47 periodic_next_shadow(struct ehci_hcd *ehci, union ehci_shadow *periodic,
48 __hc32 tag)
49 {
50 switch (hc32_to_cpu(ehci, tag)) {
51 case Q_TYPE_QH:
52 return &periodic->qh->qh_next;
53 case Q_TYPE_FSTN:
54 return &periodic->fstn->fstn_next;
55 case Q_TYPE_ITD:
56 return &periodic->itd->itd_next;
57 // case Q_TYPE_SITD:
58 default:
59 return &periodic->sitd->sitd_next;
60 }
61 }
62
63 /* caller must hold ehci->lock */
64 static void periodic_unlink (struct ehci_hcd *ehci, unsigned frame, void *ptr)
65 {
66 union ehci_shadow *prev_p = &ehci->pshadow[frame];
67 __hc32 *hw_p = &ehci->periodic[frame];
68 union ehci_shadow here = *prev_p;
69
70 /* find predecessor of "ptr"; hw and shadow lists are in sync */
71 while (here.ptr && here.ptr != ptr) {
72 prev_p = periodic_next_shadow(ehci, prev_p,
73 Q_NEXT_TYPE(ehci, *hw_p));
74 hw_p = here.hw_next;
75 here = *prev_p;
76 }
77 /* an interrupt entry (at list end) could have been shared */
78 if (!here.ptr)
79 return;
80
81 /* update shadow and hardware lists ... the old "next" pointers
82 * from ptr may still be in use, the caller updates them.
83 */
84 *prev_p = *periodic_next_shadow(ehci, &here,
85 Q_NEXT_TYPE(ehci, *hw_p));
86 *hw_p = *here.hw_next;
87 }
88
89 /* how many of the uframe's 125 usecs are allocated? */
90 static unsigned short
91 periodic_usecs (struct ehci_hcd *ehci, unsigned frame, unsigned uframe)
92 {
93 __hc32 *hw_p = &ehci->periodic [frame];
94 union ehci_shadow *q = &ehci->pshadow [frame];
95 unsigned usecs = 0;
96
97 while (q->ptr) {
98 switch (hc32_to_cpu(ehci, Q_NEXT_TYPE(ehci, *hw_p))) {
99 case Q_TYPE_QH:
100 /* is it in the S-mask? */
101 if (q->qh->hw_info2 & cpu_to_hc32(ehci, 1 << uframe))
102 usecs += q->qh->usecs;
103 /* ... or C-mask? */
104 if (q->qh->hw_info2 & cpu_to_hc32(ehci,
105 1 << (8 + uframe)))
106 usecs += q->qh->c_usecs;
107 hw_p = &q->qh->hw_next;
108 q = &q->qh->qh_next;
109 break;
110 // case Q_TYPE_FSTN:
111 default:
112 /* for "save place" FSTNs, count the relevant INTR
113 * bandwidth from the previous frame
114 */
115 if (q->fstn->hw_prev != EHCI_LIST_END(ehci)) {
116 ehci_dbg (ehci, "ignoring FSTN cost ...\n");
117 }
118 hw_p = &q->fstn->hw_next;
119 q = &q->fstn->fstn_next;
120 break;
121 case Q_TYPE_ITD:
122 usecs += q->itd->usecs [uframe];
123 hw_p = &q->itd->hw_next;
124 q = &q->itd->itd_next;
125 break;
126 case Q_TYPE_SITD:
127 /* is it in the S-mask? (count SPLIT, DATA) */
128 if (q->sitd->hw_uframe & cpu_to_hc32(ehci,
129 1 << uframe)) {
130 if (q->sitd->hw_fullspeed_ep &
131 cpu_to_hc32(ehci, 1<<31))
132 usecs += q->sitd->stream->usecs;
133 else /* worst case for OUT start-split */
134 usecs += HS_USECS_ISO (188);
135 }
136
137 /* ... C-mask? (count CSPLIT, DATA) */
138 if (q->sitd->hw_uframe &
139 cpu_to_hc32(ehci, 1 << (8 + uframe))) {
140 /* worst case for IN complete-split */
141 usecs += q->sitd->stream->c_usecs;
142 }
143
144 hw_p = &q->sitd->hw_next;
145 q = &q->sitd->sitd_next;
146 break;
147 }
148 }
149 #ifdef DEBUG
150 if (usecs > 100)
151 ehci_err (ehci, "uframe %d sched overrun: %d usecs\n",
152 frame * 8 + uframe, usecs);
153 #endif
154 return usecs;
155 }
156
157 /*-------------------------------------------------------------------------*/
158
159 static int same_tt (struct usb_device *dev1, struct usb_device *dev2)
160 {
161 if (!dev1->tt || !dev2->tt)
162 return 0;
163 if (dev1->tt != dev2->tt)
164 return 0;
165 if (dev1->tt->multi)
166 return dev1->ttport == dev2->ttport;
167 else
168 return 1;
169 }
170
171 #ifdef CONFIG_USB_EHCI_TT_NEWSCHED
172
173 /* Which uframe does the low/fullspeed transfer start in?
174 *
175 * The parameter is the mask of ssplits in "H-frame" terms
176 * and this returns the transfer start uframe in "B-frame" terms,
177 * which allows both to match, e.g. a ssplit in "H-frame" uframe 0
178 * will cause a transfer in "B-frame" uframe 0. "B-frames" lag
179 * "H-frames" by 1 uframe. See the EHCI spec sec 4.5 and figure 4.7.
180 */
181 static inline unsigned char tt_start_uframe(struct ehci_hcd *ehci, __hc32 mask)
182 {
183 unsigned char smask = QH_SMASK & hc32_to_cpu(ehci, mask);
184 if (!smask) {
185 ehci_err(ehci, "invalid empty smask!\n");
186 /* uframe 7 can't have bw so this will indicate failure */
187 return 7;
188 }
189 return ffs(smask) - 1;
190 }
191
192 static const unsigned char
193 max_tt_usecs[] = { 125, 125, 125, 125, 125, 125, 30, 0 };
194
195 /* carryover low/fullspeed bandwidth that crosses uframe boundries */
196 static inline void carryover_tt_bandwidth(unsigned short tt_usecs[8])
197 {
198 int i;
199 for (i=0; i<7; i++) {
200 if (max_tt_usecs[i] < tt_usecs[i]) {
201 tt_usecs[i+1] += tt_usecs[i] - max_tt_usecs[i];
202 tt_usecs[i] = max_tt_usecs[i];
203 }
204 }
205 }
206
207 /* How many of the tt's periodic downstream 1000 usecs are allocated?
208 *
209 * While this measures the bandwidth in terms of usecs/uframe,
210 * the low/fullspeed bus has no notion of uframes, so any particular
211 * low/fullspeed transfer can "carry over" from one uframe to the next,
212 * since the TT just performs downstream transfers in sequence.
213 *
214 * For example two seperate 100 usec transfers can start in the same uframe,
215 * and the second one would "carry over" 75 usecs into the next uframe.
216 */
217 static void
218 periodic_tt_usecs (
219 struct ehci_hcd *ehci,
220 struct usb_device *dev,
221 unsigned frame,
222 unsigned short tt_usecs[8]
223 )
224 {
225 __hc32 *hw_p = &ehci->periodic [frame];
226 union ehci_shadow *q = &ehci->pshadow [frame];
227 unsigned char uf;
228
229 memset(tt_usecs, 0, 16);
230
231 while (q->ptr) {
232 switch (hc32_to_cpu(ehci, Q_NEXT_TYPE(ehci, *hw_p))) {
233 case Q_TYPE_ITD:
234 hw_p = &q->itd->hw_next;
235 q = &q->itd->itd_next;
236 continue;
237 case Q_TYPE_QH:
238 if (same_tt(dev, q->qh->dev)) {
239 uf = tt_start_uframe(ehci, q->qh->hw_info2);
240 tt_usecs[uf] += q->qh->tt_usecs;
241 }
242 hw_p = &q->qh->hw_next;
243 q = &q->qh->qh_next;
244 continue;
245 case Q_TYPE_SITD:
246 if (same_tt(dev, q->sitd->urb->dev)) {
247 uf = tt_start_uframe(ehci, q->sitd->hw_uframe);
248 tt_usecs[uf] += q->sitd->stream->tt_usecs;
249 }
250 hw_p = &q->sitd->hw_next;
251 q = &q->sitd->sitd_next;
252 continue;
253 // case Q_TYPE_FSTN:
254 default:
255 ehci_dbg(ehci, "ignoring periodic frame %d FSTN\n",
256 frame);
257 hw_p = &q->fstn->hw_next;
258 q = &q->fstn->fstn_next;
259 }
260 }
261
262 carryover_tt_bandwidth(tt_usecs);
263
264 if (max_tt_usecs[7] < tt_usecs[7])
265 ehci_err(ehci, "frame %d tt sched overrun: %d usecs\n",
266 frame, tt_usecs[7] - max_tt_usecs[7]);
267 }
268
269 /*
270 * Return true if the device's tt's downstream bus is available for a
271 * periodic transfer of the specified length (usecs), starting at the
272 * specified frame/uframe. Note that (as summarized in section 11.19
273 * of the usb 2.0 spec) TTs can buffer multiple transactions for each
274 * uframe.
275 *
276 * The uframe parameter is when the fullspeed/lowspeed transfer
277 * should be executed in "B-frame" terms, which is the same as the
278 * highspeed ssplit's uframe (which is in "H-frame" terms). For example
279 * a ssplit in "H-frame" 0 causes a transfer in "B-frame" 0.
280 * See the EHCI spec sec 4.5 and fig 4.7.
281 *
282 * This checks if the full/lowspeed bus, at the specified starting uframe,
283 * has the specified bandwidth available, according to rules listed
284 * in USB 2.0 spec section 11.18.1 fig 11-60.
285 *
286 * This does not check if the transfer would exceed the max ssplit
287 * limit of 16, specified in USB 2.0 spec section 11.18.4 requirement #4,
288 * since proper scheduling limits ssplits to less than 16 per uframe.
289 */
290 static int tt_available (
291 struct ehci_hcd *ehci,
292 unsigned period,
293 struct usb_device *dev,
294 unsigned frame,
295 unsigned uframe,
296 u16 usecs
297 )
298 {
299 if ((period == 0) || (uframe >= 7)) /* error */
300 return 0;
301
302 for (; frame < ehci->periodic_size; frame += period) {
303 unsigned short tt_usecs[8];
304
305 periodic_tt_usecs (ehci, dev, frame, tt_usecs);
306
307 ehci_vdbg(ehci, "tt frame %d check %d usecs start uframe %d in"
308 " schedule %d/%d/%d/%d/%d/%d/%d/%d\n",
309 frame, usecs, uframe,
310 tt_usecs[0], tt_usecs[1], tt_usecs[2], tt_usecs[3],
311 tt_usecs[4], tt_usecs[5], tt_usecs[6], tt_usecs[7]);
312
313 if (max_tt_usecs[uframe] <= tt_usecs[uframe]) {
314 ehci_vdbg(ehci, "frame %d uframe %d fully scheduled\n",
315 frame, uframe);
316 return 0;
317 }
318
319 /* special case for isoc transfers larger than 125us:
320 * the first and each subsequent fully used uframe
321 * must be empty, so as to not illegally delay
322 * already scheduled transactions
323 */
324 if (125 < usecs) {
325 int ufs = (usecs / 125) - 1;
326 int i;
327 for (i = uframe; i < (uframe + ufs) && i < 8; i++)
328 if (0 < tt_usecs[i]) {
329 ehci_vdbg(ehci,
330 "multi-uframe xfer can't fit "
331 "in frame %d uframe %d\n",
332 frame, i);
333 return 0;
334 }
335 }
336
337 tt_usecs[uframe] += usecs;
338
339 carryover_tt_bandwidth(tt_usecs);
340
341 /* fail if the carryover pushed bw past the last uframe's limit */
342 if (max_tt_usecs[7] < tt_usecs[7]) {
343 ehci_vdbg(ehci,
344 "tt unavailable usecs %d frame %d uframe %d\n",
345 usecs, frame, uframe);
346 return 0;
347 }
348 }
349
350 return 1;
351 }
352
353 #else
354
355 /* return true iff the device's transaction translator is available
356 * for a periodic transfer starting at the specified frame, using
357 * all the uframes in the mask.
358 */
359 static int tt_no_collision (
360 struct ehci_hcd *ehci,
361 unsigned period,
362 struct usb_device *dev,
363 unsigned frame,
364 u32 uf_mask
365 )
366 {
367 if (period == 0) /* error */
368 return 0;
369
370 /* note bandwidth wastage: split never follows csplit
371 * (different dev or endpoint) until the next uframe.
372 * calling convention doesn't make that distinction.
373 */
374 for (; frame < ehci->periodic_size; frame += period) {
375 union ehci_shadow here;
376 __hc32 type;
377
378 here = ehci->pshadow [frame];
379 type = Q_NEXT_TYPE(ehci, ehci->periodic [frame]);
380 while (here.ptr) {
381 switch (hc32_to_cpu(ehci, type)) {
382 case Q_TYPE_ITD:
383 type = Q_NEXT_TYPE(ehci, here.itd->hw_next);
384 here = here.itd->itd_next;
385 continue;
386 case Q_TYPE_QH:
387 if (same_tt (dev, here.qh->dev)) {
388 u32 mask;
389
390 mask = hc32_to_cpu(ehci,
391 here.qh->hw_info2);
392 /* "knows" no gap is needed */
393 mask |= mask >> 8;
394 if (mask & uf_mask)
395 break;
396 }
397 type = Q_NEXT_TYPE(ehci, here.qh->hw_next);
398 here = here.qh->qh_next;
399 continue;
400 case Q_TYPE_SITD:
401 if (same_tt (dev, here.sitd->urb->dev)) {
402 u16 mask;
403
404 mask = hc32_to_cpu(ehci, here.sitd
405 ->hw_uframe);
406 /* FIXME assumes no gap for IN! */
407 mask |= mask >> 8;
408 if (mask & uf_mask)
409 break;
410 }
411 type = Q_NEXT_TYPE(ehci, here.sitd->hw_next);
412 here = here.sitd->sitd_next;
413 continue;
414 // case Q_TYPE_FSTN:
415 default:
416 ehci_dbg (ehci,
417 "periodic frame %d bogus type %d\n",
418 frame, type);
419 }
420
421 /* collision or error */
422 return 0;
423 }
424 }
425
426 /* no collision */
427 return 1;
428 }
429
430 #endif /* CONFIG_USB_EHCI_TT_NEWSCHED */
431
432 /*-------------------------------------------------------------------------*/
433
434 static int enable_periodic (struct ehci_hcd *ehci)
435 {
436 u32 cmd;
437 int status;
438
439 /* did clearing PSE did take effect yet?
440 * takes effect only at frame boundaries...
441 */
442 status = handshake(ehci, &ehci->regs->status, STS_PSS, 0, 9 * 125);
443 if (status != 0) {
444 ehci_to_hcd(ehci)->state = HC_STATE_HALT;
445 return status;
446 }
447
448 cmd = ehci_readl(ehci, &ehci->regs->command) | CMD_PSE;
449 ehci_writel(ehci, cmd, &ehci->regs->command);
450 /* posted write ... PSS happens later */
451 ehci_to_hcd(ehci)->state = HC_STATE_RUNNING;
452
453 /* make sure ehci_work scans these */
454 ehci->next_uframe = ehci_readl(ehci, &ehci->regs->frame_index)
455 % (ehci->periodic_size << 3);
456 return 0;
457 }
458
459 static int disable_periodic (struct ehci_hcd *ehci)
460 {
461 u32 cmd;
462 int status;
463
464 /* did setting PSE not take effect yet?
465 * takes effect only at frame boundaries...
466 */
467 status = handshake(ehci, &ehci->regs->status, STS_PSS, STS_PSS, 9 * 125);
468 if (status != 0) {
469 ehci_to_hcd(ehci)->state = HC_STATE_HALT;
470 return status;
471 }
472
473 cmd = ehci_readl(ehci, &ehci->regs->command) & ~CMD_PSE;
474 ehci_writel(ehci, cmd, &ehci->regs->command);
475 /* posted write ... */
476
477 ehci->next_uframe = -1;
478 return 0;
479 }
480
481 /*-------------------------------------------------------------------------*/
482
483 /* periodic schedule slots have iso tds (normal or split) first, then a
484 * sparse tree for active interrupt transfers.
485 *
486 * this just links in a qh; caller guarantees uframe masks are set right.
487 * no FSTN support (yet; ehci 0.96+)
488 */
489 static int qh_link_periodic (struct ehci_hcd *ehci, struct ehci_qh *qh)
490 {
491 unsigned i;
492 unsigned period = qh->period;
493
494 dev_dbg (&qh->dev->dev,
495 "link qh%d-%04x/%p start %d [%d/%d us]\n",
496 period, hc32_to_cpup(ehci, &qh->hw_info2) & (QH_CMASK | QH_SMASK),
497 qh, qh->start, qh->usecs, qh->c_usecs);
498
499 /* high bandwidth, or otherwise every microframe */
500 if (period == 0)
501 period = 1;
502
503 for (i = qh->start; i < ehci->periodic_size; i += period) {
504 union ehci_shadow *prev = &ehci->pshadow[i];
505 __hc32 *hw_p = &ehci->periodic[i];
506 union ehci_shadow here = *prev;
507 __hc32 type = 0;
508
509 /* skip the iso nodes at list head */
510 while (here.ptr) {
511 type = Q_NEXT_TYPE(ehci, *hw_p);
512 if (type == cpu_to_hc32(ehci, Q_TYPE_QH))
513 break;
514 prev = periodic_next_shadow(ehci, prev, type);
515 hw_p = &here.qh->hw_next;
516 here = *prev;
517 }
518
519 /* sorting each branch by period (slow-->fast)
520 * enables sharing interior tree nodes
521 */
522 while (here.ptr && qh != here.qh) {
523 if (qh->period > here.qh->period)
524 break;
525 prev = &here.qh->qh_next;
526 hw_p = &here.qh->hw_next;
527 here = *prev;
528 }
529 /* link in this qh, unless some earlier pass did that */
530 if (qh != here.qh) {
531 qh->qh_next = here;
532 if (here.qh)
533 qh->hw_next = *hw_p;
534 wmb ();
535 prev->qh = qh;
536 *hw_p = QH_NEXT (ehci, qh->qh_dma);
537 }
538 }
539 qh->qh_state = QH_STATE_LINKED;
540 qh_get (qh);
541
542 /* update per-qh bandwidth for usbfs */
543 ehci_to_hcd(ehci)->self.bandwidth_allocated += qh->period
544 ? ((qh->usecs + qh->c_usecs) / qh->period)
545 : (qh->usecs * 8);
546
547 /* maybe enable periodic schedule processing */
548 if (!ehci->periodic_sched++)
549 return enable_periodic (ehci);
550
551 return 0;
552 }
553
554 static void qh_unlink_periodic (struct ehci_hcd *ehci, struct ehci_qh *qh)
555 {
556 unsigned i;
557 unsigned period;
558
559 // FIXME:
560 // IF this isn't high speed
561 // and this qh is active in the current uframe
562 // (and overlay token SplitXstate is false?)
563 // THEN
564 // qh->hw_info1 |= __constant_cpu_to_hc32(1 << 7 /* "ignore" */);
565
566 /* high bandwidth, or otherwise part of every microframe */
567 if ((period = qh->period) == 0)
568 period = 1;
569
570 for (i = qh->start; i < ehci->periodic_size; i += period)
571 periodic_unlink (ehci, i, qh);
572
573 /* update per-qh bandwidth for usbfs */
574 ehci_to_hcd(ehci)->self.bandwidth_allocated -= qh->period
575 ? ((qh->usecs + qh->c_usecs) / qh->period)
576 : (qh->usecs * 8);
577
578 dev_dbg (&qh->dev->dev,
579 "unlink qh%d-%04x/%p start %d [%d/%d us]\n",
580 qh->period,
581 hc32_to_cpup(ehci, &qh->hw_info2) & (QH_CMASK | QH_SMASK),
582 qh, qh->start, qh->usecs, qh->c_usecs);
583
584 /* qh->qh_next still "live" to HC */
585 qh->qh_state = QH_STATE_UNLINK;
586 qh->qh_next.ptr = NULL;
587 qh_put (qh);
588
589 /* maybe turn off periodic schedule */
590 ehci->periodic_sched--;
591 if (!ehci->periodic_sched)
592 (void) disable_periodic (ehci);
593 }
594
595 static void intr_deschedule (struct ehci_hcd *ehci, struct ehci_qh *qh)
596 {
597 unsigned wait;
598
599 qh_unlink_periodic (ehci, qh);
600
601 /* simple/paranoid: always delay, expecting the HC needs to read
602 * qh->hw_next or finish a writeback after SPLIT/CSPLIT ... and
603 * expect khubd to clean up after any CSPLITs we won't issue.
604 * active high speed queues may need bigger delays...
605 */
606 if (list_empty (&qh->qtd_list)
607 || (cpu_to_hc32(ehci, QH_CMASK)
608 & qh->hw_info2) != 0)
609 wait = 2;
610 else
611 wait = 55; /* worst case: 3 * 1024 */
612
613 udelay (wait);
614 qh->qh_state = QH_STATE_IDLE;
615 qh->hw_next = EHCI_LIST_END(ehci);
616 wmb ();
617 }
618
619 /*-------------------------------------------------------------------------*/
620
621 static int check_period (
622 struct ehci_hcd *ehci,
623 unsigned frame,
624 unsigned uframe,
625 unsigned period,
626 unsigned usecs
627 ) {
628 int claimed;
629
630 /* complete split running into next frame?
631 * given FSTN support, we could sometimes check...
632 */
633 if (uframe >= 8)
634 return 0;
635
636 /*
637 * 80% periodic == 100 usec/uframe available
638 * convert "usecs we need" to "max already claimed"
639 */
640 usecs = 100 - usecs;
641
642 /* we "know" 2 and 4 uframe intervals were rejected; so
643 * for period 0, check _every_ microframe in the schedule.
644 */
645 if (unlikely (period == 0)) {
646 do {
647 for (uframe = 0; uframe < 7; uframe++) {
648 claimed = periodic_usecs (ehci, frame, uframe);
649 if (claimed > usecs)
650 return 0;
651 }
652 } while ((frame += 1) < ehci->periodic_size);
653
654 /* just check the specified uframe, at that period */
655 } else {
656 do {
657 claimed = periodic_usecs (ehci, frame, uframe);
658 if (claimed > usecs)
659 return 0;
660 } while ((frame += period) < ehci->periodic_size);
661 }
662
663 // success!
664 return 1;
665 }
666
667 static int check_intr_schedule (
668 struct ehci_hcd *ehci,
669 unsigned frame,
670 unsigned uframe,
671 const struct ehci_qh *qh,
672 __hc32 *c_maskp
673 )
674 {
675 int retval = -ENOSPC;
676 u8 mask = 0;
677
678 if (qh->c_usecs && uframe >= 6) /* FSTN territory? */
679 goto done;
680
681 if (!check_period (ehci, frame, uframe, qh->period, qh->usecs))
682 goto done;
683 if (!qh->c_usecs) {
684 retval = 0;
685 *c_maskp = 0;
686 goto done;
687 }
688
689 #ifdef CONFIG_USB_EHCI_TT_NEWSCHED
690 if (tt_available (ehci, qh->period, qh->dev, frame, uframe,
691 qh->tt_usecs)) {
692 unsigned i;
693
694 /* TODO : this may need FSTN for SSPLIT in uframe 5. */
695 for (i=uframe+1; i<8 && i<uframe+4; i++)
696 if (!check_period (ehci, frame, i,
697 qh->period, qh->c_usecs))
698 goto done;
699 else
700 mask |= 1 << i;
701
702 retval = 0;
703
704 *c_maskp = cpu_to_hc32(ehci, mask << 8);
705 }
706 #else
707 /* Make sure this tt's buffer is also available for CSPLITs.
708 * We pessimize a bit; probably the typical full speed case
709 * doesn't need the second CSPLIT.
710 *
711 * NOTE: both SPLIT and CSPLIT could be checked in just
712 * one smart pass...
713 */
714 mask = 0x03 << (uframe + qh->gap_uf);
715 *c_maskp = cpu_to_hc32(ehci, mask << 8);
716
717 mask |= 1 << uframe;
718 if (tt_no_collision (ehci, qh->period, qh->dev, frame, mask)) {
719 if (!check_period (ehci, frame, uframe + qh->gap_uf + 1,
720 qh->period, qh->c_usecs))
721 goto done;
722 if (!check_period (ehci, frame, uframe + qh->gap_uf,
723 qh->period, qh->c_usecs))
724 goto done;
725 retval = 0;
726 }
727 #endif
728 done:
729 return retval;
730 }
731
732 /* "first fit" scheduling policy used the first time through,
733 * or when the previous schedule slot can't be re-used.
734 */
735 static int qh_schedule(struct ehci_hcd *ehci, struct ehci_qh *qh)
736 {
737 int status;
738 unsigned uframe;
739 __hc32 c_mask;
740 unsigned frame; /* 0..(qh->period - 1), or NO_FRAME */
741
742 qh_refresh(ehci, qh);
743 qh->hw_next = EHCI_LIST_END(ehci);
744 frame = qh->start;
745
746 /* reuse the previous schedule slots, if we can */
747 if (frame < qh->period) {
748 uframe = ffs(hc32_to_cpup(ehci, &qh->hw_info2) & QH_SMASK);
749 status = check_intr_schedule (ehci, frame, --uframe,
750 qh, &c_mask);
751 } else {
752 uframe = 0;
753 c_mask = 0;
754 status = -ENOSPC;
755 }
756
757 /* else scan the schedule to find a group of slots such that all
758 * uframes have enough periodic bandwidth available.
759 */
760 if (status) {
761 /* "normal" case, uframing flexible except with splits */
762 if (qh->period) {
763 frame = qh->period - 1;
764 do {
765 for (uframe = 0; uframe < 8; uframe++) {
766 status = check_intr_schedule (ehci,
767 frame, uframe, qh,
768 &c_mask);
769 if (status == 0)
770 break;
771 }
772 } while (status && frame--);
773
774 /* qh->period == 0 means every uframe */
775 } else {
776 frame = 0;
777 status = check_intr_schedule (ehci, 0, 0, qh, &c_mask);
778 }
779 if (status)
780 goto done;
781 qh->start = frame;
782
783 /* reset S-frame and (maybe) C-frame masks */
784 qh->hw_info2 &= cpu_to_hc32(ehci, ~(QH_CMASK | QH_SMASK));
785 qh->hw_info2 |= qh->period
786 ? cpu_to_hc32(ehci, 1 << uframe)
787 : cpu_to_hc32(ehci, QH_SMASK);
788 qh->hw_info2 |= c_mask;
789 } else
790 ehci_dbg (ehci, "reused qh %p schedule\n", qh);
791
792 /* stuff into the periodic schedule */
793 status = qh_link_periodic (ehci, qh);
794 done:
795 return status;
796 }
797
798 static int intr_submit (
799 struct ehci_hcd *ehci,
800 struct urb *urb,
801 struct list_head *qtd_list,
802 gfp_t mem_flags
803 ) {
804 unsigned epnum;
805 unsigned long flags;
806 struct ehci_qh *qh;
807 int status;
808 struct list_head empty;
809
810 /* get endpoint and transfer/schedule data */
811 epnum = urb->ep->desc.bEndpointAddress;
812
813 spin_lock_irqsave (&ehci->lock, flags);
814
815 if (unlikely(!test_bit(HCD_FLAG_HW_ACCESSIBLE,
816 &ehci_to_hcd(ehci)->flags))) {
817 status = -ESHUTDOWN;
818 goto done_not_linked;
819 }
820 status = usb_hcd_link_urb_to_ep(ehci_to_hcd(ehci), urb);
821 if (unlikely(status))
822 goto done_not_linked;
823
824 /* get qh and force any scheduling errors */
825 INIT_LIST_HEAD (&empty);
826 qh = qh_append_tds(ehci, urb, &empty, epnum, &urb->ep->hcpriv);
827 if (qh == NULL) {
828 status = -ENOMEM;
829 goto done;
830 }
831 if (qh->qh_state == QH_STATE_IDLE) {
832 if ((status = qh_schedule (ehci, qh)) != 0)
833 goto done;
834 }
835
836 /* then queue the urb's tds to the qh */
837 qh = qh_append_tds(ehci, urb, qtd_list, epnum, &urb->ep->hcpriv);
838 BUG_ON (qh == NULL);
839
840 /* ... update usbfs periodic stats */
841 ehci_to_hcd(ehci)->self.bandwidth_int_reqs++;
842
843 done:
844 if (unlikely(status))
845 usb_hcd_unlink_urb_from_ep(ehci_to_hcd(ehci), urb);
846 done_not_linked:
847 spin_unlock_irqrestore (&ehci->lock, flags);
848 if (status)
849 qtd_list_free (ehci, urb, qtd_list);
850
851 return status;
852 }
853
854 /*-------------------------------------------------------------------------*/
855
856 /* ehci_iso_stream ops work with both ITD and SITD */
857
858 static struct ehci_iso_stream *
859 iso_stream_alloc (gfp_t mem_flags)
860 {
861 struct ehci_iso_stream *stream;
862
863 stream = kzalloc(sizeof *stream, mem_flags);
864 if (likely (stream != NULL)) {
865 INIT_LIST_HEAD(&stream->td_list);
866 INIT_LIST_HEAD(&stream->free_list);
867 stream->next_uframe = -1;
868 stream->refcount = 1;
869 }
870 return stream;
871 }
872
873 static void
874 iso_stream_init (
875 struct ehci_hcd *ehci,
876 struct ehci_iso_stream *stream,
877 struct usb_device *dev,
878 int pipe,
879 unsigned interval
880 )
881 {
882 static const u8 smask_out [] = { 0x01, 0x03, 0x07, 0x0f, 0x1f, 0x3f };
883
884 u32 buf1;
885 unsigned epnum, maxp;
886 int is_input;
887 long bandwidth;
888
889 /*
890 * this might be a "high bandwidth" highspeed endpoint,
891 * as encoded in the ep descriptor's wMaxPacket field
892 */
893 epnum = usb_pipeendpoint (pipe);
894 is_input = usb_pipein (pipe) ? USB_DIR_IN : 0;
895 maxp = usb_maxpacket(dev, pipe, !is_input);
896 if (is_input) {
897 buf1 = (1 << 11);
898 } else {
899 buf1 = 0;
900 }
901
902 /* knows about ITD vs SITD */
903 if (dev->speed == USB_SPEED_HIGH) {
904 unsigned multi = hb_mult(maxp);
905
906 stream->highspeed = 1;
907
908 maxp = max_packet(maxp);
909 buf1 |= maxp;
910 maxp *= multi;
911
912 stream->buf0 = cpu_to_hc32(ehci, (epnum << 8) | dev->devnum);
913 stream->buf1 = cpu_to_hc32(ehci, buf1);
914 stream->buf2 = cpu_to_hc32(ehci, multi);
915
916 /* usbfs wants to report the average usecs per frame tied up
917 * when transfers on this endpoint are scheduled ...
918 */
919 stream->usecs = HS_USECS_ISO (maxp);
920 bandwidth = stream->usecs * 8;
921 bandwidth /= 1 << (interval - 1);
922
923 } else {
924 u32 addr;
925 int think_time;
926 int hs_transfers;
927
928 addr = dev->ttport << 24;
929 if (!ehci_is_TDI(ehci)
930 || (dev->tt->hub !=
931 ehci_to_hcd(ehci)->self.root_hub))
932 addr |= dev->tt->hub->devnum << 16;
933 addr |= epnum << 8;
934 addr |= dev->devnum;
935 stream->usecs = HS_USECS_ISO (maxp);
936 think_time = dev->tt ? dev->tt->think_time : 0;
937 stream->tt_usecs = NS_TO_US (think_time + usb_calc_bus_time (
938 dev->speed, is_input, 1, maxp));
939 hs_transfers = max (1u, (maxp + 187) / 188);
940 if (is_input) {
941 u32 tmp;
942
943 addr |= 1 << 31;
944 stream->c_usecs = stream->usecs;
945 stream->usecs = HS_USECS_ISO (1);
946 stream->raw_mask = 1;
947
948 /* c-mask as specified in USB 2.0 11.18.4 3.c */
949 tmp = (1 << (hs_transfers + 2)) - 1;
950 stream->raw_mask |= tmp << (8 + 2);
951 } else
952 stream->raw_mask = smask_out [hs_transfers - 1];
953 bandwidth = stream->usecs + stream->c_usecs;
954 bandwidth /= 1 << (interval + 2);
955
956 /* stream->splits gets created from raw_mask later */
957 stream->address = cpu_to_hc32(ehci, addr);
958 }
959 stream->bandwidth = bandwidth;
960
961 stream->udev = dev;
962
963 stream->bEndpointAddress = is_input | epnum;
964 stream->interval = interval;
965 stream->maxp = maxp;
966 }
967
968 static void
969 iso_stream_put(struct ehci_hcd *ehci, struct ehci_iso_stream *stream)
970 {
971 stream->refcount--;
972
973 /* free whenever just a dev->ep reference remains.
974 * not like a QH -- no persistent state (toggle, halt)
975 */
976 if (stream->refcount == 1) {
977 int is_in;
978
979 // BUG_ON (!list_empty(&stream->td_list));
980
981 while (!list_empty (&stream->free_list)) {
982 struct list_head *entry;
983
984 entry = stream->free_list.next;
985 list_del (entry);
986
987 /* knows about ITD vs SITD */
988 if (stream->highspeed) {
989 struct ehci_itd *itd;
990
991 itd = list_entry (entry, struct ehci_itd,
992 itd_list);
993 dma_pool_free (ehci->itd_pool, itd,
994 itd->itd_dma);
995 } else {
996 struct ehci_sitd *sitd;
997
998 sitd = list_entry (entry, struct ehci_sitd,
999 sitd_list);
1000 dma_pool_free (ehci->sitd_pool, sitd,
1001 sitd->sitd_dma);
1002 }
1003 }
1004
1005 is_in = (stream->bEndpointAddress & USB_DIR_IN) ? 0x10 : 0;
1006 stream->bEndpointAddress &= 0x0f;
1007 stream->ep->hcpriv = NULL;
1008
1009 if (stream->rescheduled) {
1010 ehci_info (ehci, "ep%d%s-iso rescheduled "
1011 "%lu times in %lu seconds\n",
1012 stream->bEndpointAddress, is_in ? "in" : "out",
1013 stream->rescheduled,
1014 ((jiffies - stream->start)/HZ)
1015 );
1016 }
1017
1018 kfree(stream);
1019 }
1020 }
1021
1022 static inline struct ehci_iso_stream *
1023 iso_stream_get (struct ehci_iso_stream *stream)
1024 {
1025 if (likely (stream != NULL))
1026 stream->refcount++;
1027 return stream;
1028 }
1029
1030 static struct ehci_iso_stream *
1031 iso_stream_find (struct ehci_hcd *ehci, struct urb *urb)
1032 {
1033 unsigned epnum;
1034 struct ehci_iso_stream *stream;
1035 struct usb_host_endpoint *ep;
1036 unsigned long flags;
1037
1038 epnum = usb_pipeendpoint (urb->pipe);
1039 if (usb_pipein(urb->pipe))
1040 ep = urb->dev->ep_in[epnum];
1041 else
1042 ep = urb->dev->ep_out[epnum];
1043
1044 spin_lock_irqsave (&ehci->lock, flags);
1045 stream = ep->hcpriv;
1046
1047 if (unlikely (stream == NULL)) {
1048 stream = iso_stream_alloc(GFP_ATOMIC);
1049 if (likely (stream != NULL)) {
1050 /* dev->ep owns the initial refcount */
1051 ep->hcpriv = stream;
1052 stream->ep = ep;
1053 iso_stream_init(ehci, stream, urb->dev, urb->pipe,
1054 urb->interval);
1055 }
1056
1057 /* if dev->ep [epnum] is a QH, info1.maxpacket is nonzero */
1058 } else if (unlikely (stream->hw_info1 != 0)) {
1059 ehci_dbg (ehci, "dev %s ep%d%s, not iso??\n",
1060 urb->dev->devpath, epnum,
1061 usb_pipein(urb->pipe) ? "in" : "out");
1062 stream = NULL;
1063 }
1064
1065 /* caller guarantees an eventual matching iso_stream_put */
1066 stream = iso_stream_get (stream);
1067
1068 spin_unlock_irqrestore (&ehci->lock, flags);
1069 return stream;
1070 }
1071
1072 /*-------------------------------------------------------------------------*/
1073
1074 /* ehci_iso_sched ops can be ITD-only or SITD-only */
1075
1076 static struct ehci_iso_sched *
1077 iso_sched_alloc (unsigned packets, gfp_t mem_flags)
1078 {
1079 struct ehci_iso_sched *iso_sched;
1080 int size = sizeof *iso_sched;
1081
1082 size += packets * sizeof (struct ehci_iso_packet);
1083 iso_sched = kzalloc(size, mem_flags);
1084 if (likely (iso_sched != NULL)) {
1085 INIT_LIST_HEAD (&iso_sched->td_list);
1086 }
1087 return iso_sched;
1088 }
1089
1090 static inline void
1091 itd_sched_init(
1092 struct ehci_hcd *ehci,
1093 struct ehci_iso_sched *iso_sched,
1094 struct ehci_iso_stream *stream,
1095 struct urb *urb
1096 )
1097 {
1098 unsigned i;
1099 dma_addr_t dma = urb->transfer_dma;
1100
1101 /* how many uframes are needed for these transfers */
1102 iso_sched->span = urb->number_of_packets * stream->interval;
1103
1104 /* figure out per-uframe itd fields that we'll need later
1105 * when we fit new itds into the schedule.
1106 */
1107 for (i = 0; i < urb->number_of_packets; i++) {
1108 struct ehci_iso_packet *uframe = &iso_sched->packet [i];
1109 unsigned length;
1110 dma_addr_t buf;
1111 u32 trans;
1112
1113 length = urb->iso_frame_desc [i].length;
1114 buf = dma + urb->iso_frame_desc [i].offset;
1115
1116 trans = EHCI_ISOC_ACTIVE;
1117 trans |= buf & 0x0fff;
1118 if (unlikely (((i + 1) == urb->number_of_packets))
1119 && !(urb->transfer_flags & URB_NO_INTERRUPT))
1120 trans |= EHCI_ITD_IOC;
1121 trans |= length << 16;
1122 uframe->transaction = cpu_to_hc32(ehci, trans);
1123
1124 /* might need to cross a buffer page within a uframe */
1125 uframe->bufp = (buf & ~(u64)0x0fff);
1126 buf += length;
1127 if (unlikely ((uframe->bufp != (buf & ~(u64)0x0fff))))
1128 uframe->cross = 1;
1129 }
1130 }
1131
1132 static void
1133 iso_sched_free (
1134 struct ehci_iso_stream *stream,
1135 struct ehci_iso_sched *iso_sched
1136 )
1137 {
1138 if (!iso_sched)
1139 return;
1140 // caller must hold ehci->lock!
1141 list_splice (&iso_sched->td_list, &stream->free_list);
1142 kfree (iso_sched);
1143 }
1144
1145 static int
1146 itd_urb_transaction (
1147 struct ehci_iso_stream *stream,
1148 struct ehci_hcd *ehci,
1149 struct urb *urb,
1150 gfp_t mem_flags
1151 )
1152 {
1153 struct ehci_itd *itd;
1154 dma_addr_t itd_dma;
1155 int i;
1156 unsigned num_itds;
1157 struct ehci_iso_sched *sched;
1158 unsigned long flags;
1159
1160 sched = iso_sched_alloc (urb->number_of_packets, mem_flags);
1161 if (unlikely (sched == NULL))
1162 return -ENOMEM;
1163
1164 itd_sched_init(ehci, sched, stream, urb);
1165
1166 if (urb->interval < 8)
1167 num_itds = 1 + (sched->span + 7) / 8;
1168 else
1169 num_itds = urb->number_of_packets;
1170
1171 /* allocate/init ITDs */
1172 spin_lock_irqsave (&ehci->lock, flags);
1173 for (i = 0; i < num_itds; i++) {
1174
1175 /* free_list.next might be cache-hot ... but maybe
1176 * the HC caches it too. avoid that issue for now.
1177 */
1178
1179 /* prefer previously-allocated itds */
1180 if (likely (!list_empty(&stream->free_list))) {
1181 itd = list_entry (stream->free_list.prev,
1182 struct ehci_itd, itd_list);
1183 list_del (&itd->itd_list);
1184 itd_dma = itd->itd_dma;
1185 } else
1186 itd = NULL;
1187
1188 if (!itd) {
1189 spin_unlock_irqrestore (&ehci->lock, flags);
1190 itd = dma_pool_alloc (ehci->itd_pool, mem_flags,
1191 &itd_dma);
1192 spin_lock_irqsave (&ehci->lock, flags);
1193 }
1194
1195 if (unlikely (NULL == itd)) {
1196 iso_sched_free (stream, sched);
1197 spin_unlock_irqrestore (&ehci->lock, flags);
1198 return -ENOMEM;
1199 }
1200 memset (itd, 0, sizeof *itd);
1201 itd->itd_dma = itd_dma;
1202 list_add (&itd->itd_list, &sched->td_list);
1203 }
1204 spin_unlock_irqrestore (&ehci->lock, flags);
1205
1206 /* temporarily store schedule info in hcpriv */
1207 urb->hcpriv = sched;
1208 urb->error_count = 0;
1209 return 0;
1210 }
1211
1212 /*-------------------------------------------------------------------------*/
1213
1214 static inline int
1215 itd_slot_ok (
1216 struct ehci_hcd *ehci,
1217 u32 mod,
1218 u32 uframe,
1219 u8 usecs,
1220 u32 period
1221 )
1222 {
1223 uframe %= period;
1224 do {
1225 /* can't commit more than 80% periodic == 100 usec */
1226 if (periodic_usecs (ehci, uframe >> 3, uframe & 0x7)
1227 > (100 - usecs))
1228 return 0;
1229
1230 /* we know urb->interval is 2^N uframes */
1231 uframe += period;
1232 } while (uframe < mod);
1233 return 1;
1234 }
1235
1236 static inline int
1237 sitd_slot_ok (
1238 struct ehci_hcd *ehci,
1239 u32 mod,
1240 struct ehci_iso_stream *stream,
1241 u32 uframe,
1242 struct ehci_iso_sched *sched,
1243 u32 period_uframes
1244 )
1245 {
1246 u32 mask, tmp;
1247 u32 frame, uf;
1248
1249 mask = stream->raw_mask << (uframe & 7);
1250
1251 /* for IN, don't wrap CSPLIT into the next frame */
1252 if (mask & ~0xffff)
1253 return 0;
1254
1255 /* this multi-pass logic is simple, but performance may
1256 * suffer when the schedule data isn't cached.
1257 */
1258
1259 /* check bandwidth */
1260 uframe %= period_uframes;
1261 do {
1262 u32 max_used;
1263
1264 frame = uframe >> 3;
1265 uf = uframe & 7;
1266
1267 #ifdef CONFIG_USB_EHCI_TT_NEWSCHED
1268 /* The tt's fullspeed bus bandwidth must be available.
1269 * tt_available scheduling guarantees 10+% for control/bulk.
1270 */
1271 if (!tt_available (ehci, period_uframes << 3,
1272 stream->udev, frame, uf, stream->tt_usecs))
1273 return 0;
1274 #else
1275 /* tt must be idle for start(s), any gap, and csplit.
1276 * assume scheduling slop leaves 10+% for control/bulk.
1277 */
1278 if (!tt_no_collision (ehci, period_uframes << 3,
1279 stream->udev, frame, mask))
1280 return 0;
1281 #endif
1282
1283 /* check starts (OUT uses more than one) */
1284 max_used = 100 - stream->usecs;
1285 for (tmp = stream->raw_mask & 0xff; tmp; tmp >>= 1, uf++) {
1286 if (periodic_usecs (ehci, frame, uf) > max_used)
1287 return 0;
1288 }
1289
1290 /* for IN, check CSPLIT */
1291 if (stream->c_usecs) {
1292 uf = uframe & 7;
1293 max_used = 100 - stream->c_usecs;
1294 do {
1295 tmp = 1 << uf;
1296 tmp <<= 8;
1297 if ((stream->raw_mask & tmp) == 0)
1298 continue;
1299 if (periodic_usecs (ehci, frame, uf)
1300 > max_used)
1301 return 0;
1302 } while (++uf < 8);
1303 }
1304
1305 /* we know urb->interval is 2^N uframes */
1306 uframe += period_uframes;
1307 } while (uframe < mod);
1308
1309 stream->splits = cpu_to_hc32(ehci, stream->raw_mask << (uframe & 7));
1310 return 1;
1311 }
1312
1313 /*
1314 * This scheduler plans almost as far into the future as it has actual
1315 * periodic schedule slots. (Affected by TUNE_FLS, which defaults to
1316 * "as small as possible" to be cache-friendlier.) That limits the size
1317 * transfers you can stream reliably; avoid more than 64 msec per urb.
1318 * Also avoid queue depths of less than ehci's worst irq latency (affected
1319 * by the per-urb URB_NO_INTERRUPT hint, the log2_irq_thresh module parameter,
1320 * and other factors); or more than about 230 msec total (for portability,
1321 * given EHCI_TUNE_FLS and the slop). Or, write a smarter scheduler!
1322 */
1323
1324 #define SCHEDULE_SLOP 10 /* frames */
1325
1326 static int
1327 iso_stream_schedule (
1328 struct ehci_hcd *ehci,
1329 struct urb *urb,
1330 struct ehci_iso_stream *stream
1331 )
1332 {
1333 u32 now, start, max, period;
1334 int status;
1335 unsigned mod = ehci->periodic_size << 3;
1336 struct ehci_iso_sched *sched = urb->hcpriv;
1337
1338 if (sched->span > (mod - 8 * SCHEDULE_SLOP)) {
1339 ehci_dbg (ehci, "iso request %p too long\n", urb);
1340 status = -EFBIG;
1341 goto fail;
1342 }
1343
1344 if ((stream->depth + sched->span) > mod) {
1345 ehci_dbg (ehci, "request %p would overflow (%d+%d>%d)\n",
1346 urb, stream->depth, sched->span, mod);
1347 status = -EFBIG;
1348 goto fail;
1349 }
1350
1351 now = ehci_readl(ehci, &ehci->regs->frame_index) % mod;
1352
1353 /* when's the last uframe this urb could start? */
1354 max = now + mod;
1355
1356 /* typical case: reuse current schedule. stream is still active,
1357 * and no gaps from host falling behind (irq delays etc)
1358 */
1359 if (likely (!list_empty (&stream->td_list))) {
1360 start = stream->next_uframe;
1361 if (start < now)
1362 start += mod;
1363 if (likely ((start + sched->span) < max))
1364 goto ready;
1365 /* else fell behind; someday, try to reschedule */
1366 status = -EL2NSYNC;
1367 goto fail;
1368 }
1369
1370 /* need to schedule; when's the next (u)frame we could start?
1371 * this is bigger than ehci->i_thresh allows; scheduling itself
1372 * isn't free, the slop should handle reasonably slow cpus. it
1373 * can also help high bandwidth if the dma and irq loads don't
1374 * jump until after the queue is primed.
1375 */
1376 start = SCHEDULE_SLOP * 8 + (now & ~0x07);
1377 start %= mod;
1378 stream->next_uframe = start;
1379
1380 /* NOTE: assumes URB_ISO_ASAP, to limit complexity/bugs */
1381
1382 period = urb->interval;
1383 if (!stream->highspeed)
1384 period <<= 3;
1385
1386 /* find a uframe slot with enough bandwidth */
1387 for (; start < (stream->next_uframe + period); start++) {
1388 int enough_space;
1389
1390 /* check schedule: enough space? */
1391 if (stream->highspeed)
1392 enough_space = itd_slot_ok (ehci, mod, start,
1393 stream->usecs, period);
1394 else {
1395 if ((start % 8) >= 6)
1396 continue;
1397 enough_space = sitd_slot_ok (ehci, mod, stream,
1398 start, sched, period);
1399 }
1400
1401 /* schedule it here if there's enough bandwidth */
1402 if (enough_space) {
1403 stream->next_uframe = start % mod;
1404 goto ready;
1405 }
1406 }
1407
1408 /* no room in the schedule */
1409 ehci_dbg (ehci, "iso %ssched full %p (now %d max %d)\n",
1410 list_empty (&stream->td_list) ? "" : "re",
1411 urb, now, max);
1412 status = -ENOSPC;
1413
1414 fail:
1415 iso_sched_free (stream, sched);
1416 urb->hcpriv = NULL;
1417 return status;
1418
1419 ready:
1420 /* report high speed start in uframes; full speed, in frames */
1421 urb->start_frame = stream->next_uframe;
1422 if (!stream->highspeed)
1423 urb->start_frame >>= 3;
1424 return 0;
1425 }
1426
1427 /*-------------------------------------------------------------------------*/
1428
1429 static inline void
1430 itd_init(struct ehci_hcd *ehci, struct ehci_iso_stream *stream,
1431 struct ehci_itd *itd)
1432 {
1433 int i;
1434
1435 /* it's been recently zeroed */
1436 itd->hw_next = EHCI_LIST_END(ehci);
1437 itd->hw_bufp [0] = stream->buf0;
1438 itd->hw_bufp [1] = stream->buf1;
1439 itd->hw_bufp [2] = stream->buf2;
1440
1441 for (i = 0; i < 8; i++)
1442 itd->index[i] = -1;
1443
1444 /* All other fields are filled when scheduling */
1445 }
1446
1447 static inline void
1448 itd_patch(
1449 struct ehci_hcd *ehci,
1450 struct ehci_itd *itd,
1451 struct ehci_iso_sched *iso_sched,
1452 unsigned index,
1453 u16 uframe
1454 )
1455 {
1456 struct ehci_iso_packet *uf = &iso_sched->packet [index];
1457 unsigned pg = itd->pg;
1458
1459 // BUG_ON (pg == 6 && uf->cross);
1460
1461 uframe &= 0x07;
1462 itd->index [uframe] = index;
1463
1464 itd->hw_transaction[uframe] = uf->transaction;
1465 itd->hw_transaction[uframe] |= cpu_to_hc32(ehci, pg << 12);
1466 itd->hw_bufp[pg] |= cpu_to_hc32(ehci, uf->bufp & ~(u32)0);
1467 itd->hw_bufp_hi[pg] |= cpu_to_hc32(ehci, (u32)(uf->bufp >> 32));
1468
1469 /* iso_frame_desc[].offset must be strictly increasing */
1470 if (unlikely (uf->cross)) {
1471 u64 bufp = uf->bufp + 4096;
1472
1473 itd->pg = ++pg;
1474 itd->hw_bufp[pg] |= cpu_to_hc32(ehci, bufp & ~(u32)0);
1475 itd->hw_bufp_hi[pg] |= cpu_to_hc32(ehci, (u32)(bufp >> 32));
1476 }
1477 }
1478
1479 static inline void
1480 itd_link (struct ehci_hcd *ehci, unsigned frame, struct ehci_itd *itd)
1481 {
1482 /* always prepend ITD/SITD ... only QH tree is order-sensitive */
1483 itd->itd_next = ehci->pshadow [frame];
1484 itd->hw_next = ehci->periodic [frame];
1485 ehci->pshadow [frame].itd = itd;
1486 itd->frame = frame;
1487 wmb ();
1488 ehci->periodic[frame] = cpu_to_hc32(ehci, itd->itd_dma | Q_TYPE_ITD);
1489 }
1490
1491 /* fit urb's itds into the selected schedule slot; activate as needed */
1492 static int
1493 itd_link_urb (
1494 struct ehci_hcd *ehci,
1495 struct urb *urb,
1496 unsigned mod,
1497 struct ehci_iso_stream *stream
1498 )
1499 {
1500 int packet;
1501 unsigned next_uframe, uframe, frame;
1502 struct ehci_iso_sched *iso_sched = urb->hcpriv;
1503 struct ehci_itd *itd;
1504
1505 next_uframe = stream->next_uframe % mod;
1506
1507 if (unlikely (list_empty(&stream->td_list))) {
1508 ehci_to_hcd(ehci)->self.bandwidth_allocated
1509 += stream->bandwidth;
1510 ehci_vdbg (ehci,
1511 "schedule devp %s ep%d%s-iso period %d start %d.%d\n",
1512 urb->dev->devpath, stream->bEndpointAddress & 0x0f,
1513 (stream->bEndpointAddress & USB_DIR_IN) ? "in" : "out",
1514 urb->interval,
1515 next_uframe >> 3, next_uframe & 0x7);
1516 stream->start = jiffies;
1517 }
1518 ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs++;
1519
1520 /* fill iTDs uframe by uframe */
1521 for (packet = 0, itd = NULL; packet < urb->number_of_packets; ) {
1522 if (itd == NULL) {
1523 /* ASSERT: we have all necessary itds */
1524 // BUG_ON (list_empty (&iso_sched->td_list));
1525
1526 /* ASSERT: no itds for this endpoint in this uframe */
1527
1528 itd = list_entry (iso_sched->td_list.next,
1529 struct ehci_itd, itd_list);
1530 list_move_tail (&itd->itd_list, &stream->td_list);
1531 itd->stream = iso_stream_get (stream);
1532 itd->urb = usb_get_urb (urb);
1533 itd_init (ehci, stream, itd);
1534 }
1535
1536 uframe = next_uframe & 0x07;
1537 frame = next_uframe >> 3;
1538
1539 itd->usecs [uframe] = stream->usecs;
1540 itd_patch(ehci, itd, iso_sched, packet, uframe);
1541
1542 next_uframe += stream->interval;
1543 stream->depth += stream->interval;
1544 next_uframe %= mod;
1545 packet++;
1546
1547 /* link completed itds into the schedule */
1548 if (((next_uframe >> 3) != frame)
1549 || packet == urb->number_of_packets) {
1550 itd_link (ehci, frame % ehci->periodic_size, itd);
1551 itd = NULL;
1552 }
1553 }
1554 stream->next_uframe = next_uframe;
1555
1556 /* don't need that schedule data any more */
1557 iso_sched_free (stream, iso_sched);
1558 urb->hcpriv = NULL;
1559
1560 timer_action (ehci, TIMER_IO_WATCHDOG);
1561 if (unlikely (!ehci->periodic_sched++))
1562 return enable_periodic (ehci);
1563 return 0;
1564 }
1565
1566 #define ISO_ERRS (EHCI_ISOC_BUF_ERR | EHCI_ISOC_BABBLE | EHCI_ISOC_XACTERR)
1567
1568 static unsigned
1569 itd_complete (
1570 struct ehci_hcd *ehci,
1571 struct ehci_itd *itd
1572 ) {
1573 struct urb *urb = itd->urb;
1574 struct usb_iso_packet_descriptor *desc;
1575 u32 t;
1576 unsigned uframe;
1577 int urb_index = -1;
1578 struct ehci_iso_stream *stream = itd->stream;
1579 struct usb_device *dev;
1580
1581 /* for each uframe with a packet */
1582 for (uframe = 0; uframe < 8; uframe++) {
1583 if (likely (itd->index[uframe] == -1))
1584 continue;
1585 urb_index = itd->index[uframe];
1586 desc = &urb->iso_frame_desc [urb_index];
1587
1588 t = hc32_to_cpup(ehci, &itd->hw_transaction [uframe]);
1589 itd->hw_transaction [uframe] = 0;
1590 stream->depth -= stream->interval;
1591
1592 /* report transfer status */
1593 if (unlikely (t & ISO_ERRS)) {
1594 urb->error_count++;
1595 if (t & EHCI_ISOC_BUF_ERR)
1596 desc->status = usb_pipein (urb->pipe)
1597 ? -ENOSR /* hc couldn't read */
1598 : -ECOMM; /* hc couldn't write */
1599 else if (t & EHCI_ISOC_BABBLE)
1600 desc->status = -EOVERFLOW;
1601 else /* (t & EHCI_ISOC_XACTERR) */
1602 desc->status = -EPROTO;
1603
1604 /* HC need not update length with this error */
1605 if (!(t & EHCI_ISOC_BABBLE))
1606 desc->actual_length = EHCI_ITD_LENGTH (t);
1607 } else if (likely ((t & EHCI_ISOC_ACTIVE) == 0)) {
1608 desc->status = 0;
1609 desc->actual_length = EHCI_ITD_LENGTH (t);
1610 }
1611 }
1612
1613 usb_put_urb (urb);
1614 itd->urb = NULL;
1615 itd->stream = NULL;
1616 list_move (&itd->itd_list, &stream->free_list);
1617 iso_stream_put (ehci, stream);
1618
1619 /* handle completion now? */
1620 if (likely ((urb_index + 1) != urb->number_of_packets))
1621 return 0;
1622
1623 /* ASSERT: it's really the last itd for this urb
1624 list_for_each_entry (itd, &stream->td_list, itd_list)
1625 BUG_ON (itd->urb == urb);
1626 */
1627
1628 /* give urb back to the driver ... can be out-of-order */
1629 dev = urb->dev;
1630 ehci_urb_done(ehci, urb, 0);
1631 urb = NULL;
1632
1633 /* defer stopping schedule; completion can submit */
1634 ehci->periodic_sched--;
1635 if (unlikely (!ehci->periodic_sched))
1636 (void) disable_periodic (ehci);
1637 ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs--;
1638
1639 if (unlikely (list_empty (&stream->td_list))) {
1640 ehci_to_hcd(ehci)->self.bandwidth_allocated
1641 -= stream->bandwidth;
1642 ehci_vdbg (ehci,
1643 "deschedule devp %s ep%d%s-iso\n",
1644 dev->devpath, stream->bEndpointAddress & 0x0f,
1645 (stream->bEndpointAddress & USB_DIR_IN) ? "in" : "out");
1646 }
1647 iso_stream_put (ehci, stream);
1648
1649 return 1;
1650 }
1651
1652 /*-------------------------------------------------------------------------*/
1653
1654 static int itd_submit (struct ehci_hcd *ehci, struct urb *urb,
1655 gfp_t mem_flags)
1656 {
1657 int status = -EINVAL;
1658 unsigned long flags;
1659 struct ehci_iso_stream *stream;
1660
1661 /* Get iso_stream head */
1662 stream = iso_stream_find (ehci, urb);
1663 if (unlikely (stream == NULL)) {
1664 ehci_dbg (ehci, "can't get iso stream\n");
1665 return -ENOMEM;
1666 }
1667 if (unlikely (urb->interval != stream->interval)) {
1668 ehci_dbg (ehci, "can't change iso interval %d --> %d\n",
1669 stream->interval, urb->interval);
1670 goto done;
1671 }
1672
1673 #ifdef EHCI_URB_TRACE
1674 ehci_dbg (ehci,
1675 "%s %s urb %p ep%d%s len %d, %d pkts %d uframes [%p]\n",
1676 __FUNCTION__, urb->dev->devpath, urb,
1677 usb_pipeendpoint (urb->pipe),
1678 usb_pipein (urb->pipe) ? "in" : "out",
1679 urb->transfer_buffer_length,
1680 urb->number_of_packets, urb->interval,
1681 stream);
1682 #endif
1683
1684 /* allocate ITDs w/o locking anything */
1685 status = itd_urb_transaction (stream, ehci, urb, mem_flags);
1686 if (unlikely (status < 0)) {
1687 ehci_dbg (ehci, "can't init itds\n");
1688 goto done;
1689 }
1690
1691 /* schedule ... need to lock */
1692 spin_lock_irqsave (&ehci->lock, flags);
1693 if (unlikely(!test_bit(HCD_FLAG_HW_ACCESSIBLE,
1694 &ehci_to_hcd(ehci)->flags))) {
1695 status = -ESHUTDOWN;
1696 goto done_not_linked;
1697 }
1698 status = usb_hcd_link_urb_to_ep(ehci_to_hcd(ehci), urb);
1699 if (unlikely(status))
1700 goto done_not_linked;
1701 status = iso_stream_schedule(ehci, urb, stream);
1702 if (likely (status == 0))
1703 itd_link_urb (ehci, urb, ehci->periodic_size << 3, stream);
1704 else
1705 usb_hcd_unlink_urb_from_ep(ehci_to_hcd(ehci), urb);
1706 done_not_linked:
1707 spin_unlock_irqrestore (&ehci->lock, flags);
1708
1709 done:
1710 if (unlikely (status < 0))
1711 iso_stream_put (ehci, stream);
1712 return status;
1713 }
1714
1715 #ifdef CONFIG_USB_EHCI_SPLIT_ISO
1716
1717 /*-------------------------------------------------------------------------*/
1718
1719 /*
1720 * "Split ISO TDs" ... used for USB 1.1 devices going through the
1721 * TTs in USB 2.0 hubs. These need microframe scheduling.
1722 */
1723
1724 static inline void
1725 sitd_sched_init(
1726 struct ehci_hcd *ehci,
1727 struct ehci_iso_sched *iso_sched,
1728 struct ehci_iso_stream *stream,
1729 struct urb *urb
1730 )
1731 {
1732 unsigned i;
1733 dma_addr_t dma = urb->transfer_dma;
1734
1735 /* how many frames are needed for these transfers */
1736 iso_sched->span = urb->number_of_packets * stream->interval;
1737
1738 /* figure out per-frame sitd fields that we'll need later
1739 * when we fit new sitds into the schedule.
1740 */
1741 for (i = 0; i < urb->number_of_packets; i++) {
1742 struct ehci_iso_packet *packet = &iso_sched->packet [i];
1743 unsigned length;
1744 dma_addr_t buf;
1745 u32 trans;
1746
1747 length = urb->iso_frame_desc [i].length & 0x03ff;
1748 buf = dma + urb->iso_frame_desc [i].offset;
1749
1750 trans = SITD_STS_ACTIVE;
1751 if (((i + 1) == urb->number_of_packets)
1752 && !(urb->transfer_flags & URB_NO_INTERRUPT))
1753 trans |= SITD_IOC;
1754 trans |= length << 16;
1755 packet->transaction = cpu_to_hc32(ehci, trans);
1756
1757 /* might need to cross a buffer page within a td */
1758 packet->bufp = buf;
1759 packet->buf1 = (buf + length) & ~0x0fff;
1760 if (packet->buf1 != (buf & ~(u64)0x0fff))
1761 packet->cross = 1;
1762
1763 /* OUT uses multiple start-splits */
1764 if (stream->bEndpointAddress & USB_DIR_IN)
1765 continue;
1766 length = (length + 187) / 188;
1767 if (length > 1) /* BEGIN vs ALL */
1768 length |= 1 << 3;
1769 packet->buf1 |= length;
1770 }
1771 }
1772
1773 static int
1774 sitd_urb_transaction (
1775 struct ehci_iso_stream *stream,
1776 struct ehci_hcd *ehci,
1777 struct urb *urb,
1778 gfp_t mem_flags
1779 )
1780 {
1781 struct ehci_sitd *sitd;
1782 dma_addr_t sitd_dma;
1783 int i;
1784 struct ehci_iso_sched *iso_sched;
1785 unsigned long flags;
1786
1787 iso_sched = iso_sched_alloc (urb->number_of_packets, mem_flags);
1788 if (iso_sched == NULL)
1789 return -ENOMEM;
1790
1791 sitd_sched_init(ehci, iso_sched, stream, urb);
1792
1793 /* allocate/init sITDs */
1794 spin_lock_irqsave (&ehci->lock, flags);
1795 for (i = 0; i < urb->number_of_packets; i++) {
1796
1797 /* NOTE: for now, we don't try to handle wraparound cases
1798 * for IN (using sitd->hw_backpointer, like a FSTN), which
1799 * means we never need two sitds for full speed packets.
1800 */
1801
1802 /* free_list.next might be cache-hot ... but maybe
1803 * the HC caches it too. avoid that issue for now.
1804 */
1805
1806 /* prefer previously-allocated sitds */
1807 if (!list_empty(&stream->free_list)) {
1808 sitd = list_entry (stream->free_list.prev,
1809 struct ehci_sitd, sitd_list);
1810 list_del (&sitd->sitd_list);
1811 sitd_dma = sitd->sitd_dma;
1812 } else
1813 sitd = NULL;
1814
1815 if (!sitd) {
1816 spin_unlock_irqrestore (&ehci->lock, flags);
1817 sitd = dma_pool_alloc (ehci->sitd_pool, mem_flags,
1818 &sitd_dma);
1819 spin_lock_irqsave (&ehci->lock, flags);
1820 }
1821
1822 if (!sitd) {
1823 iso_sched_free (stream, iso_sched);
1824 spin_unlock_irqrestore (&ehci->lock, flags);
1825 return -ENOMEM;
1826 }
1827 memset (sitd, 0, sizeof *sitd);
1828 sitd->sitd_dma = sitd_dma;
1829 list_add (&sitd->sitd_list, &iso_sched->td_list);
1830 }
1831
1832 /* temporarily store schedule info in hcpriv */
1833 urb->hcpriv = iso_sched;
1834 urb->error_count = 0;
1835
1836 spin_unlock_irqrestore (&ehci->lock, flags);
1837 return 0;
1838 }
1839
1840 /*-------------------------------------------------------------------------*/
1841
1842 static inline void
1843 sitd_patch(
1844 struct ehci_hcd *ehci,
1845 struct ehci_iso_stream *stream,
1846 struct ehci_sitd *sitd,
1847 struct ehci_iso_sched *iso_sched,
1848 unsigned index
1849 )
1850 {
1851 struct ehci_iso_packet *uf = &iso_sched->packet [index];
1852 u64 bufp = uf->bufp;
1853
1854 sitd->hw_next = EHCI_LIST_END(ehci);
1855 sitd->hw_fullspeed_ep = stream->address;
1856 sitd->hw_uframe = stream->splits;
1857 sitd->hw_results = uf->transaction;
1858 sitd->hw_backpointer = EHCI_LIST_END(ehci);
1859
1860 bufp = uf->bufp;
1861 sitd->hw_buf[0] = cpu_to_hc32(ehci, bufp);
1862 sitd->hw_buf_hi[0] = cpu_to_hc32(ehci, bufp >> 32);
1863
1864 sitd->hw_buf[1] = cpu_to_hc32(ehci, uf->buf1);
1865 if (uf->cross)
1866 bufp += 4096;
1867 sitd->hw_buf_hi[1] = cpu_to_hc32(ehci, bufp >> 32);
1868 sitd->index = index;
1869 }
1870
1871 static inline void
1872 sitd_link (struct ehci_hcd *ehci, unsigned frame, struct ehci_sitd *sitd)
1873 {
1874 /* note: sitd ordering could matter (CSPLIT then SSPLIT) */
1875 sitd->sitd_next = ehci->pshadow [frame];
1876 sitd->hw_next = ehci->periodic [frame];
1877 ehci->pshadow [frame].sitd = sitd;
1878 sitd->frame = frame;
1879 wmb ();
1880 ehci->periodic[frame] = cpu_to_hc32(ehci, sitd->sitd_dma | Q_TYPE_SITD);
1881 }
1882
1883 /* fit urb's sitds into the selected schedule slot; activate as needed */
1884 static int
1885 sitd_link_urb (
1886 struct ehci_hcd *ehci,
1887 struct urb *urb,
1888 unsigned mod,
1889 struct ehci_iso_stream *stream
1890 )
1891 {
1892 int packet;
1893 unsigned next_uframe;
1894 struct ehci_iso_sched *sched = urb->hcpriv;
1895 struct ehci_sitd *sitd;
1896
1897 next_uframe = stream->next_uframe;
1898
1899 if (list_empty(&stream->td_list)) {
1900 /* usbfs ignores TT bandwidth */
1901 ehci_to_hcd(ehci)->self.bandwidth_allocated
1902 += stream->bandwidth;
1903 ehci_vdbg (ehci,
1904 "sched devp %s ep%d%s-iso [%d] %dms/%04x\n",
1905 urb->dev->devpath, stream->bEndpointAddress & 0x0f,
1906 (stream->bEndpointAddress & USB_DIR_IN) ? "in" : "out",
1907 (next_uframe >> 3) % ehci->periodic_size,
1908 stream->interval, hc32_to_cpu(ehci, stream->splits));
1909 stream->start = jiffies;
1910 }
1911 ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs++;
1912
1913 /* fill sITDs frame by frame */
1914 for (packet = 0, sitd = NULL;
1915 packet < urb->number_of_packets;
1916 packet++) {
1917
1918 /* ASSERT: we have all necessary sitds */
1919 BUG_ON (list_empty (&sched->td_list));
1920
1921 /* ASSERT: no itds for this endpoint in this frame */
1922
1923 sitd = list_entry (sched->td_list.next,
1924 struct ehci_sitd, sitd_list);
1925 list_move_tail (&sitd->sitd_list, &stream->td_list);
1926 sitd->stream = iso_stream_get (stream);
1927 sitd->urb = usb_get_urb (urb);
1928
1929 sitd_patch(ehci, stream, sitd, sched, packet);
1930 sitd_link (ehci, (next_uframe >> 3) % ehci->periodic_size,
1931 sitd);
1932
1933 next_uframe += stream->interval << 3;
1934 stream->depth += stream->interval << 3;
1935 }
1936 stream->next_uframe = next_uframe % mod;
1937
1938 /* don't need that schedule data any more */
1939 iso_sched_free (stream, sched);
1940 urb->hcpriv = NULL;
1941
1942 timer_action (ehci, TIMER_IO_WATCHDOG);
1943 if (!ehci->periodic_sched++)
1944 return enable_periodic (ehci);
1945 return 0;
1946 }
1947
1948 /*-------------------------------------------------------------------------*/
1949
1950 #define SITD_ERRS (SITD_STS_ERR | SITD_STS_DBE | SITD_STS_BABBLE \
1951 | SITD_STS_XACT | SITD_STS_MMF)
1952
1953 static unsigned
1954 sitd_complete (
1955 struct ehci_hcd *ehci,
1956 struct ehci_sitd *sitd
1957 ) {
1958 struct urb *urb = sitd->urb;
1959 struct usb_iso_packet_descriptor *desc;
1960 u32 t;
1961 int urb_index = -1;
1962 struct ehci_iso_stream *stream = sitd->stream;
1963 struct usb_device *dev;
1964
1965 urb_index = sitd->index;
1966 desc = &urb->iso_frame_desc [urb_index];
1967 t = hc32_to_cpup(ehci, &sitd->hw_results);
1968
1969 /* report transfer status */
1970 if (t & SITD_ERRS) {
1971 urb->error_count++;
1972 if (t & SITD_STS_DBE)
1973 desc->status = usb_pipein (urb->pipe)
1974 ? -ENOSR /* hc couldn't read */
1975 : -ECOMM; /* hc couldn't write */
1976 else if (t & SITD_STS_BABBLE)
1977 desc->status = -EOVERFLOW;
1978 else /* XACT, MMF, etc */
1979 desc->status = -EPROTO;
1980 } else {
1981 desc->status = 0;
1982 desc->actual_length = desc->length - SITD_LENGTH (t);
1983 }
1984
1985 usb_put_urb (urb);
1986 sitd->urb = NULL;
1987 sitd->stream = NULL;
1988 list_move (&sitd->sitd_list, &stream->free_list);
1989 stream->depth -= stream->interval << 3;
1990 iso_stream_put (ehci, stream);
1991
1992 /* handle completion now? */
1993 if ((urb_index + 1) != urb->number_of_packets)
1994 return 0;
1995
1996 /* ASSERT: it's really the last sitd for this urb
1997 list_for_each_entry (sitd, &stream->td_list, sitd_list)
1998 BUG_ON (sitd->urb == urb);
1999 */
2000
2001 /* give urb back to the driver */
2002 dev = urb->dev;
2003 ehci_urb_done(ehci, urb, 0);
2004 urb = NULL;
2005
2006 /* defer stopping schedule; completion can submit */
2007 ehci->periodic_sched--;
2008 if (!ehci->periodic_sched)
2009 (void) disable_periodic (ehci);
2010 ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs--;
2011
2012 if (list_empty (&stream->td_list)) {
2013 ehci_to_hcd(ehci)->self.bandwidth_allocated
2014 -= stream->bandwidth;
2015 ehci_vdbg (ehci,
2016 "deschedule devp %s ep%d%s-iso\n",
2017 dev->devpath, stream->bEndpointAddress & 0x0f,
2018 (stream->bEndpointAddress & USB_DIR_IN) ? "in" : "out");
2019 }
2020 iso_stream_put (ehci, stream);
2021
2022 return 1;
2023 }
2024
2025
2026 static int sitd_submit (struct ehci_hcd *ehci, struct urb *urb,
2027 gfp_t mem_flags)
2028 {
2029 int status = -EINVAL;
2030 unsigned long flags;
2031 struct ehci_iso_stream *stream;
2032
2033 /* Get iso_stream head */
2034 stream = iso_stream_find (ehci, urb);
2035 if (stream == NULL) {
2036 ehci_dbg (ehci, "can't get iso stream\n");
2037 return -ENOMEM;
2038 }
2039 if (urb->interval != stream->interval) {
2040 ehci_dbg (ehci, "can't change iso interval %d --> %d\n",
2041 stream->interval, urb->interval);
2042 goto done;
2043 }
2044
2045 #ifdef EHCI_URB_TRACE
2046 ehci_dbg (ehci,
2047 "submit %p dev%s ep%d%s-iso len %d\n",
2048 urb, urb->dev->devpath,
2049 usb_pipeendpoint (urb->pipe),
2050 usb_pipein (urb->pipe) ? "in" : "out",
2051 urb->transfer_buffer_length);
2052 #endif
2053
2054 /* allocate SITDs */
2055 status = sitd_urb_transaction (stream, ehci, urb, mem_flags);
2056 if (status < 0) {
2057 ehci_dbg (ehci, "can't init sitds\n");
2058 goto done;
2059 }
2060
2061 /* schedule ... need to lock */
2062 spin_lock_irqsave (&ehci->lock, flags);
2063 if (unlikely(!test_bit(HCD_FLAG_HW_ACCESSIBLE,
2064 &ehci_to_hcd(ehci)->flags))) {
2065 status = -ESHUTDOWN;
2066 goto done_not_linked;
2067 }
2068 status = usb_hcd_link_urb_to_ep(ehci_to_hcd(ehci), urb);
2069 if (unlikely(status))
2070 goto done_not_linked;
2071 status = iso_stream_schedule(ehci, urb, stream);
2072 if (status == 0)
2073 sitd_link_urb (ehci, urb, ehci->periodic_size << 3, stream);
2074 else
2075 usb_hcd_unlink_urb_from_ep(ehci_to_hcd(ehci), urb);
2076 done_not_linked:
2077 spin_unlock_irqrestore (&ehci->lock, flags);
2078
2079 done:
2080 if (status < 0)
2081 iso_stream_put (ehci, stream);
2082 return status;
2083 }
2084
2085 #else
2086
2087 static inline int
2088 sitd_submit (struct ehci_hcd *ehci, struct urb *urb, gfp_t mem_flags)
2089 {
2090 ehci_dbg (ehci, "split iso support is disabled\n");
2091 return -ENOSYS;
2092 }
2093
2094 static inline unsigned
2095 sitd_complete (
2096 struct ehci_hcd *ehci,
2097 struct ehci_sitd *sitd
2098 ) {
2099 ehci_err (ehci, "sitd_complete %p?\n", sitd);
2100 return 0;
2101 }
2102
2103 #endif /* USB_EHCI_SPLIT_ISO */
2104
2105 /*-------------------------------------------------------------------------*/
2106
2107 static void
2108 scan_periodic (struct ehci_hcd *ehci)
2109 {
2110 unsigned frame, clock, now_uframe, mod;
2111 unsigned modified;
2112
2113 mod = ehci->periodic_size << 3;
2114
2115 /*
2116 * When running, scan from last scan point up to "now"
2117 * else clean up by scanning everything that's left.
2118 * Touches as few pages as possible: cache-friendly.
2119 */
2120 now_uframe = ehci->next_uframe;
2121 if (HC_IS_RUNNING (ehci_to_hcd(ehci)->state))
2122 clock = ehci_readl(ehci, &ehci->regs->frame_index);
2123 else
2124 clock = now_uframe + mod - 1;
2125 clock %= mod;
2126
2127 for (;;) {
2128 union ehci_shadow q, *q_p;
2129 __hc32 type, *hw_p;
2130 unsigned uframes;
2131
2132 /* don't scan past the live uframe */
2133 frame = now_uframe >> 3;
2134 if (frame == (clock >> 3))
2135 uframes = now_uframe & 0x07;
2136 else {
2137 /* safe to scan the whole frame at once */
2138 now_uframe |= 0x07;
2139 uframes = 8;
2140 }
2141
2142 restart:
2143 /* scan each element in frame's queue for completions */
2144 q_p = &ehci->pshadow [frame];
2145 hw_p = &ehci->periodic [frame];
2146 q.ptr = q_p->ptr;
2147 type = Q_NEXT_TYPE(ehci, *hw_p);
2148 modified = 0;
2149
2150 while (q.ptr != NULL) {
2151 unsigned uf;
2152 union ehci_shadow temp;
2153 int live;
2154
2155 live = HC_IS_RUNNING (ehci_to_hcd(ehci)->state);
2156 switch (hc32_to_cpu(ehci, type)) {
2157 case Q_TYPE_QH:
2158 /* handle any completions */
2159 temp.qh = qh_get (q.qh);
2160 type = Q_NEXT_TYPE(ehci, q.qh->hw_next);
2161 q = q.qh->qh_next;
2162 modified = qh_completions (ehci, temp.qh);
2163 if (unlikely (list_empty (&temp.qh->qtd_list)))
2164 intr_deschedule (ehci, temp.qh);
2165 qh_put (temp.qh);
2166 break;
2167 case Q_TYPE_FSTN:
2168 /* for "save place" FSTNs, look at QH entries
2169 * in the previous frame for completions.
2170 */
2171 if (q.fstn->hw_prev != EHCI_LIST_END(ehci)) {
2172 dbg ("ignoring completions from FSTNs");
2173 }
2174 type = Q_NEXT_TYPE(ehci, q.fstn->hw_next);
2175 q = q.fstn->fstn_next;
2176 break;
2177 case Q_TYPE_ITD:
2178 /* skip itds for later in the frame */
2179 rmb ();
2180 for (uf = live ? uframes : 8; uf < 8; uf++) {
2181 if (0 == (q.itd->hw_transaction [uf]
2182 & ITD_ACTIVE(ehci)))
2183 continue;
2184 q_p = &q.itd->itd_next;
2185 hw_p = &q.itd->hw_next;
2186 type = Q_NEXT_TYPE(ehci,
2187 q.itd->hw_next);
2188 q = *q_p;
2189 break;
2190 }
2191 if (uf != 8)
2192 break;
2193
2194 /* this one's ready ... HC won't cache the
2195 * pointer for much longer, if at all.
2196 */
2197 *q_p = q.itd->itd_next;
2198 *hw_p = q.itd->hw_next;
2199 type = Q_NEXT_TYPE(ehci, q.itd->hw_next);
2200 wmb();
2201 modified = itd_complete (ehci, q.itd);
2202 q = *q_p;
2203 break;
2204 case Q_TYPE_SITD:
2205 if ((q.sitd->hw_results & SITD_ACTIVE(ehci))
2206 && live) {
2207 q_p = &q.sitd->sitd_next;
2208 hw_p = &q.sitd->hw_next;
2209 type = Q_NEXT_TYPE(ehci,
2210 q.sitd->hw_next);
2211 q = *q_p;
2212 break;
2213 }
2214 *q_p = q.sitd->sitd_next;
2215 *hw_p = q.sitd->hw_next;
2216 type = Q_NEXT_TYPE(ehci, q.sitd->hw_next);
2217 wmb();
2218 modified = sitd_complete (ehci, q.sitd);
2219 q = *q_p;
2220 break;
2221 default:
2222 dbg ("corrupt type %d frame %d shadow %p",
2223 type, frame, q.ptr);
2224 // BUG ();
2225 q.ptr = NULL;
2226 }
2227
2228 /* assume completion callbacks modify the queue */
2229 if (unlikely (modified))
2230 goto restart;
2231 }
2232
2233 /* stop when we catch up to the HC */
2234
2235 // FIXME: this assumes we won't get lapped when
2236 // latencies climb; that should be rare, but...
2237 // detect it, and just go all the way around.
2238 // FLR might help detect this case, so long as latencies
2239 // don't exceed periodic_size msec (default 1.024 sec).
2240
2241 // FIXME: likewise assumes HC doesn't halt mid-scan
2242
2243 if (now_uframe == clock) {
2244 unsigned now;
2245
2246 if (!HC_IS_RUNNING (ehci_to_hcd(ehci)->state))
2247 break;
2248 ehci->next_uframe = now_uframe;
2249 now = ehci_readl(ehci, &ehci->regs->frame_index) % mod;
2250 if (now_uframe == now)
2251 break;
2252
2253 /* rescan the rest of this frame, then ... */
2254 clock = now;
2255 } else {
2256 now_uframe++;
2257 now_uframe %= mod;
2258 }
2259 }
2260 }
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