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FUTEX: new PRIVATE futexes
[pv_ops_mirror.git] / drivers / ata / sata_sil24.c
blobb97ee9f31aece7c8959f82c26b4a754af6e650ce
1 /*
2 * sata_sil24.c - Driver for Silicon Image 3124/3132 SATA-2 controllers
3 *
4 * Copyright 2005 Tejun Heo
5 *
6 * Based on preview driver from Silicon Image.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2, or (at your option) any
11 * later version.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 */
19
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/pci.h>
23 #include <linux/blkdev.h>
24 #include <linux/delay.h>
25 #include <linux/interrupt.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/device.h>
28 #include <scsi/scsi_host.h>
29 #include <scsi/scsi_cmnd.h>
30 #include <linux/libata.h>
31
32 #define DRV_NAME "sata_sil24"
33 #define DRV_VERSION "0.8"
34
35 /*
36 * Port request block (PRB) 32 bytes
37 */
38 struct sil24_prb {
39 __le16 ctrl;
40 __le16 prot;
41 __le32 rx_cnt;
42 u8 fis[6 * 4];
43 };
44
45 /*
46 * Scatter gather entry (SGE) 16 bytes
47 */
48 struct sil24_sge {
49 __le64 addr;
50 __le32 cnt;
51 __le32 flags;
52 };
53
54 /*
55 * Port multiplier
56 */
57 struct sil24_port_multiplier {
58 __le32 diag;
59 __le32 sactive;
60 };
61
62 enum {
63 SIL24_HOST_BAR = 0,
64 SIL24_PORT_BAR = 2,
65
66 /*
67 * Global controller registers (128 bytes @ BAR0)
68 */
69 /* 32 bit regs */
70 HOST_SLOT_STAT = 0x00, /* 32 bit slot stat * 4 */
71 HOST_CTRL = 0x40,
72 HOST_IRQ_STAT = 0x44,
73 HOST_PHY_CFG = 0x48,
74 HOST_BIST_CTRL = 0x50,
75 HOST_BIST_PTRN = 0x54,
76 HOST_BIST_STAT = 0x58,
77 HOST_MEM_BIST_STAT = 0x5c,
78 HOST_FLASH_CMD = 0x70,
79 /* 8 bit regs */
80 HOST_FLASH_DATA = 0x74,
81 HOST_TRANSITION_DETECT = 0x75,
82 HOST_GPIO_CTRL = 0x76,
83 HOST_I2C_ADDR = 0x78, /* 32 bit */
84 HOST_I2C_DATA = 0x7c,
85 HOST_I2C_XFER_CNT = 0x7e,
86 HOST_I2C_CTRL = 0x7f,
87
88 /* HOST_SLOT_STAT bits */
89 HOST_SSTAT_ATTN = (1 << 31),
90
91 /* HOST_CTRL bits */
92 HOST_CTRL_M66EN = (1 << 16), /* M66EN PCI bus signal */
93 HOST_CTRL_TRDY = (1 << 17), /* latched PCI TRDY */
94 HOST_CTRL_STOP = (1 << 18), /* latched PCI STOP */
95 HOST_CTRL_DEVSEL = (1 << 19), /* latched PCI DEVSEL */
96 HOST_CTRL_REQ64 = (1 << 20), /* latched PCI REQ64 */
97 HOST_CTRL_GLOBAL_RST = (1 << 31), /* global reset */
98
99 /*
100 * Port registers
101 * (8192 bytes @ +0x0000, +0x2000, +0x4000 and +0x6000 @ BAR2)
102 */
103 PORT_REGS_SIZE = 0x2000,
104
105 PORT_LRAM = 0x0000, /* 31 LRAM slots and PMP regs */
106 PORT_LRAM_SLOT_SZ = 0x0080, /* 32 bytes PRB + 2 SGE, ACT... */
107
108 PORT_PMP = 0x0f80, /* 8 bytes PMP * 16 (128 bytes) */
109 PORT_PMP_STATUS = 0x0000, /* port device status offset */
110 PORT_PMP_QACTIVE = 0x0004, /* port device QActive offset */
111 PORT_PMP_SIZE = 0x0008, /* 8 bytes per PMP */
112
113 /* 32 bit regs */
114 PORT_CTRL_STAT = 0x1000, /* write: ctrl-set, read: stat */
115 PORT_CTRL_CLR = 0x1004, /* write: ctrl-clear */
116 PORT_IRQ_STAT = 0x1008, /* high: status, low: interrupt */
117 PORT_IRQ_ENABLE_SET = 0x1010, /* write: enable-set */
118 PORT_IRQ_ENABLE_CLR = 0x1014, /* write: enable-clear */
119 PORT_ACTIVATE_UPPER_ADDR= 0x101c,
120 PORT_EXEC_FIFO = 0x1020, /* command execution fifo */
121 PORT_CMD_ERR = 0x1024, /* command error number */
122 PORT_FIS_CFG = 0x1028,
123 PORT_FIFO_THRES = 0x102c,
124 /* 16 bit regs */
125 PORT_DECODE_ERR_CNT = 0x1040,
126 PORT_DECODE_ERR_THRESH = 0x1042,
127 PORT_CRC_ERR_CNT = 0x1044,
128 PORT_CRC_ERR_THRESH = 0x1046,
129 PORT_HSHK_ERR_CNT = 0x1048,
130 PORT_HSHK_ERR_THRESH = 0x104a,
131 /* 32 bit regs */
132 PORT_PHY_CFG = 0x1050,
133 PORT_SLOT_STAT = 0x1800,
134 PORT_CMD_ACTIVATE = 0x1c00, /* 64 bit cmd activate * 31 (248 bytes) */
135 PORT_CONTEXT = 0x1e04,
136 PORT_EXEC_DIAG = 0x1e00, /* 32bit exec diag * 16 (64 bytes, 0-10 used on 3124) */
137 PORT_PSD_DIAG = 0x1e40, /* 32bit psd diag * 16 (64 bytes, 0-8 used on 3124) */
138 PORT_SCONTROL = 0x1f00,
139 PORT_SSTATUS = 0x1f04,
140 PORT_SERROR = 0x1f08,
141 PORT_SACTIVE = 0x1f0c,
142
143 /* PORT_CTRL_STAT bits */
144 PORT_CS_PORT_RST = (1 << 0), /* port reset */
145 PORT_CS_DEV_RST = (1 << 1), /* device reset */
146 PORT_CS_INIT = (1 << 2), /* port initialize */
147 PORT_CS_IRQ_WOC = (1 << 3), /* interrupt write one to clear */
148 PORT_CS_CDB16 = (1 << 5), /* 0=12b cdb, 1=16b cdb */
149 PORT_CS_PMP_RESUME = (1 << 6), /* PMP resume */
150 PORT_CS_32BIT_ACTV = (1 << 10), /* 32-bit activation */
151 PORT_CS_PMP_EN = (1 << 13), /* port multiplier enable */
152 PORT_CS_RDY = (1 << 31), /* port ready to accept commands */
153
154 /* PORT_IRQ_STAT/ENABLE_SET/CLR */
155 /* bits[11:0] are masked */
156 PORT_IRQ_COMPLETE = (1 << 0), /* command(s) completed */
157 PORT_IRQ_ERROR = (1 << 1), /* command execution error */
158 PORT_IRQ_PORTRDY_CHG = (1 << 2), /* port ready change */
159 PORT_IRQ_PWR_CHG = (1 << 3), /* power management change */
160 PORT_IRQ_PHYRDY_CHG = (1 << 4), /* PHY ready change */
161 PORT_IRQ_COMWAKE = (1 << 5), /* COMWAKE received */
162 PORT_IRQ_UNK_FIS = (1 << 6), /* unknown FIS received */
163 PORT_IRQ_DEV_XCHG = (1 << 7), /* device exchanged */
164 PORT_IRQ_8B10B = (1 << 8), /* 8b/10b decode error threshold */
165 PORT_IRQ_CRC = (1 << 9), /* CRC error threshold */
166 PORT_IRQ_HANDSHAKE = (1 << 10), /* handshake error threshold */
167 PORT_IRQ_SDB_NOTIFY = (1 << 11), /* SDB notify received */
168
169 DEF_PORT_IRQ = PORT_IRQ_COMPLETE | PORT_IRQ_ERROR |
170 PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG |
171 PORT_IRQ_UNK_FIS,
172
173 /* bits[27:16] are unmasked (raw) */
174 PORT_IRQ_RAW_SHIFT = 16,
175 PORT_IRQ_MASKED_MASK = 0x7ff,
176 PORT_IRQ_RAW_MASK = (0x7ff << PORT_IRQ_RAW_SHIFT),
177
178 /* ENABLE_SET/CLR specific, intr steering - 2 bit field */
179 PORT_IRQ_STEER_SHIFT = 30,
180 PORT_IRQ_STEER_MASK = (3 << PORT_IRQ_STEER_SHIFT),
181
182 /* PORT_CMD_ERR constants */
183 PORT_CERR_DEV = 1, /* Error bit in D2H Register FIS */
184 PORT_CERR_SDB = 2, /* Error bit in SDB FIS */
185 PORT_CERR_DATA = 3, /* Error in data FIS not detected by dev */
186 PORT_CERR_SEND = 4, /* Initial cmd FIS transmission failure */
187 PORT_CERR_INCONSISTENT = 5, /* Protocol mismatch */
188 PORT_CERR_DIRECTION = 6, /* Data direction mismatch */
189 PORT_CERR_UNDERRUN = 7, /* Ran out of SGEs while writing */
190 PORT_CERR_OVERRUN = 8, /* Ran out of SGEs while reading */
191 PORT_CERR_PKT_PROT = 11, /* DIR invalid in 1st PIO setup of ATAPI */
192 PORT_CERR_SGT_BOUNDARY = 16, /* PLD ecode 00 - SGT not on qword boundary */
193 PORT_CERR_SGT_TGTABRT = 17, /* PLD ecode 01 - target abort */
194 PORT_CERR_SGT_MSTABRT = 18, /* PLD ecode 10 - master abort */
195 PORT_CERR_SGT_PCIPERR = 19, /* PLD ecode 11 - PCI parity err while fetching SGT */
196 PORT_CERR_CMD_BOUNDARY = 24, /* ctrl[15:13] 001 - PRB not on qword boundary */
197 PORT_CERR_CMD_TGTABRT = 25, /* ctrl[15:13] 010 - target abort */
198 PORT_CERR_CMD_MSTABRT = 26, /* ctrl[15:13] 100 - master abort */
199 PORT_CERR_CMD_PCIPERR = 27, /* ctrl[15:13] 110 - PCI parity err while fetching PRB */
200 PORT_CERR_XFR_UNDEF = 32, /* PSD ecode 00 - undefined */
201 PORT_CERR_XFR_TGTABRT = 33, /* PSD ecode 01 - target abort */
202 PORT_CERR_XFR_MSTABRT = 34, /* PSD ecode 10 - master abort */
203 PORT_CERR_XFR_PCIPERR = 35, /* PSD ecode 11 - PCI prity err during transfer */
204 PORT_CERR_SENDSERVICE = 36, /* FIS received while sending service */
205
206 /* bits of PRB control field */
207 PRB_CTRL_PROTOCOL = (1 << 0), /* override def. ATA protocol */
208 PRB_CTRL_PACKET_READ = (1 << 4), /* PACKET cmd read */
209 PRB_CTRL_PACKET_WRITE = (1 << 5), /* PACKET cmd write */
210 PRB_CTRL_NIEN = (1 << 6), /* Mask completion irq */
211 PRB_CTRL_SRST = (1 << 7), /* Soft reset request (ign BSY?) */
212
213 /* PRB protocol field */
214 PRB_PROT_PACKET = (1 << 0),
215 PRB_PROT_TCQ = (1 << 1),
216 PRB_PROT_NCQ = (1 << 2),
217 PRB_PROT_READ = (1 << 3),
218 PRB_PROT_WRITE = (1 << 4),
219 PRB_PROT_TRANSPARENT = (1 << 5),
220
221 /*
222 * Other constants
223 */
224 SGE_TRM = (1 << 31), /* Last SGE in chain */
225 SGE_LNK = (1 << 30), /* linked list
226 Points to SGT, not SGE */
227 SGE_DRD = (1 << 29), /* discard data read (/dev/null)
228 data address ignored */
229
230 SIL24_MAX_CMDS = 31,
231
232 /* board id */
233 BID_SIL3124 = 0,
234 BID_SIL3132 = 1,
235 BID_SIL3131 = 2,
236
237 /* host flags */
238 SIL24_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
239 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
240 ATA_FLAG_NCQ | ATA_FLAG_SKIP_D2H_BSY,
241 SIL24_FLAG_PCIX_IRQ_WOC = (1 << 24), /* IRQ loss errata on PCI-X */
242
243 IRQ_STAT_4PORTS = 0xf,
244 };
245
246 struct sil24_ata_block {
247 struct sil24_prb prb;
248 struct sil24_sge sge[LIBATA_MAX_PRD];
249 };
250
251 struct sil24_atapi_block {
252 struct sil24_prb prb;
253 u8 cdb[16];
254 struct sil24_sge sge[LIBATA_MAX_PRD - 1];
255 };
256
257 union sil24_cmd_block {
258 struct sil24_ata_block ata;
259 struct sil24_atapi_block atapi;
260 };
261
262 static struct sil24_cerr_info {
263 unsigned int err_mask, action;
264 const char *desc;
265 } sil24_cerr_db[] = {
266 [0] = { AC_ERR_DEV, ATA_EH_REVALIDATE,
267 "device error" },
268 [PORT_CERR_DEV] = { AC_ERR_DEV, ATA_EH_REVALIDATE,
269 "device error via D2H FIS" },
270 [PORT_CERR_SDB] = { AC_ERR_DEV, ATA_EH_REVALIDATE,
271 "device error via SDB FIS" },
272 [PORT_CERR_DATA] = { AC_ERR_ATA_BUS, ATA_EH_SOFTRESET,
273 "error in data FIS" },
274 [PORT_CERR_SEND] = { AC_ERR_ATA_BUS, ATA_EH_SOFTRESET,
275 "failed to transmit command FIS" },
276 [PORT_CERR_INCONSISTENT] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
277 "protocol mismatch" },
278 [PORT_CERR_DIRECTION] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
279 "data directon mismatch" },
280 [PORT_CERR_UNDERRUN] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
281 "ran out of SGEs while writing" },
282 [PORT_CERR_OVERRUN] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
283 "ran out of SGEs while reading" },
284 [PORT_CERR_PKT_PROT] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
285 "invalid data directon for ATAPI CDB" },
286 [PORT_CERR_SGT_BOUNDARY] = { AC_ERR_SYSTEM, ATA_EH_SOFTRESET,
287 "SGT no on qword boundary" },
288 [PORT_CERR_SGT_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
289 "PCI target abort while fetching SGT" },
290 [PORT_CERR_SGT_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
291 "PCI master abort while fetching SGT" },
292 [PORT_CERR_SGT_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
293 "PCI parity error while fetching SGT" },
294 [PORT_CERR_CMD_BOUNDARY] = { AC_ERR_SYSTEM, ATA_EH_SOFTRESET,
295 "PRB not on qword boundary" },
296 [PORT_CERR_CMD_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
297 "PCI target abort while fetching PRB" },
298 [PORT_CERR_CMD_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
299 "PCI master abort while fetching PRB" },
300 [PORT_CERR_CMD_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
301 "PCI parity error while fetching PRB" },
302 [PORT_CERR_XFR_UNDEF] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
303 "undefined error while transferring data" },
304 [PORT_CERR_XFR_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
305 "PCI target abort while transferring data" },
306 [PORT_CERR_XFR_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
307 "PCI master abort while transferring data" },
308 [PORT_CERR_XFR_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
309 "PCI parity error while transferring data" },
310 [PORT_CERR_SENDSERVICE] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
311 "FIS received while sending service FIS" },
312 };
313
314 /*
315 * ap->private_data
316 *
317 * The preview driver always returned 0 for status. We emulate it
318 * here from the previous interrupt.
319 */
320 struct sil24_port_priv {
321 union sil24_cmd_block *cmd_block; /* 32 cmd blocks */
322 dma_addr_t cmd_block_dma; /* DMA base addr for them */
323 struct ata_taskfile tf; /* Cached taskfile registers */
324 };
325
326 static void sil24_dev_config(struct ata_device *dev);
327 static u8 sil24_check_status(struct ata_port *ap);
328 static u32 sil24_scr_read(struct ata_port *ap, unsigned sc_reg);
329 static void sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val);
330 static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
331 static void sil24_qc_prep(struct ata_queued_cmd *qc);
332 static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc);
333 static void sil24_irq_clear(struct ata_port *ap);
334 static void sil24_freeze(struct ata_port *ap);
335 static void sil24_thaw(struct ata_port *ap);
336 static void sil24_error_handler(struct ata_port *ap);
337 static void sil24_post_internal_cmd(struct ata_queued_cmd *qc);
338 static int sil24_port_start(struct ata_port *ap);
339 static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
340 #ifdef CONFIG_PM
341 static int sil24_pci_device_resume(struct pci_dev *pdev);
342 #endif
343
344 static const struct pci_device_id sil24_pci_tbl[] = {
345 { PCI_VDEVICE(CMD, 0x3124), BID_SIL3124 },
346 { PCI_VDEVICE(INTEL, 0x3124), BID_SIL3124 },
347 { PCI_VDEVICE(CMD, 0x3132), BID_SIL3132 },
348 { PCI_VDEVICE(CMD, 0x0242), BID_SIL3132 },
349 { PCI_VDEVICE(CMD, 0x3131), BID_SIL3131 },
350 { PCI_VDEVICE(CMD, 0x3531), BID_SIL3131 },
351
352 { } /* terminate list */
353 };
354
355 static struct pci_driver sil24_pci_driver = {
356 .name = DRV_NAME,
357 .id_table = sil24_pci_tbl,
358 .probe = sil24_init_one,
359 .remove = ata_pci_remove_one,
360 #ifdef CONFIG_PM
361 .suspend = ata_pci_device_suspend,
362 .resume = sil24_pci_device_resume,
363 #endif
364 };
365
366 static struct scsi_host_template sil24_sht = {
367 .module = THIS_MODULE,
368 .name = DRV_NAME,
369 .ioctl = ata_scsi_ioctl,
370 .queuecommand = ata_scsi_queuecmd,
371 .change_queue_depth = ata_scsi_change_queue_depth,
372 .can_queue = SIL24_MAX_CMDS,
373 .this_id = ATA_SHT_THIS_ID,
374 .sg_tablesize = LIBATA_MAX_PRD,
375 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
376 .emulated = ATA_SHT_EMULATED,
377 .use_clustering = ATA_SHT_USE_CLUSTERING,
378 .proc_name = DRV_NAME,
379 .dma_boundary = ATA_DMA_BOUNDARY,
380 .slave_configure = ata_scsi_slave_config,
381 .slave_destroy = ata_scsi_slave_destroy,
382 .bios_param = ata_std_bios_param,
383 #ifdef CONFIG_PM
384 .suspend = ata_scsi_device_suspend,
385 .resume = ata_scsi_device_resume,
386 #endif
387 };
388
389 static const struct ata_port_operations sil24_ops = {
390 .port_disable = ata_port_disable,
391
392 .dev_config = sil24_dev_config,
393
394 .check_status = sil24_check_status,
395 .check_altstatus = sil24_check_status,
396 .dev_select = ata_noop_dev_select,
397
398 .tf_read = sil24_tf_read,
399
400 .qc_prep = sil24_qc_prep,
401 .qc_issue = sil24_qc_issue,
402
403 .irq_clear = sil24_irq_clear,
404 .irq_on = ata_dummy_irq_on,
405 .irq_ack = ata_dummy_irq_ack,
406
407 .scr_read = sil24_scr_read,
408 .scr_write = sil24_scr_write,
409
410 .freeze = sil24_freeze,
411 .thaw = sil24_thaw,
412 .error_handler = sil24_error_handler,
413 .post_internal_cmd = sil24_post_internal_cmd,
414
415 .port_start = sil24_port_start,
416 };
417
418 /*
419 * Use bits 30-31 of port_flags to encode available port numbers.
420 * Current maxium is 4.
421 */
422 #define SIL24_NPORTS2FLAG(nports) ((((unsigned)(nports) - 1) & 0x3) << 30)
423 #define SIL24_FLAG2NPORTS(flag) ((((flag) >> 30) & 0x3) + 1)
424
425 static const struct ata_port_info sil24_port_info[] = {
426 /* sil_3124 */
427 {
428 .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(4) |
429 SIL24_FLAG_PCIX_IRQ_WOC,
430 .pio_mask = 0x1f, /* pio0-4 */
431 .mwdma_mask = 0x07, /* mwdma0-2 */
432 .udma_mask = 0x3f, /* udma0-5 */
433 .port_ops = &sil24_ops,
434 },
435 /* sil_3132 */
436 {
437 .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(2),
438 .pio_mask = 0x1f, /* pio0-4 */
439 .mwdma_mask = 0x07, /* mwdma0-2 */
440 .udma_mask = 0x3f, /* udma0-5 */
441 .port_ops = &sil24_ops,
442 },
443 /* sil_3131/sil_3531 */
444 {
445 .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(1),
446 .pio_mask = 0x1f, /* pio0-4 */
447 .mwdma_mask = 0x07, /* mwdma0-2 */
448 .udma_mask = 0x3f, /* udma0-5 */
449 .port_ops = &sil24_ops,
450 },
451 };
452
453 static int sil24_tag(int tag)
454 {
455 if (unlikely(ata_tag_internal(tag)))
456 return 0;
457 return tag;
458 }
459
460 static void sil24_dev_config(struct ata_device *dev)
461 {
462 void __iomem *port = dev->ap->ioaddr.cmd_addr;
463
464 if (dev->cdb_len == 16)
465 writel(PORT_CS_CDB16, port + PORT_CTRL_STAT);
466 else
467 writel(PORT_CS_CDB16, port + PORT_CTRL_CLR);
468 }
469
470 static inline void sil24_update_tf(struct ata_port *ap)
471 {
472 struct sil24_port_priv *pp = ap->private_data;
473 void __iomem *port = ap->ioaddr.cmd_addr;
474 struct sil24_prb __iomem *prb = port;
475 u8 fis[6 * 4];
476
477 memcpy_fromio(fis, prb->fis, 6 * 4);
478 ata_tf_from_fis(fis, &pp->tf);
479 }
480
481 static u8 sil24_check_status(struct ata_port *ap)
482 {
483 struct sil24_port_priv *pp = ap->private_data;
484 return pp->tf.command;
485 }
486
487 static int sil24_scr_map[] = {
488 [SCR_CONTROL] = 0,
489 [SCR_STATUS] = 1,
490 [SCR_ERROR] = 2,
491 [SCR_ACTIVE] = 3,
492 };
493
494 static u32 sil24_scr_read(struct ata_port *ap, unsigned sc_reg)
495 {
496 void __iomem *scr_addr = ap->ioaddr.scr_addr;
497 if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
498 void __iomem *addr;
499 addr = scr_addr + sil24_scr_map[sc_reg] * 4;
500 return readl(scr_addr + sil24_scr_map[sc_reg] * 4);
501 }
502 return 0xffffffffU;
503 }
504
505 static void sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val)
506 {
507 void __iomem *scr_addr = ap->ioaddr.scr_addr;
508 if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
509 void __iomem *addr;
510 addr = scr_addr + sil24_scr_map[sc_reg] * 4;
511 writel(val, scr_addr + sil24_scr_map[sc_reg] * 4);
512 }
513 }
514
515 static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
516 {
517 struct sil24_port_priv *pp = ap->private_data;
518 *tf = pp->tf;
519 }
520
521 static int sil24_init_port(struct ata_port *ap)
522 {
523 void __iomem *port = ap->ioaddr.cmd_addr;
524 u32 tmp;
525
526 writel(PORT_CS_INIT, port + PORT_CTRL_STAT);
527 ata_wait_register(port + PORT_CTRL_STAT,
528 PORT_CS_INIT, PORT_CS_INIT, 10, 100);
529 tmp = ata_wait_register(port + PORT_CTRL_STAT,
530 PORT_CS_RDY, 0, 10, 100);
531
532 if ((tmp & (PORT_CS_INIT | PORT_CS_RDY)) != PORT_CS_RDY)
533 return -EIO;
534 return 0;
535 }
536
537 static int sil24_softreset(struct ata_port *ap, unsigned int *class,
538 unsigned long deadline)
539 {
540 void __iomem *port = ap->ioaddr.cmd_addr;
541 struct sil24_port_priv *pp = ap->private_data;
542 struct sil24_prb *prb = &pp->cmd_block[0].ata.prb;
543 dma_addr_t paddr = pp->cmd_block_dma;
544 u32 mask, irq_stat;
545 const char *reason;
546
547 DPRINTK("ENTER\n");
548
549 if (ata_port_offline(ap)) {
550 DPRINTK("PHY reports no device\n");
551 *class = ATA_DEV_NONE;
552 goto out;
553 }
554
555 /* put the port into known state */
556 if (sil24_init_port(ap)) {
557 reason ="port not ready";
558 goto err;
559 }
560
561 /* do SRST */
562 prb->ctrl = cpu_to_le16(PRB_CTRL_SRST);
563 prb->fis[1] = 0; /* no PMP yet */
564
565 writel((u32)paddr, port + PORT_CMD_ACTIVATE);
566 writel((u64)paddr >> 32, port + PORT_CMD_ACTIVATE + 4);
567
568 mask = (PORT_IRQ_COMPLETE | PORT_IRQ_ERROR) << PORT_IRQ_RAW_SHIFT;
569 irq_stat = ata_wait_register(port + PORT_IRQ_STAT, mask, 0x0,
570 100, jiffies_to_msecs(deadline - jiffies));
571
572 writel(irq_stat, port + PORT_IRQ_STAT); /* clear IRQs */
573 irq_stat >>= PORT_IRQ_RAW_SHIFT;
574
575 if (!(irq_stat & PORT_IRQ_COMPLETE)) {
576 if (irq_stat & PORT_IRQ_ERROR)
577 reason = "SRST command error";
578 else
579 reason = "timeout";
580 goto err;
581 }
582
583 sil24_update_tf(ap);
584 *class = ata_dev_classify(&pp->tf);
585
586 if (*class == ATA_DEV_UNKNOWN)
587 *class = ATA_DEV_NONE;
588
589 out:
590 DPRINTK("EXIT, class=%u\n", *class);
591 return 0;
592
593 err:
594 ata_port_printk(ap, KERN_ERR, "softreset failed (%s)\n", reason);
595 return -EIO;
596 }
597
598 static int sil24_hardreset(struct ata_port *ap, unsigned int *class,
599 unsigned long deadline)
600 {
601 void __iomem *port = ap->ioaddr.cmd_addr;
602 const char *reason;
603 int tout_msec, rc;
604 u32 tmp;
605
606 /* sil24 does the right thing(tm) without any protection */
607 sata_set_spd(ap);
608
609 tout_msec = 100;
610 if (ata_port_online(ap))
611 tout_msec = 5000;
612
613 writel(PORT_CS_DEV_RST, port + PORT_CTRL_STAT);
614 tmp = ata_wait_register(port + PORT_CTRL_STAT,
615 PORT_CS_DEV_RST, PORT_CS_DEV_RST, 10, tout_msec);
616
617 /* SStatus oscillates between zero and valid status after
618 * DEV_RST, debounce it.
619 */
620 rc = sata_phy_debounce(ap, sata_deb_timing_long, deadline);
621 if (rc) {
622 reason = "PHY debouncing failed";
623 goto err;
624 }
625
626 if (tmp & PORT_CS_DEV_RST) {
627 if (ata_port_offline(ap))
628 return 0;
629 reason = "link not ready";
630 goto err;
631 }
632
633 /* Sil24 doesn't store signature FIS after hardreset, so we
634 * can't wait for BSY to clear. Some devices take a long time
635 * to get ready and those devices will choke if we don't wait
636 * for BSY clearance here. Tell libata to perform follow-up
637 * softreset.
638 */
639 return -EAGAIN;
640
641 err:
642 ata_port_printk(ap, KERN_ERR, "hardreset failed (%s)\n", reason);
643 return -EIO;
644 }
645
646 static inline void sil24_fill_sg(struct ata_queued_cmd *qc,
647 struct sil24_sge *sge)
648 {
649 struct scatterlist *sg;
650
651 ata_for_each_sg(sg, qc) {
652 sge->addr = cpu_to_le64(sg_dma_address(sg));
653 sge->cnt = cpu_to_le32(sg_dma_len(sg));
654 if (ata_sg_is_last(sg, qc))
655 sge->flags = cpu_to_le32(SGE_TRM);
656 else
657 sge->flags = 0;
658 sge++;
659 }
660 }
661
662 static void sil24_qc_prep(struct ata_queued_cmd *qc)
663 {
664 struct ata_port *ap = qc->ap;
665 struct sil24_port_priv *pp = ap->private_data;
666 union sil24_cmd_block *cb;
667 struct sil24_prb *prb;
668 struct sil24_sge *sge;
669 u16 ctrl = 0;
670
671 cb = &pp->cmd_block[sil24_tag(qc->tag)];
672
673 switch (qc->tf.protocol) {
674 case ATA_PROT_PIO:
675 case ATA_PROT_DMA:
676 case ATA_PROT_NCQ:
677 case ATA_PROT_NODATA:
678 prb = &cb->ata.prb;
679 sge = cb->ata.sge;
680 break;
681
682 case ATA_PROT_ATAPI:
683 case ATA_PROT_ATAPI_DMA:
684 case ATA_PROT_ATAPI_NODATA:
685 prb = &cb->atapi.prb;
686 sge = cb->atapi.sge;
687 memset(cb->atapi.cdb, 0, 32);
688 memcpy(cb->atapi.cdb, qc->cdb, qc->dev->cdb_len);
689
690 if (qc->tf.protocol != ATA_PROT_ATAPI_NODATA) {
691 if (qc->tf.flags & ATA_TFLAG_WRITE)
692 ctrl = PRB_CTRL_PACKET_WRITE;
693 else
694 ctrl = PRB_CTRL_PACKET_READ;
695 }
696 break;
697
698 default:
699 prb = NULL; /* shut up, gcc */
700 sge = NULL;
701 BUG();
702 }
703
704 prb->ctrl = cpu_to_le16(ctrl);
705 ata_tf_to_fis(&qc->tf, prb->fis, 0);
706
707 if (qc->flags & ATA_QCFLAG_DMAMAP)
708 sil24_fill_sg(qc, sge);
709 }
710
711 static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc)
712 {
713 struct ata_port *ap = qc->ap;
714 struct sil24_port_priv *pp = ap->private_data;
715 void __iomem *port = ap->ioaddr.cmd_addr;
716 unsigned int tag = sil24_tag(qc->tag);
717 dma_addr_t paddr;
718 void __iomem *activate;
719
720 paddr = pp->cmd_block_dma + tag * sizeof(*pp->cmd_block);
721 activate = port + PORT_CMD_ACTIVATE + tag * 8;
722
723 writel((u32)paddr, activate);
724 writel((u64)paddr >> 32, activate + 4);
725
726 return 0;
727 }
728
729 static void sil24_irq_clear(struct ata_port *ap)
730 {
731 /* unused */
732 }
733
734 static void sil24_freeze(struct ata_port *ap)
735 {
736 void __iomem *port = ap->ioaddr.cmd_addr;
737
738 /* Port-wide IRQ mask in HOST_CTRL doesn't really work, clear
739 * PORT_IRQ_ENABLE instead.
740 */
741 writel(0xffff, port + PORT_IRQ_ENABLE_CLR);
742 }
743
744 static void sil24_thaw(struct ata_port *ap)
745 {
746 void __iomem *port = ap->ioaddr.cmd_addr;
747 u32 tmp;
748
749 /* clear IRQ */
750 tmp = readl(port + PORT_IRQ_STAT);
751 writel(tmp, port + PORT_IRQ_STAT);
752
753 /* turn IRQ back on */
754 writel(DEF_PORT_IRQ, port + PORT_IRQ_ENABLE_SET);
755 }
756
757 static void sil24_error_intr(struct ata_port *ap)
758 {
759 void __iomem *port = ap->ioaddr.cmd_addr;
760 struct ata_eh_info *ehi = &ap->eh_info;
761 int freeze = 0;
762 u32 irq_stat;
763
764 /* on error, we need to clear IRQ explicitly */
765 irq_stat = readl(port + PORT_IRQ_STAT);
766 writel(irq_stat, port + PORT_IRQ_STAT);
767
768 /* first, analyze and record host port events */
769 ata_ehi_clear_desc(ehi);
770
771 ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat);
772
773 if (irq_stat & (PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG)) {
774 ata_ehi_hotplugged(ehi);
775 ata_ehi_push_desc(ehi, ", %s",
776 irq_stat & PORT_IRQ_PHYRDY_CHG ?
777 "PHY RDY changed" : "device exchanged");
778 freeze = 1;
779 }
780
781 if (irq_stat & PORT_IRQ_UNK_FIS) {
782 ehi->err_mask |= AC_ERR_HSM;
783 ehi->action |= ATA_EH_SOFTRESET;
784 ata_ehi_push_desc(ehi , ", unknown FIS");
785 freeze = 1;
786 }
787
788 /* deal with command error */
789 if (irq_stat & PORT_IRQ_ERROR) {
790 struct sil24_cerr_info *ci = NULL;
791 unsigned int err_mask = 0, action = 0;
792 struct ata_queued_cmd *qc;
793 u32 cerr;
794
795 /* analyze CMD_ERR */
796 cerr = readl(port + PORT_CMD_ERR);
797 if (cerr < ARRAY_SIZE(sil24_cerr_db))
798 ci = &sil24_cerr_db[cerr];
799
800 if (ci && ci->desc) {
801 err_mask |= ci->err_mask;
802 action |= ci->action;
803 ata_ehi_push_desc(ehi, ", %s", ci->desc);
804 } else {
805 err_mask |= AC_ERR_OTHER;
806 action |= ATA_EH_SOFTRESET;
807 ata_ehi_push_desc(ehi, ", unknown command error %d",
808 cerr);
809 }
810
811 /* record error info */
812 qc = ata_qc_from_tag(ap, ap->active_tag);
813 if (qc) {
814 sil24_update_tf(ap);
815 qc->err_mask |= err_mask;
816 } else
817 ehi->err_mask |= err_mask;
818
819 ehi->action |= action;
820 }
821
822 /* freeze or abort */
823 if (freeze)
824 ata_port_freeze(ap);
825 else
826 ata_port_abort(ap);
827 }
828
829 static void sil24_finish_qc(struct ata_queued_cmd *qc)
830 {
831 if (qc->flags & ATA_QCFLAG_RESULT_TF)
832 sil24_update_tf(qc->ap);
833 }
834
835 static inline void sil24_host_intr(struct ata_port *ap)
836 {
837 void __iomem *port = ap->ioaddr.cmd_addr;
838 u32 slot_stat, qc_active;
839 int rc;
840
841 slot_stat = readl(port + PORT_SLOT_STAT);
842
843 if (unlikely(slot_stat & HOST_SSTAT_ATTN)) {
844 sil24_error_intr(ap);
845 return;
846 }
847
848 if (ap->flags & SIL24_FLAG_PCIX_IRQ_WOC)
849 writel(PORT_IRQ_COMPLETE, port + PORT_IRQ_STAT);
850
851 qc_active = slot_stat & ~HOST_SSTAT_ATTN;
852 rc = ata_qc_complete_multiple(ap, qc_active, sil24_finish_qc);
853 if (rc > 0)
854 return;
855 if (rc < 0) {
856 struct ata_eh_info *ehi = &ap->eh_info;
857 ehi->err_mask |= AC_ERR_HSM;
858 ehi->action |= ATA_EH_SOFTRESET;
859 ata_port_freeze(ap);
860 return;
861 }
862
863 if (ata_ratelimit())
864 ata_port_printk(ap, KERN_INFO, "spurious interrupt "
865 "(slot_stat 0x%x active_tag %d sactive 0x%x)\n",
866 slot_stat, ap->active_tag, ap->sactive);
867 }
868
869 static irqreturn_t sil24_interrupt(int irq, void *dev_instance)
870 {
871 struct ata_host *host = dev_instance;
872 void __iomem *host_base = host->iomap[SIL24_HOST_BAR];
873 unsigned handled = 0;
874 u32 status;
875 int i;
876
877 status = readl(host_base + HOST_IRQ_STAT);
878
879 if (status == 0xffffffff) {
880 printk(KERN_ERR DRV_NAME ": IRQ status == 0xffffffff, "
881 "PCI fault or device removal?\n");
882 goto out;
883 }
884
885 if (!(status & IRQ_STAT_4PORTS))
886 goto out;
887
888 spin_lock(&host->lock);
889
890 for (i = 0; i < host->n_ports; i++)
891 if (status & (1 << i)) {
892 struct ata_port *ap = host->ports[i];
893 if (ap && !(ap->flags & ATA_FLAG_DISABLED)) {
894 sil24_host_intr(host->ports[i]);
895 handled++;
896 } else
897 printk(KERN_ERR DRV_NAME
898 ": interrupt from disabled port %d\n", i);
899 }
900
901 spin_unlock(&host->lock);
902 out:
903 return IRQ_RETVAL(handled);
904 }
905
906 static void sil24_error_handler(struct ata_port *ap)
907 {
908 struct ata_eh_context *ehc = &ap->eh_context;
909
910 if (sil24_init_port(ap)) {
911 ata_eh_freeze_port(ap);
912 ehc->i.action |= ATA_EH_HARDRESET;
913 }
914
915 /* perform recovery */
916 ata_do_eh(ap, ata_std_prereset, sil24_softreset, sil24_hardreset,
917 ata_std_postreset);
918 }
919
920 static void sil24_post_internal_cmd(struct ata_queued_cmd *qc)
921 {
922 struct ata_port *ap = qc->ap;
923
924 /* make DMA engine forget about the failed command */
925 if (qc->flags & ATA_QCFLAG_FAILED)
926 sil24_init_port(ap);
927 }
928
929 static int sil24_port_start(struct ata_port *ap)
930 {
931 struct device *dev = ap->host->dev;
932 struct sil24_port_priv *pp;
933 union sil24_cmd_block *cb;
934 size_t cb_size = sizeof(*cb) * SIL24_MAX_CMDS;
935 dma_addr_t cb_dma;
936 int rc;
937
938 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
939 if (!pp)
940 return -ENOMEM;
941
942 pp->tf.command = ATA_DRDY;
943
944 cb = dmam_alloc_coherent(dev, cb_size, &cb_dma, GFP_KERNEL);
945 if (!cb)
946 return -ENOMEM;
947 memset(cb, 0, cb_size);
948
949 rc = ata_pad_alloc(ap, dev);
950 if (rc)
951 return rc;
952
953 pp->cmd_block = cb;
954 pp->cmd_block_dma = cb_dma;
955
956 ap->private_data = pp;
957
958 return 0;
959 }
960
961 static void sil24_init_controller(struct ata_host *host)
962 {
963 void __iomem *host_base = host->iomap[SIL24_HOST_BAR];
964 void __iomem *port_base = host->iomap[SIL24_PORT_BAR];
965 u32 tmp;
966 int i;
967
968 /* GPIO off */
969 writel(0, host_base + HOST_FLASH_CMD);
970
971 /* clear global reset & mask interrupts during initialization */
972 writel(0, host_base + HOST_CTRL);
973
974 /* init ports */
975 for (i = 0; i < host->n_ports; i++) {
976 void __iomem *port = port_base + i * PORT_REGS_SIZE;
977
978 /* Initial PHY setting */
979 writel(0x20c, port + PORT_PHY_CFG);
980
981 /* Clear port RST */
982 tmp = readl(port + PORT_CTRL_STAT);
983 if (tmp & PORT_CS_PORT_RST) {
984 writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR);
985 tmp = ata_wait_register(port + PORT_CTRL_STAT,
986 PORT_CS_PORT_RST,
987 PORT_CS_PORT_RST, 10, 100);
988 if (tmp & PORT_CS_PORT_RST)
989 dev_printk(KERN_ERR, host->dev,
990 "failed to clear port RST\n");
991 }
992
993 /* Configure IRQ WoC */
994 if (host->ports[0]->flags & SIL24_FLAG_PCIX_IRQ_WOC)
995 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_STAT);
996 else
997 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR);
998
999 /* Zero error counters. */
1000 writel(0x8000, port + PORT_DECODE_ERR_THRESH);
1001 writel(0x8000, port + PORT_CRC_ERR_THRESH);
1002 writel(0x8000, port + PORT_HSHK_ERR_THRESH);
1003 writel(0x0000, port + PORT_DECODE_ERR_CNT);
1004 writel(0x0000, port + PORT_CRC_ERR_CNT);
1005 writel(0x0000, port + PORT_HSHK_ERR_CNT);
1006
1007 /* Always use 64bit activation */
1008 writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_CLR);
1009
1010 /* Clear port multiplier enable and resume bits */
1011 writel(PORT_CS_PMP_EN | PORT_CS_PMP_RESUME,
1012 port + PORT_CTRL_CLR);
1013 }
1014
1015 /* Turn on interrupts */
1016 writel(IRQ_STAT_4PORTS, host_base + HOST_CTRL);
1017 }
1018
1019 static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1020 {
1021 static int printed_version = 0;
1022 struct ata_port_info pi = sil24_port_info[ent->driver_data];
1023 const struct ata_port_info *ppi[] = { &pi, NULL };
1024 void __iomem * const *iomap;
1025 struct ata_host *host;
1026 int i, rc;
1027 u32 tmp;
1028
1029 if (!printed_version++)
1030 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1031
1032 /* acquire resources */
1033 rc = pcim_enable_device(pdev);
1034 if (rc)
1035 return rc;
1036
1037 rc = pcim_iomap_regions(pdev,
1038 (1 << SIL24_HOST_BAR) | (1 << SIL24_PORT_BAR),
1039 DRV_NAME);
1040 if (rc)
1041 return rc;
1042 iomap = pcim_iomap_table(pdev);
1043
1044 /* apply workaround for completion IRQ loss on PCI-X errata */
1045 if (pi.flags & SIL24_FLAG_PCIX_IRQ_WOC) {
1046 tmp = readl(iomap[SIL24_HOST_BAR] + HOST_CTRL);
1047 if (tmp & (HOST_CTRL_TRDY | HOST_CTRL_STOP | HOST_CTRL_DEVSEL))
1048 dev_printk(KERN_INFO, &pdev->dev,
1049 "Applying completion IRQ loss on PCI-X "
1050 "errata fix\n");
1051 else
1052 pi.flags &= ~SIL24_FLAG_PCIX_IRQ_WOC;
1053 }
1054
1055 /* allocate and fill host */
1056 host = ata_host_alloc_pinfo(&pdev->dev, ppi,
1057 SIL24_FLAG2NPORTS(ppi[0]->flags));
1058 if (!host)
1059 return -ENOMEM;
1060 host->iomap = iomap;
1061
1062 for (i = 0; i < host->n_ports; i++) {
1063 void __iomem *port = iomap[SIL24_PORT_BAR] + i * PORT_REGS_SIZE;
1064
1065 host->ports[i]->ioaddr.cmd_addr = port;
1066 host->ports[i]->ioaddr.scr_addr = port + PORT_SCONTROL;
1067
1068 ata_std_ports(&host->ports[i]->ioaddr);
1069 }
1070
1071 /* configure and activate the device */
1072 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1073 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1074 if (rc) {
1075 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1076 if (rc) {
1077 dev_printk(KERN_ERR, &pdev->dev,
1078 "64-bit DMA enable failed\n");
1079 return rc;
1080 }
1081 }
1082 } else {
1083 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1084 if (rc) {
1085 dev_printk(KERN_ERR, &pdev->dev,
1086 "32-bit DMA enable failed\n");
1087 return rc;
1088 }
1089 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1090 if (rc) {
1091 dev_printk(KERN_ERR, &pdev->dev,
1092 "32-bit consistent DMA enable failed\n");
1093 return rc;
1094 }
1095 }
1096
1097 sil24_init_controller(host);
1098
1099 pci_set_master(pdev);
1100 return ata_host_activate(host, pdev->irq, sil24_interrupt, IRQF_SHARED,
1101 &sil24_sht);
1102 }
1103
1104 #ifdef CONFIG_PM
1105 static int sil24_pci_device_resume(struct pci_dev *pdev)
1106 {
1107 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1108 void __iomem *host_base = host->iomap[SIL24_HOST_BAR];
1109 int rc;
1110
1111 rc = ata_pci_device_do_resume(pdev);
1112 if (rc)
1113 return rc;
1114
1115 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND)
1116 writel(HOST_CTRL_GLOBAL_RST, host_base + HOST_CTRL);
1117
1118 sil24_init_controller(host);
1119
1120 ata_host_resume(host);
1121
1122 return 0;
1123 }
1124 #endif
1125
1126 static int __init sil24_init(void)
1127 {
1128 return pci_register_driver(&sil24_pci_driver);
1129 }
1130
1131 static void __exit sil24_exit(void)
1132 {
1133 pci_unregister_driver(&sil24_pci_driver);
1134 }
1135
1136 MODULE_AUTHOR("Tejun Heo");
1137 MODULE_DESCRIPTION("Silicon Image 3124/3132 SATA low-level driver");
1138 MODULE_LICENSE("GPL");
1139 MODULE_DEVICE_TABLE(pci, sil24_pci_tbl);
1140
1141 module_init(sil24_init);
1142 module_exit(sil24_exit);
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