fs: use kmem_cache_zalloc instead
[pv_ops_mirror.git] / drivers / edac / i82875p_edac.c
blob031abadc439a37c407d213fd1091b8e9a03b745e
1 /*
2 * Intel D82875P Memory Controller kernel module
3 * (C) 2003 Linux Networx (http://lnxi.com)
4 * This file may be distributed under the terms of the
5 * GNU General Public License.
7 * Written by Thayne Harbaugh
8 * Contributors:
9 * Wang Zhenyu at intel.com
11 * $Id: edac_i82875p.c,v 1.5.2.11 2005/10/05 00:43:44 dsp_llnl Exp $
13 * Note: E7210 appears same as D82875P - zhenyu.z.wang at intel.com
16 #include <linux/module.h>
17 #include <linux/init.h>
18 #include <linux/pci.h>
19 #include <linux/pci_ids.h>
20 #include <linux/slab.h>
21 #include "edac_core.h"
23 #define I82875P_REVISION " Ver: 2.0.2 " __DATE__
24 #define EDAC_MOD_STR "i82875p_edac"
26 #define i82875p_printk(level, fmt, arg...) \
27 edac_printk(level, "i82875p", fmt, ##arg)
29 #define i82875p_mc_printk(mci, level, fmt, arg...) \
30 edac_mc_chipset_printk(mci, level, "i82875p", fmt, ##arg)
32 #ifndef PCI_DEVICE_ID_INTEL_82875_0
33 #define PCI_DEVICE_ID_INTEL_82875_0 0x2578
34 #endif /* PCI_DEVICE_ID_INTEL_82875_0 */
36 #ifndef PCI_DEVICE_ID_INTEL_82875_6
37 #define PCI_DEVICE_ID_INTEL_82875_6 0x257e
38 #endif /* PCI_DEVICE_ID_INTEL_82875_6 */
40 /* four csrows in dual channel, eight in single channel */
41 #define I82875P_NR_CSROWS(nr_chans) (8/(nr_chans))
43 /* Intel 82875p register addresses - device 0 function 0 - DRAM Controller */
44 #define I82875P_EAP 0x58 /* Error Address Pointer (32b)
46 * 31:12 block address
47 * 11:0 reserved
50 #define I82875P_DERRSYN 0x5c /* DRAM Error Syndrome (8b)
52 * 7:0 DRAM ECC Syndrome
55 #define I82875P_DES 0x5d /* DRAM Error Status (8b)
57 * 7:1 reserved
58 * 0 Error channel 0/1
61 #define I82875P_ERRSTS 0xc8 /* Error Status Register (16b)
63 * 15:10 reserved
64 * 9 non-DRAM lock error (ndlock)
65 * 8 Sftwr Generated SMI
66 * 7 ECC UE
67 * 6 reserved
68 * 5 MCH detects unimplemented cycle
69 * 4 AGP access outside GA
70 * 3 Invalid AGP access
71 * 2 Invalid GA translation table
72 * 1 Unsupported AGP command
73 * 0 ECC CE
76 #define I82875P_ERRCMD 0xca /* Error Command (16b)
78 * 15:10 reserved
79 * 9 SERR on non-DRAM lock
80 * 8 SERR on ECC UE
81 * 7 SERR on ECC CE
82 * 6 target abort on high exception
83 * 5 detect unimplemented cyc
84 * 4 AGP access outside of GA
85 * 3 SERR on invalid AGP access
86 * 2 invalid translation table
87 * 1 SERR on unsupported AGP command
88 * 0 reserved
91 /* Intel 82875p register addresses - device 6 function 0 - DRAM Controller */
92 #define I82875P_PCICMD6 0x04 /* PCI Command Register (16b)
94 * 15:10 reserved
95 * 9 fast back-to-back - ro 0
96 * 8 SERR enable - ro 0
97 * 7 addr/data stepping - ro 0
98 * 6 parity err enable - ro 0
99 * 5 VGA palette snoop - ro 0
100 * 4 mem wr & invalidate - ro 0
101 * 3 special cycle - ro 0
102 * 2 bus master - ro 0
103 * 1 mem access dev6 - 0(dis),1(en)
104 * 0 IO access dev3 - 0(dis),1(en)
107 #define I82875P_BAR6 0x10 /* Mem Delays Base ADDR Reg (32b)
109 * 31:12 mem base addr [31:12]
110 * 11:4 address mask - ro 0
111 * 3 prefetchable - ro 0(non),1(pre)
112 * 2:1 mem type - ro 0
113 * 0 mem space - ro 0
116 /* Intel 82875p MMIO register space - device 0 function 0 - MMR space */
118 #define I82875P_DRB_SHIFT 26 /* 64MiB grain */
119 #define I82875P_DRB 0x00 /* DRAM Row Boundary (8b x 8)
121 * 7 reserved
122 * 6:0 64MiB row boundary addr
125 #define I82875P_DRA 0x10 /* DRAM Row Attribute (4b x 8)
127 * 7 reserved
128 * 6:4 row attr row 1
129 * 3 reserved
130 * 2:0 row attr row 0
132 * 000 = 4KiB
133 * 001 = 8KiB
134 * 010 = 16KiB
135 * 011 = 32KiB
138 #define I82875P_DRC 0x68 /* DRAM Controller Mode (32b)
140 * 31:30 reserved
141 * 29 init complete
142 * 28:23 reserved
143 * 22:21 nr chan 00=1,01=2
144 * 20 reserved
145 * 19:18 Data Integ Mode 00=none,01=ecc
146 * 17:11 reserved
147 * 10:8 refresh mode
148 * 7 reserved
149 * 6:4 mode select
150 * 3:2 reserved
151 * 1:0 DRAM type 01=DDR
154 enum i82875p_chips {
155 I82875P = 0,
158 struct i82875p_pvt {
159 struct pci_dev *ovrfl_pdev;
160 void __iomem *ovrfl_window;
163 struct i82875p_dev_info {
164 const char *ctl_name;
167 struct i82875p_error_info {
168 u16 errsts;
169 u32 eap;
170 u8 des;
171 u8 derrsyn;
172 u16 errsts2;
175 static const struct i82875p_dev_info i82875p_devs[] = {
176 [I82875P] = {
177 .ctl_name = "i82875p"},
180 static struct pci_dev *mci_pdev; /* init dev: in case that AGP code has
181 * already registered driver
184 static int i82875p_registered = 1;
186 static struct edac_pci_ctl_info *i82875p_pci;
188 static void i82875p_get_error_info(struct mem_ctl_info *mci,
189 struct i82875p_error_info *info)
191 struct pci_dev *pdev;
193 pdev = to_pci_dev(mci->dev);
196 * This is a mess because there is no atomic way to read all the
197 * registers at once and the registers can transition from CE being
198 * overwritten by UE.
200 pci_read_config_word(pdev, I82875P_ERRSTS, &info->errsts);
202 if (!(info->errsts & 0x0081))
203 return;
205 pci_read_config_dword(pdev, I82875P_EAP, &info->eap);
206 pci_read_config_byte(pdev, I82875P_DES, &info->des);
207 pci_read_config_byte(pdev, I82875P_DERRSYN, &info->derrsyn);
208 pci_read_config_word(pdev, I82875P_ERRSTS, &info->errsts2);
211 * If the error is the same then we can for both reads then
212 * the first set of reads is valid. If there is a change then
213 * there is a CE no info and the second set of reads is valid
214 * and should be UE info.
216 if ((info->errsts ^ info->errsts2) & 0x0081) {
217 pci_read_config_dword(pdev, I82875P_EAP, &info->eap);
218 pci_read_config_byte(pdev, I82875P_DES, &info->des);
219 pci_read_config_byte(pdev, I82875P_DERRSYN, &info->derrsyn);
222 pci_write_bits16(pdev, I82875P_ERRSTS, 0x0081, 0x0081);
225 static int i82875p_process_error_info(struct mem_ctl_info *mci,
226 struct i82875p_error_info *info,
227 int handle_errors)
229 int row, multi_chan;
231 multi_chan = mci->csrows[0].nr_channels - 1;
233 if (!(info->errsts & 0x0081))
234 return 0;
236 if (!handle_errors)
237 return 1;
239 if ((info->errsts ^ info->errsts2) & 0x0081) {
240 edac_mc_handle_ce_no_info(mci, "UE overwrote CE");
241 info->errsts = info->errsts2;
244 info->eap >>= PAGE_SHIFT;
245 row = edac_mc_find_csrow_by_page(mci, info->eap);
247 if (info->errsts & 0x0080)
248 edac_mc_handle_ue(mci, info->eap, 0, row, "i82875p UE");
249 else
250 edac_mc_handle_ce(mci, info->eap, 0, info->derrsyn, row,
251 multi_chan ? (info->des & 0x1) : 0,
252 "i82875p CE");
254 return 1;
257 static void i82875p_check(struct mem_ctl_info *mci)
259 struct i82875p_error_info info;
261 debugf1("MC%d: %s()\n", mci->mc_idx, __func__);
262 i82875p_get_error_info(mci, &info);
263 i82875p_process_error_info(mci, &info, 1);
266 /* Return 0 on success or 1 on failure. */
267 static int i82875p_setup_overfl_dev(struct pci_dev *pdev,
268 struct pci_dev **ovrfl_pdev,
269 void __iomem **ovrfl_window)
271 struct pci_dev *dev;
272 void __iomem *window;
273 int err;
275 *ovrfl_pdev = NULL;
276 *ovrfl_window = NULL;
277 dev = pci_get_device(PCI_VEND_DEV(INTEL, 82875_6), NULL);
279 if (dev == NULL) {
280 /* Intel tells BIOS developers to hide device 6 which
281 * configures the overflow device access containing
282 * the DRBs - this is where we expose device 6.
283 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
285 pci_write_bits8(pdev, 0xf4, 0x2, 0x2);
286 dev = pci_scan_single_device(pdev->bus, PCI_DEVFN(6, 0));
288 if (dev == NULL)
289 return 1;
291 err = pci_bus_add_device(dev);
292 if (err) {
293 i82875p_printk(KERN_ERR,
294 "%s(): pci_bus_add_device() Failed\n",
295 __func__);
299 *ovrfl_pdev = dev;
301 if (pci_enable_device(dev)) {
302 i82875p_printk(KERN_ERR, "%s(): Failed to enable overflow "
303 "device\n", __func__);
304 return 1;
307 if (pci_request_regions(dev, pci_name(dev))) {
308 #ifdef CORRECT_BIOS
309 goto fail0;
310 #endif
313 /* cache is irrelevant for PCI bus reads/writes */
314 window = ioremap_nocache(pci_resource_start(dev, 0),
315 pci_resource_len(dev, 0));
317 if (window == NULL) {
318 i82875p_printk(KERN_ERR, "%s(): Failed to ioremap bar6\n",
319 __func__);
320 goto fail1;
323 *ovrfl_window = window;
324 return 0;
326 fail1:
327 pci_release_regions(dev);
329 #ifdef CORRECT_BIOS
330 fail0:
331 pci_disable_device(dev);
332 #endif
333 /* NOTE: the ovrfl proc entry and pci_dev are intentionally left */
334 return 1;
337 /* Return 1 if dual channel mode is active. Else return 0. */
338 static inline int dual_channel_active(u32 drc)
340 return (drc >> 21) & 0x1;
343 static void i82875p_init_csrows(struct mem_ctl_info *mci,
344 struct pci_dev *pdev,
345 void __iomem * ovrfl_window, u32 drc)
347 struct csrow_info *csrow;
348 unsigned long last_cumul_size;
349 u8 value;
350 u32 drc_ddim; /* DRAM Data Integrity Mode 0=none,2=edac */
351 u32 cumul_size;
352 int index;
354 drc_ddim = (drc >> 18) & 0x1;
355 last_cumul_size = 0;
357 /* The dram row boundary (DRB) reg values are boundary address
358 * for each DRAM row with a granularity of 32 or 64MB (single/dual
359 * channel operation). DRB regs are cumulative; therefore DRB7 will
360 * contain the total memory contained in all eight rows.
363 for (index = 0; index < mci->nr_csrows; index++) {
364 csrow = &mci->csrows[index];
366 value = readb(ovrfl_window + I82875P_DRB + index);
367 cumul_size = value << (I82875P_DRB_SHIFT - PAGE_SHIFT);
368 debugf3("%s(): (%d) cumul_size 0x%x\n", __func__, index,
369 cumul_size);
370 if (cumul_size == last_cumul_size)
371 continue; /* not populated */
373 csrow->first_page = last_cumul_size;
374 csrow->last_page = cumul_size - 1;
375 csrow->nr_pages = cumul_size - last_cumul_size;
376 last_cumul_size = cumul_size;
377 csrow->grain = 1 << 12; /* I82875P_EAP has 4KiB reolution */
378 csrow->mtype = MEM_DDR;
379 csrow->dtype = DEV_UNKNOWN;
380 csrow->edac_mode = drc_ddim ? EDAC_SECDED : EDAC_NONE;
384 static int i82875p_probe1(struct pci_dev *pdev, int dev_idx)
386 int rc = -ENODEV;
387 struct mem_ctl_info *mci;
388 struct i82875p_pvt *pvt;
389 struct pci_dev *ovrfl_pdev;
390 void __iomem *ovrfl_window;
391 u32 drc;
392 u32 nr_chans;
393 struct i82875p_error_info discard;
395 debugf0("%s()\n", __func__);
396 ovrfl_pdev = pci_get_device(PCI_VEND_DEV(INTEL, 82875_6), NULL);
398 if (i82875p_setup_overfl_dev(pdev, &ovrfl_pdev, &ovrfl_window))
399 return -ENODEV;
400 drc = readl(ovrfl_window + I82875P_DRC);
401 nr_chans = dual_channel_active(drc) + 1;
402 mci = edac_mc_alloc(sizeof(*pvt), I82875P_NR_CSROWS(nr_chans),
403 nr_chans, 0);
405 if (!mci) {
406 rc = -ENOMEM;
407 goto fail0;
410 debugf3("%s(): init mci\n", __func__);
411 mci->dev = &pdev->dev;
412 mci->mtype_cap = MEM_FLAG_DDR;
413 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
414 mci->edac_cap = EDAC_FLAG_UNKNOWN;
415 mci->mod_name = EDAC_MOD_STR;
416 mci->mod_ver = I82875P_REVISION;
417 mci->ctl_name = i82875p_devs[dev_idx].ctl_name;
418 mci->dev_name = pci_name(pdev);
419 mci->edac_check = i82875p_check;
420 mci->ctl_page_to_phys = NULL;
421 debugf3("%s(): init pvt\n", __func__);
422 pvt = (struct i82875p_pvt *)mci->pvt_info;
423 pvt->ovrfl_pdev = ovrfl_pdev;
424 pvt->ovrfl_window = ovrfl_window;
425 i82875p_init_csrows(mci, pdev, ovrfl_window, drc);
426 i82875p_get_error_info(mci, &discard); /* clear counters */
428 /* Here we assume that we will never see multiple instances of this
429 * type of memory controller. The ID is therefore hardcoded to 0.
431 if (edac_mc_add_mc(mci)) {
432 debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
433 goto fail1;
436 /* allocating generic PCI control info */
437 i82875p_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
438 if (!i82875p_pci) {
439 printk(KERN_WARNING
440 "%s(): Unable to create PCI control\n",
441 __func__);
442 printk(KERN_WARNING
443 "%s(): PCI error report via EDAC not setup\n",
444 __func__);
447 /* get this far and it's successful */
448 debugf3("%s(): success\n", __func__);
449 return 0;
451 fail1:
452 edac_mc_free(mci);
454 fail0:
455 iounmap(ovrfl_window);
456 pci_release_regions(ovrfl_pdev);
458 pci_disable_device(ovrfl_pdev);
459 /* NOTE: the ovrfl proc entry and pci_dev are intentionally left */
460 return rc;
463 /* returns count (>= 0), or negative on error */
464 static int __devinit i82875p_init_one(struct pci_dev *pdev,
465 const struct pci_device_id *ent)
467 int rc;
469 debugf0("%s()\n", __func__);
470 i82875p_printk(KERN_INFO, "i82875p init one\n");
472 if (pci_enable_device(pdev) < 0)
473 return -EIO;
475 rc = i82875p_probe1(pdev, ent->driver_data);
477 if (mci_pdev == NULL)
478 mci_pdev = pci_dev_get(pdev);
480 return rc;
483 static void __devexit i82875p_remove_one(struct pci_dev *pdev)
485 struct mem_ctl_info *mci;
486 struct i82875p_pvt *pvt = NULL;
488 debugf0("%s()\n", __func__);
490 if (i82875p_pci)
491 edac_pci_release_generic_ctl(i82875p_pci);
493 if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
494 return;
496 pvt = (struct i82875p_pvt *)mci->pvt_info;
498 if (pvt->ovrfl_window)
499 iounmap(pvt->ovrfl_window);
501 if (pvt->ovrfl_pdev) {
502 #ifdef CORRECT_BIOS
503 pci_release_regions(pvt->ovrfl_pdev);
504 #endif /*CORRECT_BIOS */
505 pci_disable_device(pvt->ovrfl_pdev);
506 pci_dev_put(pvt->ovrfl_pdev);
509 edac_mc_free(mci);
512 static const struct pci_device_id i82875p_pci_tbl[] __devinitdata = {
514 PCI_VEND_DEV(INTEL, 82875_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
515 I82875P},
518 } /* 0 terminated list. */
521 MODULE_DEVICE_TABLE(pci, i82875p_pci_tbl);
523 static struct pci_driver i82875p_driver = {
524 .name = EDAC_MOD_STR,
525 .probe = i82875p_init_one,
526 .remove = __devexit_p(i82875p_remove_one),
527 .id_table = i82875p_pci_tbl,
530 static int __init i82875p_init(void)
532 int pci_rc;
534 debugf3("%s()\n", __func__);
535 pci_rc = pci_register_driver(&i82875p_driver);
537 if (pci_rc < 0)
538 goto fail0;
540 if (mci_pdev == NULL) {
541 mci_pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
542 PCI_DEVICE_ID_INTEL_82875_0, NULL);
544 if (!mci_pdev) {
545 debugf0("875p pci_get_device fail\n");
546 pci_rc = -ENODEV;
547 goto fail1;
550 pci_rc = i82875p_init_one(mci_pdev, i82875p_pci_tbl);
552 if (pci_rc < 0) {
553 debugf0("875p init fail\n");
554 pci_rc = -ENODEV;
555 goto fail1;
559 return 0;
561 fail1:
562 pci_unregister_driver(&i82875p_driver);
564 fail0:
565 if (mci_pdev != NULL)
566 pci_dev_put(mci_pdev);
568 return pci_rc;
571 static void __exit i82875p_exit(void)
573 debugf3("%s()\n", __func__);
575 pci_unregister_driver(&i82875p_driver);
577 if (!i82875p_registered) {
578 i82875p_remove_one(mci_pdev);
579 pci_dev_put(mci_pdev);
583 module_init(i82875p_init);
584 module_exit(i82875p_exit);
586 MODULE_LICENSE("GPL");
587 MODULE_AUTHOR("Linux Networx (http://lnxi.com) Thayne Harbaugh");
588 MODULE_DESCRIPTION("MC support for Intel 82875 memory hub controllers");