drivers/net/irda/via-ircc.h

   1 /*********************************************************************
   2  *
   3  * Filename:      via-ircc.h
   4  * Version:       1.0
   5  * Description:   Driver for the VIA VT8231/VT8233 IrDA chipsets
   6  * Author:        VIA Technologies, inc
   7  * Date  :        08/06/2003
   8
   9 Copyright (c) 1998-2003 VIA Technologies, Inc.
  10
  11 This program is free software; you can redistribute it and/or modify it under
  12 the terms of the GNU General Public License as published by the Free Software
  13 Foundation; either version 2, or (at your option) any later version.
  14
  15 This program is distributed in the hope that it will be useful, but WITHOUT
  16 ANY WARRANTIES OR REPRESENTATIONS; without even the implied warranty of
  17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
  18 See the GNU General Public License for more details.
  19
  20 You should have received a copy of the GNU General Public License along with
  21 this program; if not, write to the Free Software Foundation, Inc.,
  22 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  23
  24  * Comment:
  25  * jul/08/2002 : Rx buffer length should use Rx ring ptr.
  26  * Oct/28/2002 : Add SB id for 3147 and 3177.
  27  * jul/09/2002 : only implement two kind of dongle currently.
  28  * Oct/02/2002 : work on VT8231 and VT8233 .
  29  * Aug/06/2003 : change driver format to pci driver .
  30  ********************************************************************/
  31 #ifndef via_IRCC_H
  32 #define via_IRCC_H
  33 #include <linux/time.h>
  34 #include <linux/spinlock.h>
  35 #include <linux/pm.h>
  36 #include <linux/types.h>
  37 #include <asm/io.h>
  38
  39 #define MAX_TX_WINDOW 7
  40 #define MAX_RX_WINDOW 7
  41
  42 struct st_fifo_entry {
  43         int status;
  44         int len;
  45 };
  46
  47 struct st_fifo {
  48         struct st_fifo_entry entries[MAX_RX_WINDOW + 2];
  49         int pending_bytes;
  50         int head;
  51         int tail;
  52         int len;
  53 };
  54
  55 struct frame_cb {
  56         void *start;            /* Start of frame in DMA mem */
  57         int len;                /* Lenght of frame in DMA mem */
  58 };
  59
  60 struct tx_fifo {
  61         struct frame_cb queue[MAX_TX_WINDOW + 2];       /* Info about frames in queue */
  62         int ptr;                /* Currently being sent */
  63         int len;                /* Lenght of queue */
  64         int free;               /* Next free slot */
  65         void *tail;             /* Next free start in DMA mem */
  66 };
  67
  68
  69 struct eventflag                // for keeping track of Interrupt Events
  70 {
  71         //--------tx part
  72         unsigned char TxFIFOUnderRun;
  73         unsigned char EOMessage;
  74         unsigned char TxFIFOReady;
  75         unsigned char EarlyEOM;
  76         //--------rx part
  77         unsigned char PHYErr;
  78         unsigned char CRCErr;
  79         unsigned char RxFIFOOverRun;
  80         unsigned char EOPacket;
  81         unsigned char RxAvail;
  82         unsigned char TooLargePacket;
  83         unsigned char SIRBad;
  84         //--------unknown
  85         unsigned char Unknown;
  86         //----------
  87         unsigned char TimeOut;
  88         unsigned char RxDMATC;
  89         unsigned char TxDMATC;
  90 };
  91
  92 /* Private data for each instance */
  93 struct via_ircc_cb {
  94         struct st_fifo st_fifo; /* Info about received frames */
  95         struct tx_fifo tx_fifo; /* Info about frames to be transmitted */
  96
  97         struct net_device *netdev;      /* Yes! we are some kind of netdevice */
  98         struct net_device_stats stats;
  99
 100         struct irlap_cb *irlap; /* The link layer we are binded to */
 101         struct qos_info qos;    /* QoS capabilities for this device */
 102
 103         chipio_t io;            /* IrDA controller information */
 104         iobuff_t tx_buff;       /* Transmit buffer */
 105         iobuff_t rx_buff;       /* Receive buffer */
 106         dma_addr_t tx_buff_dma;
 107         dma_addr_t rx_buff_dma;
 108
 109         __u8 ier;               /* Interrupt enable register */
 110
 111         struct timeval stamp;
 112         struct timeval now;
 113
 114         spinlock_t lock;        /* For serializing operations */
 115
 116         __u32 flags;            /* Interface flags */
 117         __u32 new_speed;
 118         int index;              /* Instance index */
 119
 120         struct eventflag EventFlag;
 121         struct pm_dev *dev;
 122         unsigned int chip_id;   /* to remember chip id */
 123         unsigned int RetryCount;
 124         unsigned int RxDataReady;
 125         unsigned int RxLastCount;
 126 };
 127
 128
 129 //---------I=Infrared,  H=Host, M=Misc, T=Tx, R=Rx, ST=Status,
 130 //         CF=Config, CT=Control, L=Low, H=High, C=Count
 131 #define  I_CF_L_0               0x10
 132 #define  I_CF_H_0               0x11
 133 #define  I_SIR_BOF              0x12
 134 #define  I_SIR_EOF              0x13
 135 #define  I_ST_CT_0              0x15
 136 #define  I_ST_L_1               0x16
 137 #define  I_ST_H_1               0x17
 138 #define  I_CF_L_1               0x18
 139 #define  I_CF_H_1               0x19
 140 #define  I_CF_L_2               0x1a
 141 #define  I_CF_H_2               0x1b
 142 #define  I_CF_3         0x1e
 143 #define  H_CT                   0x20
 144 #define  H_ST                   0x21
 145 #define  M_CT                   0x22
 146 #define  TX_CT_1                0x23
 147 #define  TX_CT_2                0x24
 148 #define  TX_ST                  0x25
 149 #define  RX_CT                  0x26
 150 #define  RX_ST                  0x27
 151 #define  RESET                  0x28
 152 #define  P_ADDR         0x29
 153 #define  RX_C_L         0x2a
 154 #define  RX_C_H         0x2b
 155 #define  RX_P_L         0x2c
 156 #define  RX_P_H         0x2d
 157 #define  TX_C_L         0x2e
 158 #define  TX_C_H         0x2f
 159 #define  TIMER          0x32
 160 #define  I_CF_4                 0x33
 161 #define  I_T_C_L                0x34
 162 #define  I_T_C_H                0x35
 163 #define  VERSION                0x3f
 164 //-------------------------------
 165 #define StartAddr       0x10    // the first register address
 166 #define EndAddr         0x3f    // the last register address
 167 #define GetBit(val,bit)  val = (unsigned char) ((val>>bit) & 0x1)
 168                         // Returns the bit
 169 #define SetBit(val,bit)  val= (unsigned char ) (val | (0x1 << bit))
 170                         // Sets bit to 1
 171 #define ResetBit(val,bit) val= (unsigned char ) (val & ~(0x1 << bit))
 172                         // Sets bit to 0
 173
 174 #define OFF   0
 175 #define ON   1
 176 #define DMA_TX_MODE   0x08
 177 #define DMA_RX_MODE   0x04
 178
 179 #define DMA1   0
 180 #define DMA2   0xc0
 181 #define MASK1   DMA1+0x0a
 182 #define MASK2   DMA2+0x14
 183
 184 #define Clk_bit 0x40
 185 #define Tx_bit 0x01
 186 #define Rd_Valid 0x08
 187 #define RxBit 0x08
 188
 189 static void DisableDmaChannel(unsigned int channel)
 190 {
 191         switch (channel) {      // 8 Bit DMA channels DMAC1
 192         case 0:
 193                 outb(4, MASK1); //mask channel 0
 194                 break;
 195         case 1:
 196                 outb(5, MASK1); //Mask channel 1
 197                 break;
 198         case 2:
 199                 outb(6, MASK1); //Mask channel 2
 200                 break;
 201         case 3:
 202                 outb(7, MASK1); //Mask channel 3
 203                 break;
 204         case 5:
 205                 outb(5, MASK2); //Mask channel 5
 206                 break;
 207         case 6:
 208                 outb(6, MASK2); //Mask channel 6
 209                 break;
 210         case 7:
 211                 outb(7, MASK2); //Mask channel 7
 212                 break;
 213         default:
 214                 break;
 215         };                      //Switch
 216 }
 217
 218 static unsigned char ReadLPCReg(int iRegNum)
 219 {
 220         unsigned char iVal;
 221
 222         outb(0x87, 0x2e);
 223         outb(0x87, 0x2e);
 224         outb(iRegNum, 0x2e);
 225         iVal = inb(0x2f);
 226         outb(0xaa, 0x2e);
 227
 228         return iVal;
 229 }
 230
 231 static void WriteLPCReg(int iRegNum, unsigned char iVal)
 232 {
 233
 234         outb(0x87, 0x2e);
 235         outb(0x87, 0x2e);
 236         outb(iRegNum, 0x2e);
 237         outb(iVal, 0x2f);
 238         outb(0xAA, 0x2e);
 239 }
 240
 241 static __u8 ReadReg(unsigned int BaseAddr, int iRegNum)
 242 {
 243         return ((__u8) inb(BaseAddr + iRegNum));
 244 }
 245
 246 static void WriteReg(unsigned int BaseAddr, int iRegNum, unsigned char iVal)
 247 {
 248         outb(iVal, BaseAddr + iRegNum);
 249 }
 250
 251 static int WriteRegBit(unsigned int BaseAddr, unsigned char RegNum,
 252                 unsigned char BitPos, unsigned char value)
 253 {
 254         __u8 Rtemp, Wtemp;
 255
 256         if (BitPos > 7) {
 257                 return -1;
 258         }
 259         if ((RegNum < StartAddr) || (RegNum > EndAddr))
 260                 return -1;
 261         Rtemp = ReadReg(BaseAddr, RegNum);
 262         if (value == 0)
 263                 Wtemp = ResetBit(Rtemp, BitPos);
 264         else {
 265                 if (value == 1)
 266                         Wtemp = SetBit(Rtemp, BitPos);
 267                 else
 268                         return -1;
 269         }
 270         WriteReg(BaseAddr, RegNum, Wtemp);
 271         return 0;
 272 }
 273
 274 static __u8 CheckRegBit(unsigned int BaseAddr, unsigned char RegNum,
 275                  unsigned char BitPos)
 276 {
 277         __u8 temp;
 278
 279         if (BitPos > 7)
 280                 return 0xff;
 281         if ((RegNum < StartAddr) || (RegNum > EndAddr)) {
 282 //     printf("what is the register %x!\n",RegNum);
 283         }
 284         temp = ReadReg(BaseAddr, RegNum);
 285         return GetBit(temp, BitPos);
 286 }
 287
 288 static void SetMaxRxPacketSize(__u16 iobase, __u16 size)
 289 {
 290         __u16 low, high;
 291         if ((size & 0xe000) == 0) {
 292                 low = size & 0x00ff;
 293                 high = (size & 0x1f00) >> 8;
 294                 WriteReg(iobase, I_CF_L_2, low);
 295                 WriteReg(iobase, I_CF_H_2, high);
 296
 297         }
 298
 299 }
 300
 301 //for both Rx and Tx
 302
 303 static void SetFIFO(__u16 iobase, __u16 value)
 304 {
 305         switch (value) {
 306         case 128:
 307                 WriteRegBit(iobase, 0x11, 0, 0);
 308                 WriteRegBit(iobase, 0x11, 7, 1);
 309                 break;
 310         case 64:
 311                 WriteRegBit(iobase, 0x11, 0, 0);
 312                 WriteRegBit(iobase, 0x11, 7, 0);
 313                 break;
 314         case 32:
 315                 WriteRegBit(iobase, 0x11, 0, 1);
 316                 WriteRegBit(iobase, 0x11, 7, 0);
 317                 break;
 318         default:
 319                 WriteRegBit(iobase, 0x11, 0, 0);
 320                 WriteRegBit(iobase, 0x11, 7, 0);
 321         }
 322
 323 }
 324
 325 #define CRC16(BaseAddr,val)         WriteRegBit(BaseAddr,I_CF_L_0,7,val)        //0 for 32 CRC
 326 /*
 327 #define SetVFIR(BaseAddr,val)       WriteRegBit(BaseAddr,I_CF_H_0,5,val)
 328 #define SetFIR(BaseAddr,val)        WriteRegBit(BaseAddr,I_CF_L_0,6,val)
 329 #define SetMIR(BaseAddr,val)        WriteRegBit(BaseAddr,I_CF_L_0,5,val)
 330 #define SetSIR(BaseAddr,val)        WriteRegBit(BaseAddr,I_CF_L_0,4,val)
 331 */
 332 #define SIRFilter(BaseAddr,val)     WriteRegBit(BaseAddr,I_CF_L_0,3,val)
 333 #define Filter(BaseAddr,val)        WriteRegBit(BaseAddr,I_CF_L_0,2,val)
 334 #define InvertTX(BaseAddr,val)      WriteRegBit(BaseAddr,I_CF_L_0,1,val)
 335 #define InvertRX(BaseAddr,val)      WriteRegBit(BaseAddr,I_CF_L_0,0,val)
 336 //****************************I_CF_H_0
 337 #define EnableTX(BaseAddr,val)      WriteRegBit(BaseAddr,I_CF_H_0,4,val)
 338 #define EnableRX(BaseAddr,val)      WriteRegBit(BaseAddr,I_CF_H_0,3,val)
 339 #define EnableDMA(BaseAddr,val)     WriteRegBit(BaseAddr,I_CF_H_0,2,val)
 340 #define SIRRecvAny(BaseAddr,val)    WriteRegBit(BaseAddr,I_CF_H_0,1,val)
 341 #define DiableTrans(BaseAddr,val)   WriteRegBit(BaseAddr,I_CF_H_0,0,val)
 342 //***************************I_SIR_BOF,I_SIR_EOF
 343 #define SetSIRBOF(BaseAddr,val)     WriteReg(BaseAddr,I_SIR_BOF,val)
 344 #define SetSIREOF(BaseAddr,val)     WriteReg(BaseAddr,I_SIR_EOF,val)
 345 #define GetSIRBOF(BaseAddr)        ReadReg(BaseAddr,I_SIR_BOF)
 346 #define GetSIREOF(BaseAddr)        ReadReg(BaseAddr,I_SIR_EOF)
 347 //*******************I_ST_CT_0
 348 #define EnPhys(BaseAddr,val)   WriteRegBit(BaseAddr,I_ST_CT_0,7,val)
 349 #define IsModeError(BaseAddr) CheckRegBit(BaseAddr,I_ST_CT_0,6) //RO
 350 #define IsVFIROn(BaseAddr)     CheckRegBit(BaseAddr,0x14,0)     //RO for VT1211 only
 351 #define IsFIROn(BaseAddr)     CheckRegBit(BaseAddr,I_ST_CT_0,5) //RO
 352 #define IsMIROn(BaseAddr)     CheckRegBit(BaseAddr,I_ST_CT_0,4) //RO
 353 #define IsSIROn(BaseAddr)     CheckRegBit(BaseAddr,I_ST_CT_0,3) //RO
 354 #define IsEnableTX(BaseAddr)  CheckRegBit(BaseAddr,I_ST_CT_0,2) //RO
 355 #define IsEnableRX(BaseAddr)  CheckRegBit(BaseAddr,I_ST_CT_0,1) //RO
 356 #define Is16CRC(BaseAddr)     CheckRegBit(BaseAddr,I_ST_CT_0,0) //RO
 357 //***************************I_CF_3
 358 #define DisableAdjacentPulseWidth(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_3,5,val)      //1 disable
 359 #define DisablePulseWidthAdjust(BaseAddr,val)   WriteRegBit(BaseAddr,I_CF_3,4,val)      //1 disable
 360 #define UseOneRX(BaseAddr,val)                  WriteRegBit(BaseAddr,I_CF_3,1,val)      //0 use two RX
 361 #define SlowIRRXLowActive(BaseAddr,val)         WriteRegBit(BaseAddr,I_CF_3,0,val)      //0 show RX high=1 in SIR
 362 //***************************H_CT
 363 #define EnAllInt(BaseAddr,val)   WriteRegBit(BaseAddr,H_CT,7,val)
 364 #define TXStart(BaseAddr,val)    WriteRegBit(BaseAddr,H_CT,6,val)
 365 #define RXStart(BaseAddr,val)    WriteRegBit(BaseAddr,H_CT,5,val)
 366 #define ClearRXInt(BaseAddr,val)   WriteRegBit(BaseAddr,H_CT,4,val)     // 1 clear
 367 //*****************H_ST
 368 #define IsRXInt(BaseAddr)           CheckRegBit(BaseAddr,H_ST,4)
 369 #define GetIntIndentify(BaseAddr)   ((ReadReg(BaseAddr,H_ST)&0xf1) >>1)
 370 #define IsHostBusy(BaseAddr)        CheckRegBit(BaseAddr,H_ST,0)
 371 #define GetHostStatus(BaseAddr)     ReadReg(BaseAddr,H_ST)      //RO
 372 //**************************M_CT
 373 #define EnTXDMA(BaseAddr,val)         WriteRegBit(BaseAddr,M_CT,7,val)
 374 #define EnRXDMA(BaseAddr,val)         WriteRegBit(BaseAddr,M_CT,6,val)
 375 #define SwapDMA(BaseAddr,val)         WriteRegBit(BaseAddr,M_CT,5,val)
 376 #define EnInternalLoop(BaseAddr,val)  WriteRegBit(BaseAddr,M_CT,4,val)
 377 #define EnExternalLoop(BaseAddr,val)  WriteRegBit(BaseAddr,M_CT,3,val)
 378 //**************************TX_CT_1
 379 #define EnTXFIFOHalfLevelInt(BaseAddr,val)   WriteRegBit(BaseAddr,TX_CT_1,4,val)        //half empty int (1 half)
 380 #define EnTXFIFOUnderrunEOMInt(BaseAddr,val) WriteRegBit(BaseAddr,TX_CT_1,5,val)
 381 #define EnTXFIFOReadyInt(BaseAddr,val)       WriteRegBit(BaseAddr,TX_CT_1,6,val)        //int when reach it threshold (setting by bit 4)
 382 //**************************TX_CT_2
 383 #define ForceUnderrun(BaseAddr,val)   WriteRegBit(BaseAddr,TX_CT_2,7,val)       // force an underrun int
 384 #define EnTXCRC(BaseAddr,val)         WriteRegBit(BaseAddr,TX_CT_2,6,val)       //1 for FIR,MIR...0 (not SIR)
 385 #define ForceBADCRC(BaseAddr,val)     WriteRegBit(BaseAddr,TX_CT_2,5,val)       //force an bad CRC
 386 #define SendSIP(BaseAddr,val)         WriteRegBit(BaseAddr,TX_CT_2,4,val)       //send indication pulse for prevent SIR disturb
 387 #define ClearEnTX(BaseAddr,val)       WriteRegBit(BaseAddr,TX_CT_2,3,val)       // opposite to EnTX
 388 //*****************TX_ST
 389 #define GetTXStatus(BaseAddr)   ReadReg(BaseAddr,TX_ST) //RO
 390 //**************************RX_CT
 391 #define EnRXSpecInt(BaseAddr,val)           WriteRegBit(BaseAddr,RX_CT,0,val)
 392 #define EnRXFIFOReadyInt(BaseAddr,val)      WriteRegBit(BaseAddr,RX_CT,1,val)   //enable int when reach it threshold (setting by bit 7)
 393 #define EnRXFIFOHalfLevelInt(BaseAddr,val)  WriteRegBit(BaseAddr,RX_CT,7,val)   //enable int when (1) half full...or (0) just not full
 394 //*****************RX_ST
 395 #define GetRXStatus(BaseAddr)   ReadReg(BaseAddr,RX_ST) //RO
 396 //***********************P_ADDR
 397 #define SetPacketAddr(BaseAddr,addr)        WriteReg(BaseAddr,P_ADDR,addr)
 398 //***********************I_CF_4
 399 #define EnGPIOtoRX2(BaseAddr,val)       WriteRegBit(BaseAddr,I_CF_4,7,val)
 400 #define EnTimerInt(BaseAddr,val)                WriteRegBit(BaseAddr,I_CF_4,1,val)
 401 #define ClearTimerInt(BaseAddr,val)     WriteRegBit(BaseAddr,I_CF_4,0,val)
 402 //***********************I_T_C_L
 403 #define WriteGIO(BaseAddr,val)      WriteRegBit(BaseAddr,I_T_C_L,7,val)
 404 #define ReadGIO(BaseAddr)                   CheckRegBit(BaseAddr,I_T_C_L,7)
 405 #define ReadRX(BaseAddr)                    CheckRegBit(BaseAddr,I_T_C_L,3)     //RO
 406 #define WriteTX(BaseAddr,val)           WriteRegBit(BaseAddr,I_T_C_L,0,val)
 407 //***********************I_T_C_H
 408 #define EnRX2(BaseAddr,val)                 WriteRegBit(BaseAddr,I_T_C_H,7,val)
 409 #define ReadRX2(BaseAddr)           CheckRegBit(BaseAddr,I_T_C_H,7)
 410 //**********************Version
 411 #define GetFIRVersion(BaseAddr)         ReadReg(BaseAddr,VERSION)
 412
 413
 414 static void SetTimer(__u16 iobase, __u8 count)
 415 {
 416         EnTimerInt(iobase, OFF);
 417         WriteReg(iobase, TIMER, count);
 418         EnTimerInt(iobase, ON);
 419 }
 420
 421
 422 static void SetSendByte(__u16 iobase, __u32 count)
 423 {
 424         __u32 low, high;
 425
 426         if ((count & 0xf000) == 0) {
 427                 low = count & 0x00ff;
 428                 high = (count & 0x0f00) >> 8;
 429                 WriteReg(iobase, TX_C_L, low);
 430                 WriteReg(iobase, TX_C_H, high);
 431         }
 432 }
 433
 434 static void ResetChip(__u16 iobase, __u8 type)
 435 {
 436         __u8 value;
 437
 438         value = (type + 2) << 4;
 439         WriteReg(iobase, RESET, type);
 440 }
 441
 442 static int CkRxRecv(__u16 iobase, struct via_ircc_cb *self)
 443 {
 444         __u8 low, high;
 445         __u16 wTmp = 0, wTmp1 = 0, wTmp_new = 0;
 446
 447         low = ReadReg(iobase, RX_C_L);
 448         high = ReadReg(iobase, RX_C_H);
 449         wTmp1 = high;
 450         wTmp = (wTmp1 << 8) | low;
 451         udelay(10);
 452         low = ReadReg(iobase, RX_C_L);
 453         high = ReadReg(iobase, RX_C_H);
 454         wTmp1 = high;
 455         wTmp_new = (wTmp1 << 8) | low;
 456         if (wTmp_new != wTmp)
 457                 return 1;
 458         else
 459                 return 0;
 460
 461 }
 462
 463 static __u16 RxCurCount(__u16 iobase, struct via_ircc_cb * self)
 464 {
 465         __u8 low, high;
 466         __u16 wTmp = 0, wTmp1 = 0;
 467
 468         low = ReadReg(iobase, RX_P_L);
 469         high = ReadReg(iobase, RX_P_H);
 470         wTmp1 = high;
 471         wTmp = (wTmp1 << 8) | low;
 472         return wTmp;
 473 }
 474
 475 /* This Routine can only use in recevie_complete
 476  * for it will update last count.
 477  */
 478
 479 static __u16 GetRecvByte(__u16 iobase, struct via_ircc_cb * self)
 480 {
 481         __u8 low, high;
 482         __u16 wTmp, wTmp1, ret;
 483
 484         low = ReadReg(iobase, RX_P_L);
 485         high = ReadReg(iobase, RX_P_H);
 486         wTmp1 = high;
 487         wTmp = (wTmp1 << 8) | low;
 488
 489
 490         if (wTmp >= self->RxLastCount)
 491                 ret = wTmp - self->RxLastCount;
 492         else
 493                 ret = (0x8000 - self->RxLastCount) + wTmp;
 494         self->RxLastCount = wTmp;
 495
 496 /* RX_P is more actually the RX_C
 497  low=ReadReg(iobase,RX_C_L);
 498  high=ReadReg(iobase,RX_C_H);
 499
 500  if(!(high&0xe000)) {
 501          temp=(high<<8)+low;
 502          return temp;
 503  }
 504  else return 0;
 505 */
 506         return ret;
 507 }
 508
 509 static void Sdelay(__u16 scale)
 510 {
 511         __u8 bTmp;
 512         int i, j;
 513
 514         for (j = 0; j < scale; j++) {
 515                 for (i = 0; i < 0x20; i++) {
 516                         bTmp = inb(0xeb);
 517                         outb(bTmp, 0xeb);
 518                 }
 519         }
 520 }
 521
 522 static void Tdelay(__u16 scale)
 523 {
 524         __u8 bTmp;
 525         int i, j;
 526
 527         for (j = 0; j < scale; j++) {
 528                 for (i = 0; i < 0x50; i++) {
 529                         bTmp = inb(0xeb);
 530                         outb(bTmp, 0xeb);
 531                 }
 532         }
 533 }
 534
 535
 536 static void ActClk(__u16 iobase, __u8 value)
 537 {
 538         __u8 bTmp;
 539         bTmp = ReadReg(iobase, 0x34);
 540         if (value)
 541                 WriteReg(iobase, 0x34, bTmp | Clk_bit);
 542         else
 543                 WriteReg(iobase, 0x34, bTmp & ~Clk_bit);
 544 }
 545
 546 static void ClkTx(__u16 iobase, __u8 Clk, __u8 Tx)
 547 {
 548         __u8 bTmp;
 549
 550         bTmp = ReadReg(iobase, 0x34);
 551         if (Clk == 0)
 552                 bTmp &= ~Clk_bit;
 553         else {
 554                 if (Clk == 1)
 555                         bTmp |= Clk_bit;
 556         }
 557         WriteReg(iobase, 0x34, bTmp);
 558         Sdelay(1);
 559         if (Tx == 0)
 560                 bTmp &= ~Tx_bit;
 561         else {
 562                 if (Tx == 1)
 563                         bTmp |= Tx_bit;
 564         }
 565         WriteReg(iobase, 0x34, bTmp);
 566 }
 567
 568 static void Wr_Byte(__u16 iobase, __u8 data)
 569 {
 570         __u8 bData = data;
 571 //      __u8 btmp;
 572         int i;
 573
 574         ClkTx(iobase, 0, 1);
 575
 576         Tdelay(2);
 577         ActClk(iobase, 1);
 578         Tdelay(1);
 579
 580         for (i = 0; i < 8; i++) {       //LDN
 581
 582                 if ((bData >> i) & 0x01) {
 583                         ClkTx(iobase, 0, 1);    //bit data = 1;
 584                 } else {
 585                         ClkTx(iobase, 0, 0);    //bit data = 1;
 586                 }
 587                 Tdelay(2);
 588                 Sdelay(1);
 589                 ActClk(iobase, 1);      //clk hi
 590                 Tdelay(1);
 591         }
 592 }
 593
 594 static __u8 Rd_Indx(__u16 iobase, __u8 addr, __u8 index)
 595 {
 596         __u8 data = 0, bTmp, data_bit;
 597         int i;
 598
 599         bTmp = addr | (index << 1) | 0;
 600         ClkTx(iobase, 0, 0);
 601         Tdelay(2);
 602         ActClk(iobase, 1);
 603         udelay(1);
 604         Wr_Byte(iobase, bTmp);
 605         Sdelay(1);
 606         ClkTx(iobase, 0, 0);
 607         Tdelay(2);
 608         for (i = 0; i < 10; i++) {
 609                 ActClk(iobase, 1);
 610                 Tdelay(1);
 611                 ActClk(iobase, 0);
 612                 Tdelay(1);
 613                 ClkTx(iobase, 0, 1);
 614                 Tdelay(1);
 615                 bTmp = ReadReg(iobase, 0x34);
 616                 if (!(bTmp & Rd_Valid))
 617                         break;
 618         }
 619         if (!(bTmp & Rd_Valid)) {
 620                 for (i = 0; i < 8; i++) {
 621                         ActClk(iobase, 1);
 622                         Tdelay(1);
 623                         ActClk(iobase, 0);
 624                         bTmp = ReadReg(iobase, 0x34);
 625                         data_bit = 1 << i;
 626                         if (bTmp & RxBit)
 627                                 data |= data_bit;
 628                         else
 629                                 data &= ~data_bit;
 630                         Tdelay(2);
 631                 }
 632         } else {
 633                 for (i = 0; i < 2; i++) {
 634                         ActClk(iobase, 1);
 635                         Tdelay(1);
 636                         ActClk(iobase, 0);
 637                         Tdelay(2);
 638                 }
 639                 bTmp = ReadReg(iobase, 0x34);
 640         }
 641         for (i = 0; i < 1; i++) {
 642                 ActClk(iobase, 1);
 643                 Tdelay(1);
 644                 ActClk(iobase, 0);
 645                 Tdelay(2);
 646         }
 647         ClkTx(iobase, 0, 0);
 648         Tdelay(1);
 649         for (i = 0; i < 3; i++) {
 650                 ActClk(iobase, 1);
 651                 Tdelay(1);
 652                 ActClk(iobase, 0);
 653                 Tdelay(2);
 654         }
 655         return data;
 656 }
 657
 658 static void Wr_Indx(__u16 iobase, __u8 addr, __u8 index, __u8 data)
 659 {
 660         int i;
 661         __u8 bTmp;
 662
 663         ClkTx(iobase, 0, 0);
 664         udelay(2);
 665         ActClk(iobase, 1);
 666         udelay(1);
 667         bTmp = addr | (index << 1) | 1;
 668         Wr_Byte(iobase, bTmp);
 669         Wr_Byte(iobase, data);
 670         for (i = 0; i < 2; i++) {
 671                 ClkTx(iobase, 0, 0);
 672                 Tdelay(2);
 673                 ActClk(iobase, 1);
 674                 Tdelay(1);
 675         }
 676         ActClk(iobase, 0);
 677 }
 678
 679 static void ResetDongle(__u16 iobase)
 680 {
 681         int i;
 682         ClkTx(iobase, 0, 0);
 683         Tdelay(1);
 684         for (i = 0; i < 30; i++) {
 685                 ActClk(iobase, 1);
 686                 Tdelay(1);
 687                 ActClk(iobase, 0);
 688                 Tdelay(1);
 689         }
 690         ActClk(iobase, 0);
 691 }
 692
 693 static void SetSITmode(__u16 iobase)
 694 {
 695
 696         __u8 bTmp;
 697
 698         bTmp = ReadLPCReg(0x28);
 699         WriteLPCReg(0x28, bTmp | 0x10); //select ITMOFF
 700         bTmp = ReadReg(iobase, 0x35);
 701         WriteReg(iobase, 0x35, bTmp | 0x40);    // Driver ITMOFF
 702         WriteReg(iobase, 0x28, bTmp | 0x80);    // enable All interrupt
 703 }
 704
 705 static void SI_SetMode(__u16 iobase, int mode)
 706 {
 707         //__u32 dTmp;
 708         __u8 bTmp;
 709
 710         WriteLPCReg(0x28, 0x70);        // S/W Reset
 711         SetSITmode(iobase);
 712         ResetDongle(iobase);
 713         udelay(10);
 714         Wr_Indx(iobase, 0x40, 0x0, 0x17);       //RX ,APEN enable,Normal power
 715         Wr_Indx(iobase, 0x40, 0x1, mode);       //Set Mode
 716         Wr_Indx(iobase, 0x40, 0x2, 0xff);       //Set power to FIR VFIR > 1m
 717         bTmp = Rd_Indx(iobase, 0x40, 1);
 718 }
 719
 720 static void InitCard(__u16 iobase)
 721 {
 722         ResetChip(iobase, 5);
 723         WriteReg(iobase, I_ST_CT_0, 0x00);      // open CHIP on
 724         SetSIRBOF(iobase, 0xc0);        // hardware default value
 725         SetSIREOF(iobase, 0xc1);
 726 }
 727
 728 static void CommonInit(__u16 iobase)
 729 {
 730 //  EnTXCRC(iobase,0);
 731         SwapDMA(iobase, OFF);
 732         SetMaxRxPacketSize(iobase, 0x0fff);     //set to max:4095
 733         EnRXFIFOReadyInt(iobase, OFF);
 734         EnRXFIFOHalfLevelInt(iobase, OFF);
 735         EnTXFIFOHalfLevelInt(iobase, OFF);
 736         EnTXFIFOUnderrunEOMInt(iobase, ON);
 737 //  EnTXFIFOReadyInt(iobase,ON);
 738         InvertTX(iobase, OFF);
 739         InvertRX(iobase, OFF);
 740 //  WriteLPCReg(0xF0,0); //(if VT1211 then do this)
 741         if (IsSIROn(iobase)) {
 742                 SIRFilter(iobase, ON);
 743                 SIRRecvAny(iobase, ON);
 744         } else {
 745                 SIRFilter(iobase, OFF);
 746                 SIRRecvAny(iobase, OFF);
 747         }
 748         EnRXSpecInt(iobase, ON);
 749         WriteReg(iobase, I_ST_CT_0, 0x80);
 750         EnableDMA(iobase, ON);
 751 }
 752
 753 static void SetBaudRate(__u16 iobase, __u32 rate)
 754 {
 755         __u8 value = 11, temp;
 756
 757         if (IsSIROn(iobase)) {
 758                 switch (rate) {
 759                 case (__u32) (2400L):
 760                         value = 47;
 761                         break;
 762                 case (__u32) (9600L):
 763                         value = 11;
 764                         break;
 765                 case (__u32) (19200L):
 766                         value = 5;
 767                         break;
 768                 case (__u32) (38400L):
 769                         value = 2;
 770                         break;
 771                 case (__u32) (57600L):
 772                         value = 1;
 773                         break;
 774                 case (__u32) (115200L):
 775                         value = 0;
 776                         break;
 777                 default:
 778                         break;
 779                 };
 780         } else if (IsMIROn(iobase)) {
 781                 value = 0;      // will automatically be fixed in 1.152M
 782         } else if (IsFIROn(iobase)) {
 783                 value = 0;      // will automatically be fixed in 4M
 784         }
 785         temp = (ReadReg(iobase, I_CF_H_1) & 0x03);
 786         temp |= value << 2;
 787         WriteReg(iobase, I_CF_H_1, temp);
 788 }
 789
 790 static void SetPulseWidth(__u16 iobase, __u8 width)
 791 {
 792         __u8 temp, temp1, temp2;
 793
 794         temp = (ReadReg(iobase, I_CF_L_1) & 0x1f);
 795         temp1 = (ReadReg(iobase, I_CF_H_1) & 0xfc);
 796         temp2 = (width & 0x07) << 5;
 797         temp |= temp2;
 798         temp2 = (width & 0x18) >> 3;
 799         temp1 |= temp2;
 800         WriteReg(iobase, I_CF_L_1, temp);
 801         WriteReg(iobase, I_CF_H_1, temp1);
 802 }
 803
 804 static void SetSendPreambleCount(__u16 iobase, __u8 count)
 805 {
 806         __u8 temp;
 807
 808         temp = ReadReg(iobase, I_CF_L_1) & 0xe0;
 809         temp |= count;
 810         WriteReg(iobase, I_CF_L_1, temp);
 811
 812 }
 813
 814 static void SetVFIR(__u16 BaseAddr, __u8 val)
 815 {
 816         __u8 tmp;
 817
 818         tmp = ReadReg(BaseAddr, I_CF_L_0);
 819         WriteReg(BaseAddr, I_CF_L_0, tmp & 0x8f);
 820         WriteRegBit(BaseAddr, I_CF_H_0, 5, val);
 821 }
 822
 823 static void SetFIR(__u16 BaseAddr, __u8 val)
 824 {
 825         __u8 tmp;
 826
 827         WriteRegBit(BaseAddr, I_CF_H_0, 5, 0);
 828         tmp = ReadReg(BaseAddr, I_CF_L_0);
 829         WriteReg(BaseAddr, I_CF_L_0, tmp & 0x8f);
 830         WriteRegBit(BaseAddr, I_CF_L_0, 6, val);
 831 }
 832
 833 static void SetMIR(__u16 BaseAddr, __u8 val)
 834 {
 835         __u8 tmp;
 836
 837         WriteRegBit(BaseAddr, I_CF_H_0, 5, 0);
 838         tmp = ReadReg(BaseAddr, I_CF_L_0);
 839         WriteReg(BaseAddr, I_CF_L_0, tmp & 0x8f);
 840         WriteRegBit(BaseAddr, I_CF_L_0, 5, val);
 841 }
 842
 843 static void SetSIR(__u16 BaseAddr, __u8 val)
 844 {
 845         __u8 tmp;
 846
 847         WriteRegBit(BaseAddr, I_CF_H_0, 5, 0);
 848         tmp = ReadReg(BaseAddr, I_CF_L_0);
 849         WriteReg(BaseAddr, I_CF_L_0, tmp & 0x8f);
 850         WriteRegBit(BaseAddr, I_CF_L_0, 4, val);
 851 }
 852
 853 #endif                          /* via_IRCC_H */